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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [addv3.cgs] - Blame information for rev 272

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# m32r testcase for addv3 $dr,$sr,#$simm16
# mach(): m32r m32rx
 
        .include "testutils.inc"
 
        start
 
        .global addv3
addv3:
        mvi_h_condbit 0
        mvi_h_gr r4, 1
        mvi_h_gr r5, 1
 
        addv3 r4, r5, #2
 
        bc not_ok
 
        test_h_gr r4, 3
 
        mvi_h_gr r5, 0x7fff8001
 
        addv3 r4, r5, #0x7fff
 
        bnc not_ok
 
        pass
not_ok:
        fail

Line No.	Rev	Author	Line
1	24	jeremybenn	`# m32r testcase for addv3 $dr,$sr,#$simm16`
2			`# mach(): m32r m32rx`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global addv3`
9			`addv3:`
10			`mvi_h_condbit 0`
11			`mvi_h_gr r4, 1`
12			`mvi_h_gr r5, 1`
13
14			`addv3 r4, r5, #2`
15
16			`bc not_ok`
17
18			`test_h_gr r4, 3`
19
20			`mvi_h_gr r5, 0x7fff8001`
21
22			`addv3 r4, r5, #0x7fff`
23
24			`bnc not_ok`
25
26			`pass`
27			`not_ok:`
28			`fail`

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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [addv3.cgs] - Blame information for rev 272