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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [bc24.cgs] - Blame information for rev 272

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# m32r testcase for bc $disp24
# mach(): m32r m32rx
 
        .include "testutils.inc"
 
        start
 
        .global bc24
bc24:
 
        mvi_h_condbit 0
        bc.l test0fail
        bra test0pass
test0fail:
        fail
test0pass:
 
        mvi_h_condbit 1
        bc.l test1pass
        fail
test1pass:
 
        pass
 

Line No.	Rev	Author	Line
1	24	jeremybenn	`# m32r testcase for bc $disp24`
2			`# mach(): m32r m32rx`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global bc24`
9			`bc24:`
10
11			`mvi_h_condbit 0`
12			`bc.l test0fail`
13			`bra test0pass`
14			`test0fail:`
15			`fail`
16			`test0pass:`
17
18			`mvi_h_condbit 1`
19			`bc.l test1pass`
20			`fail`
21			`test1pass:`
22
23			`pass`
24

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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [bc24.cgs] - Blame information for rev 272