URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [bnc24.cgs] - Blame information for rev 24

Go to most recent revision | Details | Compare with Previous | View Log


# m32r testcase for bnc $disp24
# mach(): m32r m32rx
 
        .include "testutils.inc"
 
        start
 
        .global bnc24
bnc24:
        mvi_h_condbit 0
        bnc.l test0pass
 
test1fail:
        fail
test0pass:
 
        mvi_h_condbit 1
        bnc.l test1fail
 
        pass

Line No.	Rev	Author	Line
1	24	jeremybenn	`# m32r testcase for bnc $disp24`
2			`# mach(): m32r m32rx`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global bnc24`
9			`bnc24:`
10			`mvi_h_condbit 0`
11			`bnc.l test0pass`
12
13			`test1fail:`
14			`fail`
15			`test0pass:`
16
17			`mvi_h_condbit 1`
18			`bnc.l test1fail`
19
20			`pass`

Browse

Tools

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [bnc24.cgs] - Blame information for rev 24