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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [cmpu.cgs] - Blame information for rev 24

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# m32r testcase for cmpu $src1,$src2
# mach(): m32r m32rx
 
        .include "testutils.inc"
 
        start
 
        .global cmpu
cmpu:
        mvi_h_condbit 0
        mvi_h_gr r4, 1
        mvi_h_gr r5, -2
        cmpu r4, r5
        bc ok
not_ok:
        fail
ok:
        mvi_h_condbit 1
        mvi_h_gr r4, -1
        cmpu r4, r5
        bc not_ok
 
        pass

Line No.	Rev	Author	Line
1	24	jeremybenn	`# m32r testcase for cmpu $src1,$src2`
2			`# mach(): m32r m32rx`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global cmpu`
9			`cmpu:`
10			`mvi_h_condbit 0`
11			`mvi_h_gr r4, 1`
12			`mvi_h_gr r5, -2`
13			`cmpu r4, r5`
14			`bc ok`
15			`not_ok:`
16			`fail`
17			`ok:`
18			`mvi_h_condbit 1`
19			`mvi_h_gr r4, -1`
20			`cmpu r4, r5`
21			`bc not_ok`
22
23			`pass`

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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [cmpu.cgs] - Blame information for rev 24