OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [ld-plus.cgs] - Blame information for rev 272

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# m32r testcase for ld $dr,@$sr+
2
# mach(): m32r m32rx
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global ld_plus
9
ld_plus:
10
        mvaddr_h_gr r4, data_loc
11
        mvi_h_gr    r5, 0
12
 
13
        ld r5, @r4+
14
 
15
        test_h_gr r5, 0x12345678
16
 
17
        mvaddr_h_gr r5, data_loc2
18
        bne r4, r5, not_ok
19
 
20
        pass
21
not_ok:
22
        fail
23
 
24
data_loc:
25
        .word 0x12345678
26
data_loc2:
27
        .word 0x11223344
28
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.