URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [lock.cgs] - Blame information for rev 157

Details | Compare with Previous | View Log


# m32r testcase for lock $dr,@$sr
# mach(): m32r m32rx
 
        .include "testutils.inc"
 
        start
 
        .global lock
lock:
        mvaddr_h_gr r4, data_loc
        mvi_h_gr    r5, 0
 
        lock r5, @r4
 
        test_h_gr r5, 0x12345678
 
        ; There is no way to test the lock bit
 
        unlock r5, @r4  ; Unlock the processor
 
        pass
 
data_loc:
        .word 0x12345678
 

Line No.	Rev	Author	Line
1	24	jeremybenn	`# m32r testcase for lock $dr,@$sr`
2			`# mach(): m32r m32rx`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global lock`
9			`lock:`
10			`mvaddr_h_gr r4, data_loc`
11			`mvi_h_gr r5, 0`
12
13			`lock r5, @r4`
14
15			`test_h_gr r5, 0x12345678`
16
17			`; There is no way to test the lock bit`
18
19			`unlock r5, @r4 ; Unlock the processor`
20
21			`pass`
22
23			`data_loc:`
24			`.word 0x12345678`
25

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [lock.cgs] - Blame information for rev 157