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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [unlock.cgs] - Blame information for rev 272

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# m32r testcase for unlock $src1,@$src2
# mach(): m32r m32rx
 
        .include "testutils.inc"
 
        start
 
        .global unlock
unlock:
        mvaddr_h_gr r4, data_loc
        mvi_h_gr    r5, 1
 
        lock r5, @r4
 
        mvi_h_gr r5, 2
        unlock r5, @r4
 
        ld r6, @r4
        test_h_gr r6, 2
 
        mvi_h_gr r5, 0
        unlock r5, @r4  ; This should be a nop since the processor should be unlocked.
 
        ld r6, @r4
        test_h_gr r6, 2
 
        pass
 
data_loc:
        .word 0

Line No.	Rev	Author	Line
1	24	jeremybenn	`# m32r testcase for unlock $src1,@$src2`
2			`# mach(): m32r m32rx`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global unlock`
9			`unlock:`
10			`mvaddr_h_gr r4, data_loc`
11			`mvi_h_gr r5, 1`
12
13			`lock r5, @r4`
14
15			`mvi_h_gr r5, 2`
16			`unlock r5, @r4`
17
18			`ld r6, @r4`
19			`test_h_gr r6, 2`
20
21			`mvi_h_gr r5, 0`
22			`unlock r5, @r4 ; This should be a nop since the processor should be unlocked.`
23
24			`ld r6, @r4`
25			`test_h_gr r6, 2`
26
27			`pass`
28
29			`data_loc:`
30			`.word 0`

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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [m32r/] [unlock.cgs] - Blame information for rev 272