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# sh testcase for fabs
# mach: sh
# as(sh):       -defsym sim_cpu=0
 
        .include "testutils.inc"
 
        start
fabs_freg_b0:
        single_prec
        bank0
        set_grs_a5a5
        set_fprs_a5a5
        # fabs(0.0) = 0.0.
        fldi0   fr0
        fabs    fr0
        fldi0   fr1
        fcmp/eq fr0, fr1
        bt      .L1
        fail
.L1:
        # fabs(1.0) = 1.0.
        fldi1   fr0
        fabs    fr0
        fldi1   fr1
        fcmp/eq fr0, fr1
        bt      .L2
        fail
.L2:
        # fabs(-1.0) = 1.0.
        fldi1   fr0
        fneg    fr0
        fabs    fr0
        fldi1   fr1
        fcmp/eq fr0, fr1
        bt      .L3
        fail
.L3:
        test_grs_a5a5
        test_fpr_a5a5 fr2
        test_fpr_a5a5 fr3
        test_fpr_a5a5 fr4
        test_fpr_a5a5 fr5
        test_fpr_a5a5 fr6
        test_fpr_a5a5 fr7
        test_fpr_a5a5 fr8
        test_fpr_a5a5 fr9
        test_fpr_a5a5 fr10
        test_fpr_a5a5 fr11
        test_fpr_a5a5 fr12
        test_fpr_a5a5 fr13
        test_fpr_a5a5 fr14
        test_fpr_a5a5 fr15
 
fabs_dreg_b0:
        # double precision tests.
        set_grs_a5a5
        set_fprs_a5a5
        double_prec
        # fabs(0.0) = 0.0.
        fldi0   fr0
        flds    fr0, fpul
        fcnvsd  fpul, dr0
        fabs dr0
        assert_dpreg_i 0 dr0
 
        # fabs(1.0) = 1.0.
        fldi1   fr0
        flds    fr0, fpul
        fcnvsd  fpul, dr0
        fabs dr0
        assert_dpreg_i 1 dr0
 
        # check.
        fldi1 fr2
        flds    fr2, fpul
        fcnvsd  fpul, dr2
        fcmp/eq dr0, dr2
        bt      .L4
        fail
 
.L4:
        # fabs(-1.0) = 1.0.
        fldi1 fr0
        fneg fr0
        flds    fr0, fpul
        fcnvsd  fpul, dr0
        fabs dr0
        assert_dpreg_i 1 dr0
 
        # check.
        fldi1 fr2
        flds    fr2, fpul
        fcnvsd  fpul, dr2
        fcmp/eq dr0, dr2
        bt      .L5
        fail
.L5:
        test_grs_a5a5
        assert_dpreg_i 1 dr0
        assert_dpreg_i 1 dr2
        test_fpr_a5a5 fr4
        test_fpr_a5a5 fr5
        test_fpr_a5a5 fr6
        test_fpr_a5a5 fr7
        test_fpr_a5a5 fr8
        test_fpr_a5a5 fr9
        test_fpr_a5a5 fr10
        test_fpr_a5a5 fr11
        test_fpr_a5a5 fr12
        test_fpr_a5a5 fr13
        test_fpr_a5a5 fr14
        test_fpr_a5a5 fr15
 
        pass
        exit 0

Line No.	Rev	Author	Line
1	24	jeremybenn	`# sh testcase for fabs`
2			`# mach: sh`
3			`# as(sh): -defsym sim_cpu=0`
4
5			`.include "testutils.inc"`
6
7			`start`
8			`fabs_freg_b0:`
9			`single_prec`
10			`bank0`
11			`set_grs_a5a5`
12			`set_fprs_a5a5`
13			`# fabs(0.0) = 0.0.`
14			`fldi0 fr0`
15			`fabs fr0`
16			`fldi0 fr1`
17			`fcmp/eq fr0, fr1`
18			`bt .L1`
19			`fail`
20			`.L1:`
21			`# fabs(1.0) = 1.0.`
22			`fldi1 fr0`
23			`fabs fr0`
24			`fldi1 fr1`
25			`fcmp/eq fr0, fr1`
26			`bt .L2`
27			`fail`
28			`.L2:`
29			`# fabs(-1.0) = 1.0.`
30			`fldi1 fr0`
31			`fneg fr0`
32			`fabs fr0`
33			`fldi1 fr1`
34			`fcmp/eq fr0, fr1`
35			`bt .L3`
36			`fail`
37			`.L3:`
38			`test_grs_a5a5`
39			`test_fpr_a5a5 fr2`
40			`test_fpr_a5a5 fr3`
41			`test_fpr_a5a5 fr4`
42			`test_fpr_a5a5 fr5`
43			`test_fpr_a5a5 fr6`
44			`test_fpr_a5a5 fr7`
45			`test_fpr_a5a5 fr8`
46			`test_fpr_a5a5 fr9`
47			`test_fpr_a5a5 fr10`
48			`test_fpr_a5a5 fr11`
49			`test_fpr_a5a5 fr12`
50			`test_fpr_a5a5 fr13`
51			`test_fpr_a5a5 fr14`
52			`test_fpr_a5a5 fr15`
53
54			`fabs_dreg_b0:`
55			`# double precision tests.`
56			`set_grs_a5a5`
57			`set_fprs_a5a5`
58			`double_prec`
59			`# fabs(0.0) = 0.0.`
60			`fldi0 fr0`
61			`flds fr0, fpul`
62			`fcnvsd fpul, dr0`
63			`fabs dr0`
64			`assert_dpreg_i 0 dr0`
65
66			`# fabs(1.0) = 1.0.`
67			`fldi1 fr0`
68			`flds fr0, fpul`
69			`fcnvsd fpul, dr0`
70			`fabs dr0`
71			`assert_dpreg_i 1 dr0`
72
73			`# check.`
74			`fldi1 fr2`
75			`flds fr2, fpul`
76			`fcnvsd fpul, dr2`
77			`fcmp/eq dr0, dr2`
78			`bt .L4`
79			`fail`
80
81			`.L4:`
82			`# fabs(-1.0) = 1.0.`
83			`fldi1 fr0`
84			`fneg fr0`
85			`flds fr0, fpul`
86			`fcnvsd fpul, dr0`
87			`fabs dr0`
88			`assert_dpreg_i 1 dr0`
89
90			`# check.`
91			`fldi1 fr2`
92			`flds fr2, fpul`
93			`fcnvsd fpul, dr2`
94			`fcmp/eq dr0, dr2`
95			`bt .L5`
96			`fail`
97			`.L5:`
98			`test_grs_a5a5`
99			`assert_dpreg_i 1 dr0`
100			`assert_dpreg_i 1 dr2`
101			`test_fpr_a5a5 fr4`
102			`test_fpr_a5a5 fr5`
103			`test_fpr_a5a5 fr6`
104			`test_fpr_a5a5 fr7`
105			`test_fpr_a5a5 fr8`
106			`test_fpr_a5a5 fr9`
107			`test_fpr_a5a5 fr10`
108			`test_fpr_a5a5 fr11`
109			`test_fpr_a5a5 fr12`
110			`test_fpr_a5a5 fr13`
111			`test_fpr_a5a5 fr14`
112			`test_fpr_a5a5 fr15`
113
114			`pass`
115			`exit 0`

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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh/] [fabs.s] - Blame information for rev 301