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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh/] [fdiv.s] - Blame information for rev 225

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Line No. Rev Author Line
1 24 jeremybenn
# sh testcase for fdiv
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# mach: sh
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# as(sh):       -defsym sim_cpu=0
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        .include "testutils.inc"
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        start
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fdiv_single:
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        # Single test
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        set_grs_a5a5
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        set_fprs_a5a5
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        single_prec
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        # 1.0 / 0.0 should be INF
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        # (and not crash the sim).
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        fldi0   fr0
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        fldi1   fr1
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        fdiv    fr0, fr1
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        assert_fpreg_x  0x7f800000, fr1
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        # 0.0 / 1.0 == 0.0.
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        fldi0   fr0
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        fldi1   fr1
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        fdiv    fr1, fr0
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        assert_fpreg_x  0, fr0
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        # 2.0 / 1.0 == 2.0.
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        fldi1   fr1
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        fldi1   fr2
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        fadd    fr2, fr2
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        fdiv    fr1, fr2
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        assert_fpreg_i  2, fr2
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        # (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
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        fldi1   fr1
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        fldi1   fr2
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        fadd    fr2, fr2
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        fdiv    fr2, fr1
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        # fr1 should contain 0.5.
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        fadd    fr1, fr1
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        assert_fpreg_i  1, fr1
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        test_grs_a5a5
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        assert_fpreg_i  2, fr2
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        test_fpr_a5a5   fr3
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        test_fpr_a5a5   fr4
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        test_fpr_a5a5   fr5
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        test_fpr_a5a5   fr6
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        test_fpr_a5a5   fr7
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        test_fpr_a5a5   fr8
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        test_fpr_a5a5   fr9
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        test_fpr_a5a5   fr10
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        test_fpr_a5a5   fr11
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        test_fpr_a5a5   fr12
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        test_fpr_a5a5   fr13
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        test_fpr_a5a5   fr14
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        test_fpr_a5a5   fr15
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fdiv_double:
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        # Double test
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        set_grs_a5a5
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        set_fprs_a5a5
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        # (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
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        fldi1   fr1
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        fldi1   fr2
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        # This add must be in single precision.  The rest must be in double.
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        fadd    fr2, fr2
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        double_prec
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        _s2d    fr1, dr0
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        _s2d    fr2, dr2
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        fdiv    dr2, dr0
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        # dr0 should contain 0.5.
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        # double it, expect 1.0.
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        fadd    dr0, dr0
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        assert_dpreg_i  1, dr0
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        assert_dpreg_i  2, dr2
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        test_grs_a5a5
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        test_fpr_a5a5   fr4
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        test_fpr_a5a5   fr5
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        test_fpr_a5a5   fr6
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        test_fpr_a5a5   fr7
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        test_fpr_a5a5   fr8
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        test_fpr_a5a5   fr9
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        test_fpr_a5a5   fr10
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        test_fpr_a5a5   fr11
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        test_fpr_a5a5   fr12
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        test_fpr_a5a5   fr13
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        test_fpr_a5a5   fr14
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        test_fpr_a5a5   fr15
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        pass
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        exit 0
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