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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh/] [fmov.s] - Blame information for rev 225

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Line No. Rev Author Line
1 24 jeremybenn
# sh testcase for all fmov instructions
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# mach: sh
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# as(sh):       -defsym sim_cpu=0
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        .include "testutils.inc"
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        .macro init
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        fldi0   fr0
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        fldi1   fr1
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        fldi1   fr2
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        fldi1   fr3
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        .endm
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        start
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fmov1:  # Test fr -> fr.
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        set_grs_a5a5
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        set_fprs_a5a5
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        init
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        single_prec
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        sz_32
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        fmov    fr0, fr1
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        # Ensure fr0 and fr1 are now equal.
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        fcmp/eq fr0, fr1
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        bt      fmov2
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        fail
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fmov2:  # Test dr -> dr.
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        init
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        double_prec
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        sz_64
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        fmov    dr0, dr2
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        # Ensure dr0 and dr2 are now equal.
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        fcmp/eq dr0, dr2
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        bt      fmov3
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        fail
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fmov3:  # Test dr -> xd and xd -> dr.
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        init
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        sz_64
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        fmov    dr0, xd0
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        # Ensure dr0 and xd0 are now equal.
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        fmov    xd0, dr2
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        fcmp/eq dr0, dr2
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        bt      fmov4
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        fail
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fmov4:  # Test xd -> xd.
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        init
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        sz_64
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        double_prec
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        fmov    dr0, xd0
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        fmov    xd0, xd2
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        fmov    xd2, dr2
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        # Ensure dr0 and dr2 are now equal.
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        fcmp/eq dr0, dr2
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        bt      .L0
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        fail
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        # FIXME: test fmov.s fr -> @gr,      fmov dr -> @gr
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        # FIXME: test fmov.s @gr -> fr,      fmov @gr -> dr
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        # FIXME: test fmov.s @gr+ -> fr,     fmov @gr+ -> dr
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        # FIXME: test fmov.s fr -> @-gr,     fmov dr -> @-gr
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        # FIXME: test fmov.s @(r0,gr) -> fr, fmov @(r0,gr) -> dr
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        # FIXME: test fmov.s fr -> @(r0,gr), fmov dr -> @(r0,gr)
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.L0:
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        test_grs_a5a5
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        sz_32
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        single_prec
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        assert_fpreg_i  0, fr0
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        assert_fpreg_i  1, fr1
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        assert_fpreg_i  0, fr2
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        assert_fpreg_i  1, fr3
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        test_fpr_a5a5   fr4
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        test_fpr_a5a5   fr5
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        test_fpr_a5a5   fr6
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        test_fpr_a5a5   fr7
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        test_fpr_a5a5   fr8
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        test_fpr_a5a5   fr9
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        test_fpr_a5a5   fr10
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        test_fpr_a5a5   fr11
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        test_fpr_a5a5   fr12
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        test_fpr_a5a5   fr13
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        test_fpr_a5a5   fr14
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        test_fpr_a5a5   fr15
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fmov5:  # Test fr -> @rn and @rn -> fr.
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        init
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        sz_32
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        single_prec
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        # FIXME!  Use a reserved memory location!
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        mov     #40, r0
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        shll8   r0
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        fmov    fr0, @r0
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        fmov    @r0, fr1
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        fcmp/eq fr0, fr1
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        bt      fmov6
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        fail
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fmov6:  # Test dr -> @rn and @rn -> dr.
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        init
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        sz_64
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        double_prec
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        mov     #40, r0
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        shll8   r0
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        fmov    dr0, @r0
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        fmov    @r0, dr2
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        fcmp/eq dr0, dr2
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        bt      fmov7
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        fail
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fmov7:  # Test xd -> @rn and @rn -> xd.
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        init
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        sz_64
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        double_prec
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        mov     #40, r0
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        shll8   r0
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        fmov    dr0, xd0
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        fmov    xd0, @r0
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        fmov    @r0, xd2
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        fmov    xd2, dr2
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        fcmp/eq dr0, dr2
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        bt      fmov8
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        fail
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fmov8:  # Test fr -> @-rn.
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        init
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        sz_32
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        single_prec
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        mov     #40, r0
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        shll8   r0
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        # Preserve.
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        mov     r0, r1
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        fmov    fr0, @-r0
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        fmov    @r0, fr2
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        fcmp/eq fr0, fr2
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        bt      f8b
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        fail
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f8b:    # check pre-dec.
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        add     #4, r0
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        cmp/eq  r0, r1
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        bt      fmov9
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        fail
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fmov9:  # Test dr -> @-rn.
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        init
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        sz_64
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        double_prec
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        mov     #40, r0
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        shll8   r0
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        # Preserve r0.
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        mov     r0, r1
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        fmov    dr0, @-r0
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        fmov    @r0, dr2
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        fcmp/eq dr0, dr2
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        bt      f9b
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        fail
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f9b:    # check pre-dec.
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        add     #8, r0
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        cmp/eq  r0, r1
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        bt      fmov10
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        fail
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fmov10: # Test xd -> @-rn.
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        init
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        sz_64
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        double_prec
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        mov     #40, r0
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        shll8   r0
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        # Preserve r0.
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        mov     r0, r1
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        fmov    dr0, xd0
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        fmov    xd0, @-r0
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        fmov    @r0, xd2
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        fmov    xd2, dr2
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        fcmp/eq dr0, dr2
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        bt      f10b
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        fail
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f10b:   # check pre-dec.
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        add     #8, r0
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        cmp/eq  r0, r1
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        bt      fmov11
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        fail
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fmov11: # Test @rn+ -> fr.
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        init
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        sz_32
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        single_prec
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        mov     #40, r0
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        shll8   r0
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        # Preserve r0.
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        mov     r0, r1
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        fmov    fr0, @r0
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        fmov    @r0+, fr2
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        fcmp/eq fr0, fr2
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        bt      f11b
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        fail
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f11b:   # check post-inc.
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        add     #4, r1
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        cmp/eq  r0, r1
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        bt      fmov12
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        fail
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fmov12: # Test @rn+ -> dr.
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        init
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        sz_64
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        double_prec
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        mov     #40, r0
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        shll8   r0
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        # preserve r0.
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        mov     r0, r1
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        fmov    dr0, @r0
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        fmov    @r0+, dr2
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        fcmp/eq dr0, dr2
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        bt      f12b
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        fail
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f12b:   # check post-inc.
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        add     #8, r1
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        cmp/eq  r0, r1
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        bt      fmov13
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        fail
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fmov13: # Test @rn -> xd.
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        init
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        sz_64
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        double_prec
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        mov     #40, r0
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        shll8   r0
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        # Preserve r0.
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        mov     r0, r1
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        fmov    dr0, xd0
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        fmov    xd0, @r0
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        fmov    @r0+, xd2
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        fmov    xd2, dr2
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        fcmp/eq dr0, dr2
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        bt      f13b
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        fail
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f13b:
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        add     #8, r1
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        cmp/eq  r0, r1
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        bt      fmov14
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        fail
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fmov14: # Test fr -> @(r0,rn), @(r0, rn) -> fr.
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        init
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        sz_32
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        single_prec
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        mov     #40, r0
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        shll8   r0
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        mov     #0, r1
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        fmov    fr0, @(r0, r1)
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        fmov    @(r0, r1), fr1
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        fcmp/eq fr0, fr1
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        bt      fmov15
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        fail
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fmov15: # Test dr -> @(r0, rn), @(r0, rn) -> dr.
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        init
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        sz_64
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        double_prec
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        mov     #40, r0
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        shll8   r0
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        mov     #0, r1
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        fmov    dr0, @(r0, r1)
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        fmov    @(r0, r1), dr2
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        fcmp/eq dr0, dr2
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        bt      fmov16
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        fail
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fmov16: # Test xd -> @(r0, rn), @(r0, rn) -> xd.
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        init
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        sz_64
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        double_prec
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        mov     #40, r0
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        shll8   r0
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        mov     #0, r1
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        fmov    dr0, xd0
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        fmov    xd0, @(r0, r1)
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        fmov    @(r0, r1), xd2
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        fmov    xd2, dr2
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        fcmp/eq dr0, dr2
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        bt      .L1
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        fail
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.L1:
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        assertreg0      0x2800
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        assertreg       0, r1
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        test_gr_a5a5    r2
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        test_gr_a5a5    r3
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        test_gr_a5a5    r4
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        test_gr_a5a5    r5
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        test_gr_a5a5    r6
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        test_gr_a5a5    r7
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        test_gr_a5a5    r8
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        test_gr_a5a5    r9
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        test_gr_a5a5    r10
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        test_gr_a5a5    r11
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        test_gr_a5a5    r12
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        test_gr_a5a5    r13
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        test_gr_a5a5    r14
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        sz_32
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        single_prec
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        assert_fpreg_i  0, fr0
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        assert_fpreg_i  1, fr1
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        assert_fpreg_i  0, fr2
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        assert_fpreg_i  1, fr3
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        test_fpr_a5a5   fr4
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        test_fpr_a5a5   fr5
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        test_fpr_a5a5   fr6
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        test_fpr_a5a5   fr7
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        test_fpr_a5a5   fr8
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        test_fpr_a5a5   fr9
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        test_fpr_a5a5   fr10
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        test_fpr_a5a5   fr11
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        test_fpr_a5a5   fr12
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        test_fpr_a5a5   fr13
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        test_fpr_a5a5   fr14
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        test_fpr_a5a5   fr15
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        pass
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        exit 0

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