OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh/] [pushpop.s] - Blame information for rev 157

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# sh testcase for push/pop (mov,movml,movmu...) insns.
2
# mach:  all
3
# as(sh):       -defsym sim_cpu=0
4
# as(shdsp):    -defsym sim_cpu=1 -dsp
5
 
6
        .include "testutils.inc"
7
 
8
        start
9
movml_1:
10
        set_greg 0, r0
11
        set_greg 1, r1
12
        set_greg 2, r2
13
        set_greg 3, r3
14
        set_greg 4, r4
15
        set_greg 5, r5
16
        set_greg 6, r6
17
        set_greg 7, r7
18
        set_greg 8, r8
19
        set_greg 9, r9
20
        set_greg 10, r10
21
        set_greg 11, r11
22
        set_greg 12, r12
23
        set_greg 13, r13
24
        set_greg 14, r14
25
        set_sreg 15, pr
26
 
27
        movml.l         r15,@-r15
28
 
29
        assertmem       stackt-4,  15
30
        assertmem       stackt-8,  14
31
        assertmem       stackt-12, 13
32
        assertmem       stackt-16, 12
33
        assertmem       stackt-20, 11
34
        assertmem       stackt-24, 10
35
        assertmem       stackt-28, 9
36
        assertmem       stackt-32, 8
37
        assertmem       stackt-36, 7
38
        assertmem       stackt-40, 6
39
        assertmem       stackt-44, 5
40
        assertmem       stackt-48, 4
41
        assertmem       stackt-52, 3
42
        assertmem       stackt-56, 2
43
        assertmem       stackt-60, 1
44
        assertmem       stackt-64, 0
45
 
46
        assertreg0      0
47
        assertreg       1, r1
48
        assertreg       2, r2
49
        assertreg       3, r3
50
        assertreg       4, r4
51
        assertreg       5, r5
52
        assertreg       6, r6
53
        assertreg       7, r7
54
        assertreg       8, r8
55
        assertreg       9, r9
56
        assertreg       10, r10
57
        assertreg       11, r11
58
        assertreg       12, r12
59
        assertreg       13, r13
60
        assertreg       14, r14
61
        mov             r15, r0
62
        assertreg0      stackt-64
63
 
64
movml_2:
65
        set_grs_a5a5
66
        movml.l         @r15+, r15
67
        assert_sreg     15, pr
68
        assertreg0      0
69
        assertreg       1, r1
70
        assertreg       2, r2
71
        assertreg       3, r3
72
        assertreg       4, r4
73
        assertreg       5, r5
74
        assertreg       6, r6
75
        assertreg       7, r7
76
        assertreg       8, r8
77
        assertreg       9, r9
78
        assertreg       10, r10
79
        assertreg       11, r11
80
        assertreg       12, r12
81
        assertreg       13, r13
82
        assertreg       14, r14
83
        mov             r15, r0
84
        assertreg0      stackt
85
 
86
movmu_1:
87
        set_grs_a5a5
88
        add     #1,r14
89
        add     #2,r13
90
        add     #3,r12
91
        set_sreg 0xa5a5,pr
92
 
93
        movmu.l r12,@-r15
94
 
95
        assert_sreg     0xa5a5,pr
96
        assertreg       0xa5a5a5a6, r14
97
        assertreg       0xa5a5a5a7, r13
98
        assertreg       0xa5a5a5a8, r12
99
        test_gr_a5a5    r11
100
        test_gr_a5a5    r10
101
        test_gr_a5a5    r9
102
        test_gr_a5a5    r8
103
        test_gr_a5a5    r7
104
        test_gr_a5a5    r6
105
        test_gr_a5a5    r5
106
        test_gr_a5a5    r4
107
        test_gr_a5a5    r3
108
        test_gr_a5a5    r2
109
        test_gr_a5a5    r1
110
        test_gr_a5a5    r0
111
        mov     r15, r0
112
        assertreg       stackt-16, r0
113
 
114
        assertmem       stackt-4, 0xa5a5
115
        assertmem       stackt-8, 0xa5a5a5a6
116
        assertmem       stackt-12, 0xa5a5a5a7
117
        assertmem       stackt-16, 0xa5a5a5a8
118
 
119
movmu_2:
120
        set_grs_a5a5
121
        movmu.l         @r15+,r12
122
 
123
        assert_sreg     0xa5a5, pr
124
        assertreg       0xa5a5a5a6, r14
125
        assertreg       0xa5a5a5a7, r13
126
        assertreg       0xa5a5a5a8, r12
127
        test_gr_a5a5    r11
128
        test_gr_a5a5    r10
129
        test_gr_a5a5    r9
130
        test_gr_a5a5    r8
131
        test_gr_a5a5    r7
132
        test_gr_a5a5    r6
133
        test_gr_a5a5    r5
134
        test_gr_a5a5    r4
135
        test_gr_a5a5    r3
136
        test_gr_a5a5    r2
137
        test_gr_a5a5    r1
138
        test_gr_a5a5    r0
139
        mov     r15, r0
140
        assertreg       stackt, r0
141
 
142
        pass
143
 
144
        exit 0
145
 
146
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.