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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh/] [resbank.s] - Blame information for rev 300

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# sh testcase for ldbank stbank resbank
# mach:  all
# as(sh):       -defsym sim_cpu=0
# as(shdsp):    -defsym sim_cpu=1 -dsp
 
        .include "testutils.inc"
 
        .macro  SEND reg bankno regno
        set_greg ((\bankno << 7) + (\regno << 2)), \reg
        .endm
 
        start
 
stbank_1:
        set_grs_a5a5
        mov     #0, r0
        SEND    r1, 0, 0
        stbank  r0, @r1
        mov     #1, r0
        SEND    r1, 0, 1
        stbank  r0, @r1
        mov     #2, r0
        SEND    r1, 0, 2
        stbank  r0, @r1
        mov     #3, r0
        SEND    r1, 0, 3
        stbank  r0, @r1
        mov     #4, r0
        SEND    r1, 0, 4
        stbank  r0, @r1
        mov     #5, r0
        SEND    r1, 0, 5
        stbank  r0, @r1
        mov     #6, r0
        SEND    r1, 0, 6
        stbank  r0, @r1
        mov     #7, r0
        SEND    r1, 0, 7
        stbank  r0, @r1
        mov     #8, r0
        SEND    r1, 0, 8
        stbank  r0, @r1
        mov     #9, r0
        SEND    r1, 0, 9
        stbank  r0, @r1
        mov     #10, r0
        SEND    r1, 0, 10
        stbank  r0, @r1
        mov     #11, r0
        SEND    r1, 0, 11
        stbank  r0, @r1
        mov     #12, r0
        SEND    r1, 0, 12
        stbank  r0, @r1
        mov     #13, r0
        SEND    r1, 0, 13
        stbank  r0, @r1
        mov     #14, r0
        SEND    r1, 0, 14
        stbank  r0, @r1
        mov     #15, r0
        SEND    r1, 0, 15
        stbank  r0, @r1
        mov     #16, r0
        SEND    r1, 0, 16
        stbank  r0, @r1
        mov     #17, r0
        SEND    r1, 0, 17
        stbank  r0, @r1
        mov     #18, r0
        SEND    r1, 0, 18
        stbank  r0, @r1
        mov     #19, r0
        SEND    r1, 0, 19
        stbank  r0, @r1
 
        assertreg0      19
        assertreg       19 << 2, r1
        test_gr_a5a5    r2
        test_gr_a5a5    r3
        test_gr_a5a5    r4
        test_gr_a5a5    r5
        test_gr_a5a5    r6
        test_gr_a5a5    r7
        test_gr_a5a5    r8
        test_gr_a5a5    r9
        test_gr_a5a5    r10
        test_gr_a5a5    r11
        test_gr_a5a5    r12
        test_gr_a5a5    r13
        test_gr_a5a5    r14
 
ldbank_1:
        set_grs_a5a5
        SEND    r1, 0, 0
        ldbank  @r1, r0
        assertreg0 0
        SEND    r1, 0, 1
        ldbank  @r1, r0
        assertreg0 1
        SEND    r1, 0, 2
        ldbank  @r1, r0
        assertreg0 2
        SEND    r1, 0, 3
        ldbank  @r1, r0
        assertreg0 3
        SEND    r1, 0, 4
        ldbank  @r1, r0
        assertreg0 4
        SEND    r1, 0, 5
        ldbank  @r1, r0
        assertreg0 5
        SEND    r1, 0, 6
        ldbank  @r1, r0
        assertreg0 6
        SEND    r1, 0, 7
        ldbank  @r1, r0
        assertreg0 7
        SEND    r1, 0, 8
        ldbank  @r1, r0
        assertreg0 8
        SEND    r1, 0, 9
        ldbank  @r1, r0
        assertreg0 9
        SEND    r1, 0, 10
        ldbank  @r1, r0
        assertreg0 10
        SEND    r1, 0, 11
        ldbank  @r1, r0
        assertreg0 11
        SEND    r1, 0, 12
        ldbank  @r1, r0
        assertreg0 12
        SEND    r1, 0, 13
        ldbank  @r1, r0
        assertreg0 13
        SEND    r1, 0, 14
        ldbank  @r1, r0
        assertreg0 14
        SEND    r1, 0, 15
        ldbank  @r1, r0
        assertreg0 15
        SEND    r1, 0, 16
        ldbank  @r1, r0
        assertreg0 16
        SEND    r1, 0, 17
        ldbank  @r1, r0
        assertreg0 17
        SEND    r1, 0, 18
        ldbank  @r1, r0
        assertreg0 18
        SEND    r1, 0, 19
        ldbank  @r1, r0
        assertreg0 19
 
        assertreg (19 << 2), r1
        test_gr_a5a5 r2
        test_gr_a5a5 r3
        test_gr_a5a5 r4
        test_gr_a5a5 r5
        test_gr_a5a5 r6
        test_gr_a5a5 r7
        test_gr_a5a5 r8
        test_gr_a5a5 r9
        test_gr_a5a5 r10
        test_gr_a5a5 r11
        test_gr_a5a5 r12
        test_gr_a5a5 r13
        test_gr_a5a5 r14
 
resbank_1:
        set_grs_a5a5
        mov     #1, r0
        trapa   #13     ! magic trap, sets ibnr
 
        resbank
 
        assertreg0      0
        assertreg       1, r1
        assertreg       2, r2
        assertreg       3, r3
        assertreg       4, r4
        assertreg       5, r5
        assertreg       6, r6
        assertreg       7, r7
        assertreg       8, r8
        assertreg       9, r9
        assertreg       10, r10
        assertreg       11, r11
        assertreg       12, r12
        assertreg       13, r13
        assertreg       14, r14
        assert_sreg     15, mach
        assert_sreg     17, pr
        assert_creg     18, gbr
        assert_sreg     19, macl
 
resbank_2:
        set_grs_a5a5
        movi20  #555, r0
        mov.l   r0, @-r15
        add     #-1, r0
        mov.l   r0, @-r15
        add     #-1, r0
        mov.l   r0, @-r15
        add     #-1, r0
        mov.l   r0, @-r15
        add     #-1, r0
        mov.l   r0, @-r15
        add     #-1, r0
        mov.l   r0, @-r15
        add     #-1, r0
        mov.l   r0, @-r15
        add     #-1, r0
        mov.l   r0, @-r15
        add     #-1, r0
        mov.l   r0, @-r15
        add     #-1, r0
        mov.l   r0, @-r15
        add     #-1, r0
        mov.l   r0, @-r15
        add     #-1, r0
        mov.l   r0, @-r15
        add     #-1, r0
        mov.l   r0, @-r15
        add     #-1, r0
        mov.l   r0, @-r15
        add     #-1, r0
        mov.l   r0, @-r15
        add     #-1, r0
        mov.l   r0, @-r15
        add     #-1, r0
        mov.l   r0, @-r15
        add     #-1, r0
        mov.l   r0, @-r15
        add     #-1, r0
        mov.l   r0, @-r15
 
        set_sr_bit      (1 << 14)       ! set BO
 
        resbank
 
        assert_sreg     555, macl
        assert_sreg     554, mach
        assert_creg     553, gbr
        assert_sreg     552, pr
        assertreg       551, r14
        assertreg       550, r13
        assertreg       549, r12
        assertreg       548, r11
        assertreg       547, r10
        assertreg       546, r9
        assertreg       545, r8
        assertreg       544, r7
        assertreg       543, r6
        assertreg       542, r5
        assertreg       541, r4
        assertreg       540, r3
        assertreg       539, r2
        assertreg       538, r1
        assertreg0      537
 
        mov             r15, r0
        assertreg0      stackt
 
        pass
 
        exit 0

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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh/] [resbank.s] - Blame information for rev 300

Line No.	Rev	Author	Line
1	24	jeremybenn	`# sh testcase for ldbank stbank resbank`
2			`# mach: all`
3			`# as(sh): -defsym sim_cpu=0`
4			`# as(shdsp): -defsym sim_cpu=1 -dsp`
5
6			`.include "testutils.inc"`
7
8			`.macro SEND reg bankno regno`
9			`set_greg ((\bankno << 7) + (\regno << 2)), \reg`
10			`.endm`
11
12			`start`
13
14			`stbank_1:`
15			`set_grs_a5a5`
16			`mov #0, r0`
17			`SEND r1, 0, 0`
18			`stbank r0, @r1`
19			`mov #1, r0`
20			`SEND r1, 0, 1`
21			`stbank r0, @r1`
22			`mov #2, r0`
23			`SEND r1, 0, 2`
24			`stbank r0, @r1`
25			`mov #3, r0`
26			`SEND r1, 0, 3`
27			`stbank r0, @r1`
28			`mov #4, r0`
29			`SEND r1, 0, 4`
30			`stbank r0, @r1`
31			`mov #5, r0`
32			`SEND r1, 0, 5`
33			`stbank r0, @r1`
34			`mov #6, r0`
35			`SEND r1, 0, 6`
36			`stbank r0, @r1`
37			`mov #7, r0`
38			`SEND r1, 0, 7`
39			`stbank r0, @r1`
40			`mov #8, r0`
41			`SEND r1, 0, 8`
42			`stbank r0, @r1`
43			`mov #9, r0`
44			`SEND r1, 0, 9`
45			`stbank r0, @r1`
46			`mov #10, r0`
47			`SEND r1, 0, 10`
48			`stbank r0, @r1`
49			`mov #11, r0`
50			`SEND r1, 0, 11`
51			`stbank r0, @r1`
52			`mov #12, r0`
53			`SEND r1, 0, 12`
54			`stbank r0, @r1`
55			`mov #13, r0`
56			`SEND r1, 0, 13`
57			`stbank r0, @r1`
58			`mov #14, r0`
59			`SEND r1, 0, 14`
60			`stbank r0, @r1`
61			`mov #15, r0`
62			`SEND r1, 0, 15`
63			`stbank r0, @r1`
64			`mov #16, r0`
65			`SEND r1, 0, 16`
66			`stbank r0, @r1`
67			`mov #17, r0`
68			`SEND r1, 0, 17`
69			`stbank r0, @r1`
70			`mov #18, r0`
71			`SEND r1, 0, 18`
72			`stbank r0, @r1`
73			`mov #19, r0`
74			`SEND r1, 0, 19`
75			`stbank r0, @r1`
76
77			`assertreg0 19`
78			`assertreg 19 << 2, r1`
79			`test_gr_a5a5 r2`
80			`test_gr_a5a5 r3`
81			`test_gr_a5a5 r4`
82			`test_gr_a5a5 r5`
83			`test_gr_a5a5 r6`
84			`test_gr_a5a5 r7`
85			`test_gr_a5a5 r8`
86			`test_gr_a5a5 r9`
87			`test_gr_a5a5 r10`
88			`test_gr_a5a5 r11`
89			`test_gr_a5a5 r12`
90			`test_gr_a5a5 r13`
91			`test_gr_a5a5 r14`
92
93			`ldbank_1:`
94			`set_grs_a5a5`
95			`SEND r1, 0, 0`
96			`ldbank @r1, r0`
97			`assertreg0 0`
98			`SEND r1, 0, 1`
99			`ldbank @r1, r0`
100			`assertreg0 1`
101			`SEND r1, 0, 2`
102			`ldbank @r1, r0`
103			`assertreg0 2`
104			`SEND r1, 0, 3`
105			`ldbank @r1, r0`
106			`assertreg0 3`
107			`SEND r1, 0, 4`
108			`ldbank @r1, r0`
109			`assertreg0 4`
110			`SEND r1, 0, 5`
111			`ldbank @r1, r0`
112			`assertreg0 5`
113			`SEND r1, 0, 6`
114			`ldbank @r1, r0`
115			`assertreg0 6`
116			`SEND r1, 0, 7`
117			`ldbank @r1, r0`
118			`assertreg0 7`
119			`SEND r1, 0, 8`
120			`ldbank @r1, r0`
121			`assertreg0 8`
122			`SEND r1, 0, 9`
123			`ldbank @r1, r0`
124			`assertreg0 9`
125			`SEND r1, 0, 10`
126			`ldbank @r1, r0`
127			`assertreg0 10`
128			`SEND r1, 0, 11`
129			`ldbank @r1, r0`
130			`assertreg0 11`
131			`SEND r1, 0, 12`
132			`ldbank @r1, r0`
133			`assertreg0 12`
134			`SEND r1, 0, 13`
135			`ldbank @r1, r0`
136			`assertreg0 13`
137			`SEND r1, 0, 14`
138			`ldbank @r1, r0`
139			`assertreg0 14`
140			`SEND r1, 0, 15`
141			`ldbank @r1, r0`
142			`assertreg0 15`
143			`SEND r1, 0, 16`
144			`ldbank @r1, r0`
145			`assertreg0 16`
146			`SEND r1, 0, 17`
147			`ldbank @r1, r0`
148			`assertreg0 17`
149			`SEND r1, 0, 18`
150			`ldbank @r1, r0`
151			`assertreg0 18`
152			`SEND r1, 0, 19`
153			`ldbank @r1, r0`
154			`assertreg0 19`
155
156			`assertreg (19 << 2), r1`
157			`test_gr_a5a5 r2`
158			`test_gr_a5a5 r3`
159			`test_gr_a5a5 r4`
160			`test_gr_a5a5 r5`
161			`test_gr_a5a5 r6`
162			`test_gr_a5a5 r7`
163			`test_gr_a5a5 r8`
164			`test_gr_a5a5 r9`
165			`test_gr_a5a5 r10`
166			`test_gr_a5a5 r11`
167			`test_gr_a5a5 r12`
168			`test_gr_a5a5 r13`
169			`test_gr_a5a5 r14`
170
171			`resbank_1:`
172			`set_grs_a5a5`
173			`mov #1, r0`
174			`trapa #13 ! magic trap, sets ibnr`
175
176			`resbank`
177
178			`assertreg0 0`
179			`assertreg 1, r1`
180			`assertreg 2, r2`
181			`assertreg 3, r3`
182			`assertreg 4, r4`
183			`assertreg 5, r5`
184			`assertreg 6, r6`
185			`assertreg 7, r7`
186			`assertreg 8, r8`
187			`assertreg 9, r9`
188			`assertreg 10, r10`
189			`assertreg 11, r11`
190			`assertreg 12, r12`
191			`assertreg 13, r13`
192			`assertreg 14, r14`
193			`assert_sreg 15, mach`
194			`assert_sreg 17, pr`
195			`assert_creg 18, gbr`
196			`assert_sreg 19, macl`
197
198			`resbank_2:`
199			`set_grs_a5a5`
200			`movi20 #555, r0`
201			`mov.l r0, @-r15`
202			`add #-1, r0`
203			`mov.l r0, @-r15`
204			`add #-1, r0`
205			`mov.l r0, @-r15`
206			`add #-1, r0`
207			`mov.l r0, @-r15`
208			`add #-1, r0`
209			`mov.l r0, @-r15`
210			`add #-1, r0`
211			`mov.l r0, @-r15`
212			`add #-1, r0`
213			`mov.l r0, @-r15`
214			`add #-1, r0`
215			`mov.l r0, @-r15`
216			`add #-1, r0`
217			`mov.l r0, @-r15`
218			`add #-1, r0`
219			`mov.l r0, @-r15`
220			`add #-1, r0`
221			`mov.l r0, @-r15`
222			`add #-1, r0`
223			`mov.l r0, @-r15`
224			`add #-1, r0`
225			`mov.l r0, @-r15`
226			`add #-1, r0`
227			`mov.l r0, @-r15`
228			`add #-1, r0`
229			`mov.l r0, @-r15`
230			`add #-1, r0`
231			`mov.l r0, @-r15`
232			`add #-1, r0`
233			`mov.l r0, @-r15`
234			`add #-1, r0`
235			`mov.l r0, @-r15`
236			`add #-1, r0`
237			`mov.l r0, @-r15`
238
239			`set_sr_bit (1 << 14) ! set BO`
240
241			`resbank`
242
243			`assert_sreg 555, macl`
244			`assert_sreg 554, mach`
245			`assert_creg 553, gbr`
246			`assert_sreg 552, pr`
247			`assertreg 551, r14`
248			`assertreg 550, r13`
249			`assertreg 549, r12`
250			`assertreg 548, r11`
251			`assertreg 547, r10`
252			`assertreg 546, r9`
253			`assertreg 545, r8`
254			`assertreg 544, r7`
255			`assertreg 543, r6`
256			`assertreg 542, r5`
257			`assertreg 541, r4`
258			`assertreg 540, r3`
259			`assertreg 539, r2`
260			`assertreg 538, r1`
261			`assertreg0 537`
262
263			`mov r15, r0`
264			`assertreg0 stackt`
265
266			`pass`
267
268			`exit 0`