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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh/] [shll16.s] - Blame information for rev 300

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1 24 jeremybenn 
# sh testcase for shll16
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# mach: all
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# as(sh):       -defsym sim_cpu=0
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# as(shdsp):    -defsym sim_cpu=1 -dsp
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        .include "testutils.inc"
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        start
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shll16:
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        set_grs_a5a5
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        mov #0x18, r1
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        shll16 r1
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        assertreg 0x180000, r1
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        shll16 r1
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        assertreg 0, r1
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        # another:
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        mov #1, r1
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        shll16 r1
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        mov #1, r7
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        shll r7
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        shll r7
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        shll r7
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        shll r7
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        shll r7
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        shll r7
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        shll r7
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        shll r7
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        shll r7
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        shll r7
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        shll r7
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        shll r7
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        shll r7
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        shll r7
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        shll r7
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        shll r7
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        cmp/eq r1, r7
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        bt   okay
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        fail
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okay:
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        set_greg 0xa5a5a5a5, r1
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        set_greg 0xa5a5a5a5, r7
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        test_grs_a5a5
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        pass
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        exit 0

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