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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh/] [testutils.inc] - Blame information for rev 157

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# Support macros for the sh assembly test cases.
 
        .equ    no_dsp,  0
        .equ    yes_dsp, 1
 
        .section        .rodata
        .align 2
_pass:  .string "pass\n"
_fail:  .string "fail\n"
_stack: .fill   128, 4, 0
stackt:
 
        .macro  push reg
        mov.l   \reg, @-r15
        .endm
 
        .macro  pop reg
        mov.l   @r15+, \reg
        .endm
 
        .macro start
        .text
        .align 1
        .global start
start:  mov.l   stackp, r15
        bra     main
        nop
        .align 2
stackp: .long   stackt
mpass:
        mov     #4, r4
        mov     #1, r5
        mov.l   ppass, r6
        mov     #5, r7
        trapa   #34
        rts
        nop
mfail:
        mov     #4, r4
        mov     #1, r5
        mov.l   pfail, r6
        mov     #5, r7
        trapa   #34
        mov     #1, r5
mexit:
        mov     #1, r4
        mov     #0, r6
        mov     #0, r7
        trapa   #34
        .align 2
ppass:  .long   _pass
pfail:  .long   _fail
 
mtesta5:
        push    r0
        mov.l   a5a5, r0
        cmp/eq  r1, r0
        bf      mfail
        cmp/eq  r2, r0
        bf      mfail
        cmp/eq  r3, r0
        bf      mfail
        cmp/eq  r4, r0
        bf      mfail
        cmp/eq  r5, r0
        bf      mfail
        cmp/eq  r6, r0
        bf      mfail
        cmp/eq  r7, r0
        bf      mfail
        cmp/eq  r8, r0
        bf      mfail
        cmp/eq  r9, r0
        bf      mfail
        cmp/eq  r10, r0
        bf      mfail
        cmp/eq  r11, r0
        bf      mfail
        cmp/eq  r12, r0
        bf      mfail
        cmp/eq  r13, r0
        bf      mfail
        cmp/eq  r14, r0
        bf      mfail
        # restore and check r0
        pop     r0
        cmp/eq  r0, r1
        bf      mfail
        # pass
        rts
        nop
.if (sim_cpu == no_dsp)
mtesta5_fp:
        push    r0
        flds    fr0, fpul
        sts     fpul, r0
        push    r0
        mov.l   a5a5, r0
        lds     r0, fpul
        fsts    fpul, fr0
        fcmp/eq fr1, fr0
        bf      mfail
        fcmp/eq fr2, fr0
        bf      mfail
        fcmp/eq fr3, fr0
        bf      mfail
        fcmp/eq fr4, fr0
        bf      mfail
        fcmp/eq fr5, fr0
        bf      mfail
        fcmp/eq fr6, fr0
        bf      mfail
        fcmp/eq fr7, fr0
        bf      mfail
        fcmp/eq fr8, fr0
        bf      mfail
        fcmp/eq fr9, fr0
        bf      mfail
        fcmp/eq fr10, fr0
        bf      mfail
        fcmp/eq fr11, fr0
        bf      mfail
        fcmp/eq fr12, fr0
        bf      mfail
        fcmp/eq fr13, fr0
        bf      mfail
        fcmp/eq fr14, fr0
        bf      mfail
        fcmp/eq fr15, fr0
        bf      mfail
        # restore and check fr0
        pop     r0
        lds     r0, fpul
        fsts    fpul, fr0
        fcmp/eq fr0, fr1
        bf      mfail
        # restore r0 and pass
        pop     r0
        rts
        nop
.endif
 
mseta5:
        mov.l   a5a5, r0
        mov.l   a5a5, r1
        mov.l   a5a5, r2
        mov.l   a5a5, r3
        mov.l   a5a5, r4
        mov.l   a5a5, r5
        mov.l   a5a5, r6
        mov.l   a5a5, r7
        mov.l   a5a5, r8
        mov.l   a5a5, r9
        mov.l   a5a5, r10
        mov.l   a5a5, r11
        mov.l   a5a5, r12
        mov.l   a5a5, r13
        mov.l   a5a5, r14
        rts
        nop
 
.if (sim_cpu == no_dsp)
mseta5_fp:
        push    r0
        mov.l   a5a5, r0
        lds     r0, fpul
        fsts    fpul, fr0
        fsts    fpul, fr1
        fsts    fpul, fr2
        fsts    fpul, fr3
        fsts    fpul, fr4
        fsts    fpul, fr5
        fsts    fpul, fr6
        fsts    fpul, fr7
        fsts    fpul, fr8
        fsts    fpul, fr9
        fsts    fpul, fr10
        fsts    fpul, fr11
        fsts    fpul, fr12
        fsts    fpul, fr13
        fsts    fpul, fr14
        fsts    fpul, fr15
        pop     r0
        rts
        nop
.endif
 
        .align 2
a5a5:   .long   0xa5a5a5a5
main:
        .endm
 
        .macro exit val
        mov     #\val, r5
        bra     mexit
        nop
        .endm
 
        .macro pass
        bsr     mpass
        nop
        .endm
 
        .macro fail
        bra     mfail
        nop
        .endm
        # Branch if false -- 8k range
        .macro bf8k label
        bt      .Lbf8k\@
        bra     \label
.Lbf8k\@:
        .endm
 
        # Branch if true -- 8k range
        .macro bt8k label
        bf      .Lbt8k\@
        bra     \label
.Lbt8k\@:
        .endm
 
        # Assert value of register (any general register but r0)
        # Preserves r0 on stack, restores it on success.
        .macro assertreg val reg
        push    r0
        mov.l   .Larval\@, r0
        cmp/eq  r0, \reg
        bt      .Lar\@
        fail
        .align 2
.Larval\@:
        .long   \val
.Lar\@: pop     r0
        .endm
 
        # Assert value of register zero
        # Preserves r1 on stack, restores it on success.
        .macro assertreg0 val
        push    r1
        mov.l   .Lazval\@, r1
        cmp/eq  r1, r0
        bt      .Laz\@
        fail
        .align 2
.Lazval\@:
        .long   \val
.Laz\@: pop     r1
        .endm
 
        # Assert value of system register
        # [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...]
        .macro assert_sreg val reg
        push    r0
        sts     \reg, r0
        assertreg0 \val
        pop     r0
        .endm
 
        # Assert value of system register that isn't directly stc-able
        # [a1, m0, m1, ...]
        .macro assert_sreg2 val reg
        push    r0
        sts     a0, r0
        push    r0
        pcopy   \reg, a0
        sts     a0, r0
        assertreg0 \val
        pop     r0
        lds     r0, a0
        pop     r0
        .endm
 
        # Assert value of control register
        # [gbr, vbr, ssr, spc, sgr, dbr, r[0-7]_bank, sr, mod, re, rs, ...]
        .macro assert_creg val reg
        push    r0
        stc     \reg, r0
        assertreg0 \val
        pop     r0
        .endm
 
        # Assert integer value of fp register
        # Preserves r0 on stack, restores it on success
        # Assumes single-precision fp mode
        .macro assert_fpreg_i val freg
        push    r0
        ftrc    \freg, fpul
        sts     fpul, r0
        assertreg0      \val
        pop     r0
        .endm
 
        # Assert integer value of dp register
        # Preserves r0 on stack, restores it on success
        # Assumes double-precision fp mode
        .macro assert_dpreg_i val dreg
        push    r0
        ftrc    \dreg, fpul
        sts     fpul, r0
        assertreg0      \val
        pop     r0
        .endm
 
        # Assert hex value of fp register
        # Preserves r0 on stack, restores it on success
        # Assumes single-precision fp mode
        .macro assert_fpreg_x val freg
        push    r0
        flds    \freg, fpul
        sts     fpul, r0
        assertreg0      \val
        pop     r0
        .endm
 
        # Set FP bank 0
        # Saves and restores r0 and r1
        .macro  bank0
        push    r0
        push    r1
        mov     #32, r1
        shll16  r1
        not     r1, r1
        sts     fpscr, r0
        and     r1, r0
        lds     r0, fpscr
        pop     r1
        pop     r0
        .endm
 
        # Set FP bank 1
        .macro  bank1
        push    r0
        push    r1
        mov     #32,  r1
        shll16  r1
        sts     fpscr, r0
        or      r1, r0
        lds     r0, fpscr
        pop     r1
        pop     r0
        .endm
 
        # Set FP 32-bit xfer
        .macro  sz_32
        push    r0
        push    r1
        mov     #16,  r1
        shll16  r1
        not     r1, r1
        sts     fpscr, r0
        and     r1, r0
        lds     r0, fpscr
        pop     r1
        pop     r0
        .endm
 
        # Set FP 64-bit xfer
        .macro  sz_64
        push    r0
        push    r1
        mov     #16,  r1
        shll16  r1
        sts     fpscr, r0
        or      r1, r0
        lds     r0, fpscr
        pop     r1
        pop     r0
        .endm
 
        # Set FP single precision
        .macro  single_prec
        push    r0
        push    r1
        mov     #8, r1
        shll16  r1
        not     r1, r1
        sts     fpscr, r0
        and     r1, r0
        lds     r0, fpscr
        pop     r1
        pop     r0
        .endm
 
        # Set FP double precision
        .macro  double_prec
        push    r0
        push    r1
        mov     #8, r1
        shll16  r1
        sts     fpscr, r0
        or      r1, r0
        lds     r0, fpscr
        pop     r1
        pop     r0
        .endm
 
        .macro  set_carry
        sett
        .endm
 
        .macro  set_ovf
        sett
        .endm
 
        .macro  clear_carry
        clrt
        .endm
 
        .macro  clear_ovf
        clrt
        .endm
 
        # sets, clrs
 
 
        .macro set_grs_a5a5
        bsr     mseta5
        nop
        .endm
 
        .macro set_greg val greg
        mov.l   gregval\@, \greg
        bra     set_greg\@
        nop
        .align  2
gregval\@:      .long   \val
set_greg\@:
        .endm
 
        .macro set_fprs_a5a5
        bsr     mseta5_fp
        nop
        .endm
 
        .macro test_grs_a5a5
        bsr     mtesta5
        nop
        .endm
 
        .macro test_fprs_a5a5
        bsr     mtesta5_fp
        nop
        .endm
 
        .macro test_gr_a5a5 reg
        assertreg 0xa5a5a5a5 \reg
        .endm
 
        .macro test_fpr_a5a5 reg
        assert_fpreg_x 0xa5a5a5a5 \reg
        .endm
 
        .macro test_gr0_a5a5
        assertreg0 0xa5a5a5a5
        .endm
 
        # Perform a single to double precision floating point conversion.
        # Assumes correct settings of fpscr.
        .macro _s2d fpr dpr
        flds \fpr, fpul
        fcnvsd fpul, \dpr
        .endm
 
        # Manipulate the status register
        .macro set_sr   val
        push    r0
        mov.l   .Lsrval\@, r0
        ldc     r0, sr
        pop     r0
        bra     .Lsetsr\@
        nop
        .align 2
.Lsrval\@:
        .long   \val
.Lsetsr\@:
        .endm
 
        .macro  get_sr  reg
        stc     sr, \reg
        .endm
 
        .macro  test_sr val
        push    r0
        get_sr  r0
        assertreg0 \val
        pop     r0
        .endm
 
        .macro  set_sr_bit val
        push    r0
        push    r1
        get_sr  r0
        mov.l   .Lsrbitval\@, r1
        or      r1, r0
        ldc     r0, sr
        pop     r1
        pop     r0
        bra     .Lsrbit\@
        nop
        .align 2
.Lsrbitval\@:
        .long   \val
.Lsrbit\@:
        .endm
 
        .macro  test_sr_bit_set val
        push    r0
        push    r1
        get_sr  r0
        mov.l   .Ltsbsval\@, r1
        tst     r1, r0
        bf      .Ltsbs\@
        fail
        .align  2
.Ltsbsval\@:
        .long   \val
.Ltsbs\@:
        pop     r1
        pop     r0
        .endm
 
        .macro  test_sr_bit_clear val
        push    r0
        push    r1
        get_sr  r0
        mov.l   .Ltsbcval\@, r1
        not     r0, r0
        tst     r1, r0
        bf      .Ltsbc\@
        fail
        .align  2
.Ltsbcval\@:
        .long   \val
.Ltsbc\@:
        pop     r1
        pop     r0
        .endm
 
        # Set system registers
        .macro set_sreg val reg
        # [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...]
        push    r0
        mov.l   .Lssrval\@, r0
        lds     r0, \reg
        pop     r0
        bra     .Lssr\@
        nop
        .align 2
.Lssrval\@:
        .long   \val
.Lssr\@:
        .endm
 
        .macro set_sreg2 val reg
        # [a1, m0, m1, ...]
        push    r0
        sts     a0, r0
        push    r0
        mov.l   .Lssr2val\@, r0
        lds     r0, a0
        pcopy   a0, \reg
        pop     r0
        lds     r0, a0
        pop     r0
        bra     .Lssr2_\@
        nop
        .align 2
.Lssr2val\@:
        .long   \val
.Lssr2_\@:
        .endm
 
 
        .macro set_creg val reg
        # [gbr, vbr, ssr, spc, sgr, dbr... ]
        push    r0
        mov.l   .Lscrval\@, r0
        ldc     r0, \reg
        pop     r0
        bra     .Lscr\@
        nop
        .align 2
.Lscrval\@:
        .long   \val
.Lscr\@:
        .endm
 
        .macro  set_dctrue
        push    r0
        sts     dsr, r0
        or      #1, r0
        lds     r0, dsr
        pop     r0
        .endm
 
        .macro  set_dcfalse
        push    r0
        sts     dsr, r0
        not     r0, r0
        or      #1, r0
        not     r0, r0
        lds     r0, dsr
        pop     r0
        .endm
 
        .macro  assertmem addr val
        push    r0
        mov.l   .Laddr\@, r0
        mov.l   @r0, r0
        assertreg0 \val
        bra     .Lam\@
        nop
        .align  2
.Laddr\@:
        .long   \addr
.Lam\@: pop     r0
        .endm

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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh/] [testutils.inc] - Blame information for rev 157

Line No.	Rev	Author	Line
1	24	jeremybenn	`# Support macros for the sh assembly test cases.`
2
3			`.equ no_dsp, 0`
4			`.equ yes_dsp, 1`
5
6			`.section .rodata`
7			`.align 2`
8			`_pass: .string "pass\n"`
9			`_fail: .string "fail\n"`
10			`_stack: .fill 128, 4, 0`
11			`stackt:`
12
13			`.macro push reg`
14			`mov.l \reg, @-r15`
15			`.endm`
16
17			`.macro pop reg`
18			`mov.l @r15+, \reg`
19			`.endm`
20
21			`.macro start`
22			`.text`
23			`.align 1`
24			`.global start`
25			`start: mov.l stackp, r15`
26			`bra main`
27			`nop`
28			`.align 2`
29			`stackp: .long stackt`
30			`mpass:`
31			`mov #4, r4`
32			`mov #1, r5`
33			`mov.l ppass, r6`
34			`mov #5, r7`
35			`trapa #34`
36			`rts`
37			`nop`
38			`mfail:`
39			`mov #4, r4`
40			`mov #1, r5`
41			`mov.l pfail, r6`
42			`mov #5, r7`
43			`trapa #34`
44			`mov #1, r5`
45			`mexit:`
46			`mov #1, r4`
47			`mov #0, r6`
48			`mov #0, r7`
49			`trapa #34`
50			`.align 2`
51			`ppass: .long _pass`
52			`pfail: .long _fail`
53
54			`mtesta5:`
55			`push r0`
56			`mov.l a5a5, r0`
57			`cmp/eq r1, r0`
58			`bf mfail`
59			`cmp/eq r2, r0`
60			`bf mfail`
61			`cmp/eq r3, r0`
62			`bf mfail`
63			`cmp/eq r4, r0`
64			`bf mfail`
65			`cmp/eq r5, r0`
66			`bf mfail`
67			`cmp/eq r6, r0`
68			`bf mfail`
69			`cmp/eq r7, r0`
70			`bf mfail`
71			`cmp/eq r8, r0`
72			`bf mfail`
73			`cmp/eq r9, r0`
74			`bf mfail`
75			`cmp/eq r10, r0`
76			`bf mfail`
77			`cmp/eq r11, r0`
78			`bf mfail`
79			`cmp/eq r12, r0`
80			`bf mfail`
81			`cmp/eq r13, r0`
82			`bf mfail`
83			`cmp/eq r14, r0`
84			`bf mfail`
85			`# restore and check r0`
86			`pop r0`
87			`cmp/eq r0, r1`
88			`bf mfail`
89			`# pass`
90			`rts`
91			`nop`
92			`.if (sim_cpu == no_dsp)`
93			`mtesta5_fp:`
94			`push r0`
95			`flds fr0, fpul`
96			`sts fpul, r0`
97			`push r0`
98			`mov.l a5a5, r0`
99			`lds r0, fpul`
100			`fsts fpul, fr0`
101			`fcmp/eq fr1, fr0`
102			`bf mfail`
103			`fcmp/eq fr2, fr0`
104			`bf mfail`
105			`fcmp/eq fr3, fr0`
106			`bf mfail`
107			`fcmp/eq fr4, fr0`
108			`bf mfail`
109			`fcmp/eq fr5, fr0`
110			`bf mfail`
111			`fcmp/eq fr6, fr0`
112			`bf mfail`
113			`fcmp/eq fr7, fr0`
114			`bf mfail`
115			`fcmp/eq fr8, fr0`
116			`bf mfail`
117			`fcmp/eq fr9, fr0`
118			`bf mfail`
119			`fcmp/eq fr10, fr0`
120			`bf mfail`
121			`fcmp/eq fr11, fr0`
122			`bf mfail`
123			`fcmp/eq fr12, fr0`
124			`bf mfail`
125			`fcmp/eq fr13, fr0`
126			`bf mfail`
127			`fcmp/eq fr14, fr0`
128			`bf mfail`
129			`fcmp/eq fr15, fr0`
130			`bf mfail`
131			`# restore and check fr0`
132			`pop r0`
133			`lds r0, fpul`
134			`fsts fpul, fr0`
135			`fcmp/eq fr0, fr1`
136			`bf mfail`
137			`# restore r0 and pass`
138			`pop r0`
139			`rts`
140			`nop`
141			`.endif`
142
143			`mseta5:`
144			`mov.l a5a5, r0`
145			`mov.l a5a5, r1`
146			`mov.l a5a5, r2`
147			`mov.l a5a5, r3`
148			`mov.l a5a5, r4`
149			`mov.l a5a5, r5`
150			`mov.l a5a5, r6`
151			`mov.l a5a5, r7`
152			`mov.l a5a5, r8`
153			`mov.l a5a5, r9`
154			`mov.l a5a5, r10`
155			`mov.l a5a5, r11`
156			`mov.l a5a5, r12`
157			`mov.l a5a5, r13`
158			`mov.l a5a5, r14`
159			`rts`
160			`nop`
161
162			`.if (sim_cpu == no_dsp)`
163			`mseta5_fp:`
164			`push r0`
165			`mov.l a5a5, r0`
166			`lds r0, fpul`
167			`fsts fpul, fr0`
168			`fsts fpul, fr1`
169			`fsts fpul, fr2`
170			`fsts fpul, fr3`
171			`fsts fpul, fr4`
172			`fsts fpul, fr5`
173			`fsts fpul, fr6`
174			`fsts fpul, fr7`
175			`fsts fpul, fr8`
176			`fsts fpul, fr9`
177			`fsts fpul, fr10`
178			`fsts fpul, fr11`
179			`fsts fpul, fr12`
180			`fsts fpul, fr13`
181			`fsts fpul, fr14`
182			`fsts fpul, fr15`
183			`pop r0`
184			`rts`
185			`nop`
186			`.endif`
187
188			`.align 2`
189			`a5a5: .long 0xa5a5a5a5`
190			`main:`
191			`.endm`
192
193			`.macro exit val`
194			`mov #\val, r5`
195			`bra mexit`
196			`nop`
197			`.endm`
198
199			`.macro pass`
200			`bsr mpass`
201			`nop`
202			`.endm`
203
204			`.macro fail`
205			`bra mfail`
206			`nop`
207			`.endm`
208			`# Branch if false -- 8k range`
209			`.macro bf8k label`
210			`bt .Lbf8k\@`
211			`bra \label`
212			`.Lbf8k\@:`
213			`.endm`
214
215			`# Branch if true -- 8k range`
216			`.macro bt8k label`
217			`bf .Lbt8k\@`
218			`bra \label`
219			`.Lbt8k\@:`
220			`.endm`
221
222			`# Assert value of register (any general register but r0)`
223			`# Preserves r0 on stack, restores it on success.`
224			`.macro assertreg val reg`
225			`push r0`
226			`mov.l .Larval\@, r0`
227			`cmp/eq r0, \reg`
228			`bt .Lar\@`
229			`fail`
230			`.align 2`
231			`.Larval\@:`
232			`.long \val`
233			`.Lar\@: pop r0`
234			`.endm`
235
236			`# Assert value of register zero`
237			`# Preserves r1 on stack, restores it on success.`
238			`.macro assertreg0 val`
239			`push r1`
240			`mov.l .Lazval\@, r1`
241			`cmp/eq r1, r0`
242			`bt .Laz\@`
243			`fail`
244			`.align 2`
245			`.Lazval\@:`
246			`.long \val`
247			`.Laz\@: pop r1`
248			`.endm`
249
250			`# Assert value of system register`
251			`# [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...]`
252			`.macro assert_sreg val reg`
253			`push r0`
254			`sts \reg, r0`
255			`assertreg0 \val`
256			`pop r0`
257			`.endm`
258
259			`# Assert value of system register that isn't directly stc-able`
260			`# [a1, m0, m1, ...]`
261			`.macro assert_sreg2 val reg`
262			`push r0`
263			`sts a0, r0`
264			`push r0`
265			`pcopy \reg, a0`
266			`sts a0, r0`
267			`assertreg0 \val`
268			`pop r0`
269			`lds r0, a0`
270			`pop r0`
271			`.endm`
272
273			`# Assert value of control register`
274			`# [gbr, vbr, ssr, spc, sgr, dbr, r[0-7]_bank, sr, mod, re, rs, ...]`
275			`.macro assert_creg val reg`
276			`push r0`
277			`stc \reg, r0`
278			`assertreg0 \val`
279			`pop r0`
280			`.endm`
281
282			`# Assert integer value of fp register`
283			`# Preserves r0 on stack, restores it on success`
284			`# Assumes single-precision fp mode`
285			`.macro assert_fpreg_i val freg`
286			`push r0`
287			`ftrc \freg, fpul`
288			`sts fpul, r0`
289			`assertreg0 \val`
290			`pop r0`
291			`.endm`
292
293			`# Assert integer value of dp register`
294			`# Preserves r0 on stack, restores it on success`
295			`# Assumes double-precision fp mode`
296			`.macro assert_dpreg_i val dreg`
297			`push r0`
298			`ftrc \dreg, fpul`
299			`sts fpul, r0`
300			`assertreg0 \val`
301			`pop r0`
302			`.endm`
303
304			`# Assert hex value of fp register`
305			`# Preserves r0 on stack, restores it on success`
306			`# Assumes single-precision fp mode`
307			`.macro assert_fpreg_x val freg`
308			`push r0`
309			`flds \freg, fpul`
310			`sts fpul, r0`
311			`assertreg0 \val`
312			`pop r0`
313			`.endm`
314
315			`# Set FP bank 0`
316			`# Saves and restores r0 and r1`
317			`.macro bank0`
318			`push r0`
319			`push r1`
320			`mov #32, r1`
321			`shll16 r1`
322			`not r1, r1`
323			`sts fpscr, r0`
324			`and r1, r0`
325			`lds r0, fpscr`
326			`pop r1`
327			`pop r0`
328			`.endm`
329
330			`# Set FP bank 1`
331			`.macro bank1`
332			`push r0`
333			`push r1`
334			`mov #32, r1`
335			`shll16 r1`
336			`sts fpscr, r0`
337			`or r1, r0`
338			`lds r0, fpscr`
339			`pop r1`
340			`pop r0`
341			`.endm`
342
343			`# Set FP 32-bit xfer`
344			`.macro sz_32`
345			`push r0`
346			`push r1`
347			`mov #16, r1`
348			`shll16 r1`
349			`not r1, r1`
350			`sts fpscr, r0`
351			`and r1, r0`
352			`lds r0, fpscr`
353			`pop r1`
354			`pop r0`
355			`.endm`
356
357			`# Set FP 64-bit xfer`
358			`.macro sz_64`
359			`push r0`
360			`push r1`
361			`mov #16, r1`
362			`shll16 r1`
363			`sts fpscr, r0`
364			`or r1, r0`
365			`lds r0, fpscr`
366			`pop r1`
367			`pop r0`
368			`.endm`
369
370			`# Set FP single precision`
371			`.macro single_prec`
372			`push r0`
373			`push r1`
374			`mov #8, r1`
375			`shll16 r1`
376			`not r1, r1`
377			`sts fpscr, r0`
378			`and r1, r0`
379			`lds r0, fpscr`
380			`pop r1`
381			`pop r0`
382			`.endm`
383
384			`# Set FP double precision`
385			`.macro double_prec`
386			`push r0`
387			`push r1`
388			`mov #8, r1`
389			`shll16 r1`
390			`sts fpscr, r0`
391			`or r1, r0`
392			`lds r0, fpscr`
393			`pop r1`
394			`pop r0`
395			`.endm`
396
397			`.macro set_carry`
398			`sett`
399			`.endm`
400
401			`.macro set_ovf`
402			`sett`
403			`.endm`
404
405			`.macro clear_carry`
406			`clrt`
407			`.endm`
408
409			`.macro clear_ovf`
410			`clrt`
411			`.endm`
412
413			`# sets, clrs`
414
415
416			`.macro set_grs_a5a5`
417			`bsr mseta5`
418			`nop`
419			`.endm`
420
421			`.macro set_greg val greg`
422			`mov.l gregval\@, \greg`
423			`bra set_greg\@`
424			`nop`
425			`.align 2`
426			`gregval\@: .long \val`
427			`set_greg\@:`
428			`.endm`
429
430			`.macro set_fprs_a5a5`
431			`bsr mseta5_fp`
432			`nop`
433			`.endm`
434
435			`.macro test_grs_a5a5`
436			`bsr mtesta5`
437			`nop`
438			`.endm`
439
440			`.macro test_fprs_a5a5`
441			`bsr mtesta5_fp`
442			`nop`
443			`.endm`
444
445			`.macro test_gr_a5a5 reg`
446			`assertreg 0xa5a5a5a5 \reg`
447			`.endm`
448
449			`.macro test_fpr_a5a5 reg`
450			`assert_fpreg_x 0xa5a5a5a5 \reg`
451			`.endm`
452
453			`.macro test_gr0_a5a5`
454			`assertreg0 0xa5a5a5a5`
455			`.endm`
456
457			`# Perform a single to double precision floating point conversion.`
458			`# Assumes correct settings of fpscr.`
459			`.macro _s2d fpr dpr`
460			`flds \fpr, fpul`
461			`fcnvsd fpul, \dpr`
462			`.endm`
463
464			`# Manipulate the status register`
465			`.macro set_sr val`
466			`push r0`
467			`mov.l .Lsrval\@, r0`
468			`ldc r0, sr`
469			`pop r0`
470			`bra .Lsetsr\@`
471			`nop`
472			`.align 2`
473			`.Lsrval\@:`
474			`.long \val`
475			`.Lsetsr\@:`
476			`.endm`
477
478			`.macro get_sr reg`
479			`stc sr, \reg`
480			`.endm`
481
482			`.macro test_sr val`
483			`push r0`
484			`get_sr r0`
485			`assertreg0 \val`
486			`pop r0`
487			`.endm`
488
489			`.macro set_sr_bit val`
490			`push r0`
491			`push r1`
492			`get_sr r0`
493			`mov.l .Lsrbitval\@, r1`
494			`or r1, r0`
495			`ldc r0, sr`
496			`pop r1`
497			`pop r0`
498			`bra .Lsrbit\@`
499			`nop`
500			`.align 2`
501			`.Lsrbitval\@:`
502			`.long \val`
503			`.Lsrbit\@:`
504			`.endm`
505
506			`.macro test_sr_bit_set val`
507			`push r0`
508			`push r1`
509			`get_sr r0`
510			`mov.l .Ltsbsval\@, r1`
511			`tst r1, r0`
512			`bf .Ltsbs\@`
513			`fail`
514			`.align 2`
515			`.Ltsbsval\@:`
516			`.long \val`
517			`.Ltsbs\@:`
518			`pop r1`
519			`pop r0`
520			`.endm`
521
522			`.macro test_sr_bit_clear val`
523			`push r0`
524			`push r1`
525			`get_sr r0`
526			`mov.l .Ltsbcval\@, r1`
527			`not r0, r0`
528			`tst r1, r0`
529			`bf .Ltsbc\@`
530			`fail`
531			`.align 2`
532			`.Ltsbcval\@:`
533			`.long \val`
534			`.Ltsbc\@:`
535			`pop r1`
536			`pop r0`
537			`.endm`
538
539			`# Set system registers`
540			`.macro set_sreg val reg`
541			`# [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...]`
542			`push r0`
543			`mov.l .Lssrval\@, r0`
544			`lds r0, \reg`
545			`pop r0`
546			`bra .Lssr\@`
547			`nop`
548			`.align 2`
549			`.Lssrval\@:`
550			`.long \val`
551			`.Lssr\@:`
552			`.endm`
553
554			`.macro set_sreg2 val reg`
555			`# [a1, m0, m1, ...]`
556			`push r0`
557			`sts a0, r0`
558			`push r0`
559			`mov.l .Lssr2val\@, r0`
560			`lds r0, a0`
561			`pcopy a0, \reg`
562			`pop r0`
563			`lds r0, a0`
564			`pop r0`
565			`bra .Lssr2_\@`
566			`nop`
567			`.align 2`
568			`.Lssr2val\@:`
569			`.long \val`
570			`.Lssr2_\@:`
571			`.endm`
572
573
574			`.macro set_creg val reg`
575			`# [gbr, vbr, ssr, spc, sgr, dbr... ]`
576			`push r0`
577			`mov.l .Lscrval\@, r0`
578			`ldc r0, \reg`
579			`pop r0`
580			`bra .Lscr\@`
581			`nop`
582			`.align 2`
583			`.Lscrval\@:`
584			`.long \val`
585			`.Lscr\@:`
586			`.endm`
587
588			`.macro set_dctrue`
589			`push r0`
590			`sts dsr, r0`
591			`or #1, r0`
592			`lds r0, dsr`
593			`pop r0`
594			`.endm`
595
596			`.macro set_dcfalse`
597			`push r0`
598			`sts dsr, r0`
599			`not r0, r0`
600			`or #1, r0`
601			`not r0, r0`
602			`lds r0, dsr`
603			`pop r0`
604			`.endm`
605
606			`.macro assertmem addr val`
607			`push r0`
608			`mov.l .Laddr\@, r0`
609			`mov.l @r0, r0`
610			`assertreg0 \val`
611			`bra .Lam\@`
612			`nop`
613			`.align 2`
614			`.Laddr\@:`
615			`.long \addr`
616			`.Lam\@: pop r0`
617			`.endm`