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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh64/] [compact/] [fmov.cgs] - Blame information for rev 157

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Line No. Rev Author Line
1 24 jeremybenn
# sh testcase for all fmov instructions
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# mach: all
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# as: -isa=shcompact
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# ld: -m shelf32
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        .include "compact/testutils.inc"
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        .macro init
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        fldi0 fr0
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        fldi1 fr2
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        .endm
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        # Set the SZ (SiZe) bit in the fpscr.
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        .macro _setsz
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        sts fpscr, r7
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        mov #16, r8
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        shll16 r8
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        or r8, r7
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        lds r7, fpscr
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        .endm
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        # Clear the SZ bit.
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        .macro _clrsz
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        sts fpscr, r7
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        mov #16, r8
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        shll16 r8
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        not r8, r8
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        and r8, r7
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        lds r7, fpscr
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        .endm
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        start
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fmov1:  # Test fr -> fr.
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        init
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        _clrpr
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        _clrsz
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        fmov fr0, fr10
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        # Ensure fr0 and fr10 are now equal.
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        fcmp/eq fr0, fr10
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        bt fmov2
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        fail
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fmov2:  # Test dr -> dr.
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        init
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        _setpr
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        _setsz
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        fmov dr0, dr2
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        # Ensure dr0 and dr2 are now equal.
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        fcmp/eq dr0, dr2
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        bt fmov3
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        fail
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fmov3:  # Test dr -> xd and xd -> dr.
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        init
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        _setsz
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        fmov dr0, xd0
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        # Ensure dr0 and xd0 are now equal.
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        fmov xd0, dr2
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        fcmp/eq dr0, dr2
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        bt fmov4
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        fail
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fmov4:  # Test xd -> xd.
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        init
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        _setsz
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        _setpr
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        fmov dr0, xd0
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        fmov xd0, xd2
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        fmov xd2, dr2
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        # Ensure dr0 and dr2 are now equal.
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        fcmp/eq dr0, dr2
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        bt fmov5
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        fail
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fmov5:  # Test fr -> @rn and @rn -> fr.
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        init
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        _clrsz
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        _clrpr
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        mov #40, r0
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        shll8 r0
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        fmov fr0, @r0
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        fmov @r0, fr1
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        fcmp/eq fr0, fr1
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        bt fmov6
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        fail
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fmov6:  # Test dr -> @rn and @rn -> dr.
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        init
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        _setsz
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        _setpr
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        mov #40, r0
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        shll8 r0
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        fmov dr0, @r0
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        fmov @r0, dr2
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        fcmp/eq dr0, dr2
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        bt fmov7
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        fail
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fmov7:  # Test xd -> @rn and @rn -> xd.
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        init
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        _setsz
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        _setpr
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        mov #40, r0
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        shll8 r0
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        fmov dr0, xd0
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        fmov xd0, @r0
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        fmov @r0, xd2
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        fmov xd2, dr2
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        fcmp/eq dr0, dr2
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        bt fmov8
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        fail
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fmov8:  # Test fr -> @-rn.
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        init
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        _clrsz
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        _clrpr
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        mov #40, r0
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        shll8 r0
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        # Preserve.
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        mov r0, r1
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        fmov fr0, @-r0
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        fmov @r0, fr2
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        fcmp/eq fr0, fr2
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        bt f8b
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        fail
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f8b:    # check pre-dec.
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        add #4, r0
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        cmp/eq r0, r1
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        bt fmov9
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        fail
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fmov9:  # Test dr -> @-rn.
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        init
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        _setsz
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        _setpr
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        mov #40, r0
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        shll8 r0
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        # Preserve r0.
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        mov r0, r1
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        fmov dr0, @-r0
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        fmov @r0, dr2
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        fcmp/eq dr0, dr2
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        bt f9b
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        fail
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f9b:    # check pre-dec.
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        add #8, r0
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        cmp/eq r0, r1
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        bt fmov10
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        fail
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fmov10: # Test xd -> @-rn.
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        init
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        _setsz
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        _setpr
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        mov #40, r0
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        shll8 r0
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        # Preserve r0.
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        mov r0, r1
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        fmov dr0, xd0
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        fmov xd0, @-r0
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        fmov @r0, xd2
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        fmov xd2, dr2
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        fcmp/eq dr0, dr2
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        bt f10b
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        fail
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f10b:   # check pre-dec.
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        add #8, r0
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        cmp/eq r0, r1
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        bt fmov11
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        fail
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fmov11: # Test @rn+ -> fr.
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        init
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        _clrsz
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        _clrpr
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        mov #40, r0
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        shll8 r0
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        # Preserve r0.
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        mov r0, r1
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        fmov fr0, @r0
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        fmov @r0+, fr2
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        fcmp/eq fr0, fr2
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        bt f11b
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        fail
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f11b:   # check post-inc.
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        add #4, r1
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        cmp/eq r0, r1
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        bt fmov12
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        fail
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fmov12: # Test @rn+ -> dr.
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        init
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        _setsz
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        _setpr
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        mov #40, r0
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        shll8 r0
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        # preserve r0.
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        mov r0, r1
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        fmov dr0, @r0
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        fmov @r0+, dr2
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        fcmp/eq dr0, dr2
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        bt f12b
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        fail
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f12b:   # check post-inc.
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        add #8, r1
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        cmp/eq r0, r1
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        bt fmov13
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        fail
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fmov13: # Test @rn -> xd.
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        init
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        _setsz
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        _setpr
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        mov #40, r0
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        shll8 r0
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        # Preserve r0.
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        mov r0, r1
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        fmov dr0, xd0
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        fmov xd0, @r0
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        fmov @r0+, xd2
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        fmov xd2, dr2
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        fcmp/eq dr0, dr2
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        bt f13b
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        fail
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f13b:
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        add #8, r1
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        cmp/eq r0, r1
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        bt fmov14
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        fail
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fmov14: # Test fr -> @(r0,rn), @(r0, rn) -> fr.
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        init
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        _clrsz
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        _clrpr
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        mov #40, r0
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        shll8 r0
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        mov #0, r1
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        fmov fr0, @(r0, r1)
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        fmov @(r0, r1), fr1
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        fcmp/eq fr0, fr1
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        bt fmov15
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        fail
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fmov15: # Test dr -> @(r0, rn), @(r0, rn) -> dr.
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        init
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        _setsz
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        _setpr
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        mov #40, r0
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        shll8 r0
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        mov #0, r1
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        fmov dr0, @(r0, r1)
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        fmov @(r0, r1), dr2
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        fcmp/eq dr0, dr2
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        bt fmov16
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        fail
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fmov16: # Test xd -> @(r0, rn), @(r0, rn) -> xd.
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        init
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        _setsz
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        _setpr
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        mov #40, r0
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        shll8 r0
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        mov #0, r1
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        fmov dr0, xd0
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        fmov xd0, @(r0, r1)
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        fmov @(r0, r1), xd2
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        fmov xd2, dr2
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        fcmp/eq dr0, dr2
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        bt okay
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        fail
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okay:
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        pass

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