OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh64/] [compact/] [movw3.cgs] - Blame information for rev 280

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# sh testcase for mov.w $rm, @(r0, $rn) -*- Asm -*-
2
# mach: all
3
# as: -isa=shcompact
4
# ld: -m shelf32
5
 
6
        .include "compact/testutils.inc"
7
 
8
        start
9
 
10
        mov #0, r0
11
        mov #30, r1
12
        shll8 r1
13
init:
14
        # Build up a distinctive bit pattern.
15
        mov #1, r2
16
        shll8 r2
17
        add #12, r2
18
        mov.w r2, @(r0, r1)
19
check:
20
        # Read it back.
21
        mov.w @(r0, r1), r3
22
        shll16 r2
23
        shll16 r3
24
        cmp/eq r2, r3
25
        bf wrong
26
 
27
okay:
28
        pass
29
wrong:
30
        fail
31
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.