OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh64/] [compact/] [movw6.cgs] - Blame information for rev 280

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# sh testcase for mov.w @$rm, $rn -*- Asm -*-
2
# mach: all
3
# as: -isa=shcompact
4
# ld: -m shelf32
5
 
6
        .include "compact/testutils.inc"
7
 
8
        start
9
 
10
        mov #30, r0
11
        shll8 r0
12
 
13
        # Store something first.
14
        # Build up a distinctive bit pattern.
15
        mov #1, r2
16
        shll8 r2
17
        add #12, r2
18
        mov.w r2, @r0
19
 
20
check:
21
        # Read it back.
22
        mov.w @r0, r1
23
        cmp/eq r1, r2
24
        bf wrong
25
 
26
okay:
27
        pass
28
wrong:
29
        fail
30
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.