OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh64/] [compact/] [shad.cgs] - Blame information for rev 280

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# sh testcase for shad $rm, $rn -*- Asm -*-
2
# mach: all
3
# as: -isa=shcompact
4
# ld: -m shelf32
5
 
6
        .include "compact/testutils.inc"
7
 
8
        start
9
 
10
        .global null
11
null:
12
        mov #1, r0
13
        mov #0, r1
14
        shad r1, r0
15
        # no shift is performed.
16
        assert r0, #1
17
 
18
        .global gt0
19
gt0:
20
        mov #4, r0
21
        mov #3, r1
22
        shad r1, r0
23
        # shift left 3 bits.
24
        assert r0, #32
25
 
26
        .global lt0
27
lt0:
28
        mov #32, r0
29
        mov #3, r1
30
        neg r1, r1
31
        shad r1, r0
32
        # shift right 3 bits.
33
        assert r0, #4
34
 
35
        .global fillpos
36
fillpos:
37
        mov #1, r0
38
        mov #1, r1
39
        rotr r1
40
        shad r1, r0
41
        # check result.
42
        assert r0, #0
43
 
44
        .global fillneg
45
fillneg:
46
        mov #1, r0
47
        neg r0, r0
48
        mov #1, r1
49
        rotr r1
50
        shad r1, r0
51
        # check result.
52
        not r0, r0
53
        assert r0, #0
54
 
55
okay:
56
        pass
57
wrong:
58
        fail

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.