OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh64/] [media/] [addl.cgs] - Blame information for rev 280

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# sh testcase for add.l $rm, $rn, $rd -*- Asm -*-
2
# mach: all
3
# as: -isa=shmedia
4
# ld: -m shelf64
5
 
6
        .include "media/testutils.inc"
7
 
8
        start
9
 
10
        .global addl
11
init:
12
        pta wrong, tr0
13
 
14
addl0:
15
        movi 1, r63
16
        add.l r63, r63, r1
17
        bnei r1, 0, tr0
18
 
19
addl1:
20
        movi 10, r0
21
        movi 0, r1
22
        add.l r0, r1, r3
23
        movi 10, r4
24
        bne r3, r4, tr0
25
 
26
addl2:
27
        movi 0, r0
28
        movi 10, r1
29
        add.l r0, r1, r2
30
        movi 10, r3
31
        bne r2, r3, tr0
32
 
33
addl3:
34
        movi 10, r0
35
        add.l r63, r0, r1
36
        movi 10, r2
37
        bne r1, r2, tr0
38
 
39
addl4:
40
        movi 10, r0
41
        add.l r0, r63, r1
42
        movi 10, r2
43
        bne r1, r2, tr0
44
 
45
addl5:
46
        # Ensure top 32-bits are discarded when adding.
47
        movi 10, r0
48
        shlli r0, 32, r0
49
        addi r0, 10, r0
50
        movi 10, r1
51
        shlli r1, 32, r1
52
        addi r1, 10, r1
53
        add.l r0, r1, r2
54
        movi 20, r3
55
        bne r2, r3, tr0
56
 
57
okay:
58
        pass
59
 
60
wrong:
61
        fail

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.