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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [v850/] [divhu.cgs] - Blame information for rev 225

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Line No. Rev Author Line
1 24 jeremybenn
# v850 divu
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# mach: v850e
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# as(v850e): -mv850e
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        .include "testutils.inc"
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        seti    6, r1
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        seti    45, r2
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        divu    r1, r2, r3
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        flags   0
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        reg     r1, 6
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        reg     r2, 7
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        reg     r3, 3
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        seti    4, r1
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        seti    0x40000000, r2
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        divu    r1, r2, r3
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        flags   0
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        reg     r1, 4
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        reg     r2, 0x10000000
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        reg     r3, 0
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# Only the lower half of the dividend is used
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        seti    0x00010006, r1
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        seti    45, r2
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        divhu   r1, r2, r3
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        flags   0
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        reg     r1, 0x00010006
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        reg     r2, 7
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        reg     r3, 3
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# If the data is divided by zero, OV=1 and the quotient is undefined.
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# According to NEC, the S and Z flags, and the output registers, are
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# unchanged.
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        noflags
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        seti    0, r1
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        seti    45, r2
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        seti    67, r3
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        divu    r1, r2, r3
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        flags   v
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        reg     r2, 45
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        reg     r3, 67
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        allflags
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        seti    0, r1
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        seti    45, r2
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        seti    67, r3
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        divu    r1, r2, r3
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        flags   sat + c + v + s + z
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        reg     r2, 45
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        reg     r3, 67
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# Zero / (N!=0) => normal
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        noflags
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        seti    45, r1
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        seti    0, r2
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        seti    67, r3
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        divu    r1, r2, r3
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        flags   z
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        reg     r1, 45
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        reg     r2, 0
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        reg     r3, 0
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# The Z flag is based on the quotient, not the remainder
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        noflags
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        seti    45, r1
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        seti    16, r2
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        divu    r1, r2, r3
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        flags   z
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        reg     r2, 0
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        reg     r3, 16
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# If the quot and rem registers are the same, the remainder is stored.
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        seti    6, r1
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        seti    45, r2
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        divu    r1, r2, r2
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        flags   0
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        reg     r1, 6
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        reg     r2, 3
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        pass

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