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# v850 shr
# mach: all
 
        .include "testutils.inc"
 
# CY is set to 1 if the bit shifted out last is 1, else 0
# OV is set to zero.
# Z is set if the result is 0, else 0
 
        noflags
        seti    4, r1
        seti    0x00000000, r2
        shr     r1, r2
 
        flags   z
        reg     r2, 0
 
        noflags
        seti    4, r1
        seti    0x00000001, r2
        shr     r1, r2
 
        flags   z
        reg     r2, 0
 
        noflags
        seti    4, r1
        seti    0x00000008, r2
        shr     r1, r2
 
        flags   c + z
        reg     r2, 0
 
        noflags
        seti    0x00000000, r2
        shr     4, r2
 
        flags   z
        reg     r2, 0
 
        noflags
        seti    0x00000001, r2
        shr     4, r2
 
        flags   z
        reg     r2, 0
 
        noflags
        seti    0x00000008, r2
        shr     4, r2
 
        flags   c + z
        reg     r2, 0
 
# However, if the number of shifts is 0, CY is 0.
 
        noflags
        seti    0, r1
        seti    0xffffffff, r2
        shr     r1, r2
 
        flags   s
        reg     r2, 0xffffffff
 
        noflags
        seti    0xffffffff, r2
        shr     0, r2
 
        flags   s
        reg     r2, 0xffffffff
 
# Zere is shifted into the MSB
# S is 1 if the result is negative, else 0
 
        noflags
        seti    1, r1
        seti    0x80000000, r2
        shr     r1, r2
 
        flags   0
        reg     r2, 0x40000000
 
        noflags
        seti    1, r1
        seti    0x40000000, r2
        shr     r1, r2
 
        flags   0
        reg     r2, 0x20000000
 
        pass

Line No.	Rev	Author	Line
1	24	jeremybenn	`# v850 shr`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`# CY is set to 1 if the bit shifted out last is 1, else 0`
7			`# OV is set to zero.`
8			`# Z is set if the result is 0, else 0`
9
10			`noflags`
11			`seti 4, r1`
12			`seti 0x00000000, r2`
13			`shr r1, r2`
14
15			`flags z`
16			`reg r2, 0`
17
18			`noflags`
19			`seti 4, r1`
20			`seti 0x00000001, r2`
21			`shr r1, r2`
22
23			`flags z`
24			`reg r2, 0`
25
26			`noflags`
27			`seti 4, r1`
28			`seti 0x00000008, r2`
29			`shr r1, r2`
30
31			`flags c + z`
32			`reg r2, 0`
33
34			`noflags`
35			`seti 0x00000000, r2`
36			`shr 4, r2`
37
38			`flags z`
39			`reg r2, 0`
40
41			`noflags`
42			`seti 0x00000001, r2`
43			`shr 4, r2`
44
45			`flags z`
46			`reg r2, 0`
47
48			`noflags`
49			`seti 0x00000008, r2`
50			`shr 4, r2`
51
52			`flags c + z`
53			`reg r2, 0`
54
55			`# However, if the number of shifts is 0, CY is 0.`
56
57			`noflags`
58			`seti 0, r1`
59			`seti 0xffffffff, r2`
60			`shr r1, r2`
61
62			`flags s`
63			`reg r2, 0xffffffff`
64
65			`noflags`
66			`seti 0xffffffff, r2`
67			`shr 0, r2`
68
69			`flags s`
70			`reg r2, 0xffffffff`
71
72			`# Zere is shifted into the MSB`
73			`# S is 1 if the result is negative, else 0`
74
75			`noflags`
76			`seti 1, r1`
77			`seti 0x80000000, r2`
78			`shr r1, r2`
79
80			`flags 0`
81			`reg r2, 0x40000000`
82
83			`noflags`
84			`seti 1, r1`
85			`seti 0x40000000, r2`
86			`shr r1, r2`
87
88			`flags 0`
89			`reg r2, 0x20000000`
90
91			`pass`

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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [v850/] [shr.cgs] - Blame information for rev 24