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1 227 jeremybenn
@section Relocations
2
BFD maintains relocations in much the same way it maintains
3
symbols: they are left alone until required, then read in
4
en-masse and translated into an internal form.  A common
5
routine @code{bfd_perform_relocation} acts upon the
6
canonical form to do the fixup.
7
 
8
Relocations are maintained on a per section basis,
9
while symbols are maintained on a per BFD basis.
10
 
11
All that a back end has to do to fit the BFD interface is to create
12
a @code{struct reloc_cache_entry} for each relocation
13
in a particular section, and fill in the right bits of the structures.
14
 
15
@menu
16
* typedef arelent::
17
* howto manager::
18
@end menu
19
 
20
 
21
@node typedef arelent, howto manager, Relocations, Relocations
22
@subsection typedef arelent
23
This is the structure of a relocation entry:
24
 
25
 
26
@example
27
 
28
typedef enum bfd_reloc_status
29
@{
30
  /* No errors detected.  */
31
  bfd_reloc_ok,
32
 
33
  /* The relocation was performed, but there was an overflow.  */
34
  bfd_reloc_overflow,
35
 
36
  /* The address to relocate was not within the section supplied.  */
37
  bfd_reloc_outofrange,
38
 
39
  /* Used by special functions.  */
40
  bfd_reloc_continue,
41
 
42
  /* Unsupported relocation size requested.  */
43
  bfd_reloc_notsupported,
44
 
45
  /* Unused.  */
46
  bfd_reloc_other,
47
 
48
  /* The symbol to relocate against was undefined.  */
49
  bfd_reloc_undefined,
50
 
51
  /* The relocation was performed, but may not be ok - presently
52
     generated only when linking i960 coff files with i960 b.out
53
     symbols.  If this type is returned, the error_message argument
54
     to bfd_perform_relocation will be set.  */
55
  bfd_reloc_dangerous
56
 @}
57
 bfd_reloc_status_type;
58
 
59
 
60
typedef struct reloc_cache_entry
61
@{
62
  /* A pointer into the canonical table of pointers.  */
63
  struct bfd_symbol **sym_ptr_ptr;
64
 
65
  /* offset in section.  */
66
  bfd_size_type address;
67
 
68
  /* addend for relocation value.  */
69
  bfd_vma addend;
70
 
71
  /* Pointer to how to perform the required relocation.  */
72
  reloc_howto_type *howto;
73
 
74
@}
75
arelent;
76
 
77
@end example
78
@strong{Description}@*
79
Here is a description of each of the fields within an @code{arelent}:
80
 
81
@itemize @bullet
82
 
83
@item
84
@code{sym_ptr_ptr}
85
@end itemize
86
The symbol table pointer points to a pointer to the symbol
87
associated with the relocation request.  It is the pointer
88
into the table returned by the back end's
89
@code{canonicalize_symtab} action. @xref{Symbols}. The symbol is
90
referenced through a pointer to a pointer so that tools like
91
the linker can fix up all the symbols of the same name by
92
modifying only one pointer. The relocation routine looks in
93
the symbol and uses the base of the section the symbol is
94
attached to and the value of the symbol as the initial
95
relocation offset. If the symbol pointer is zero, then the
96
section provided is looked up.
97
 
98
@itemize @bullet
99
 
100
@item
101
@code{address}
102
@end itemize
103
The @code{address} field gives the offset in bytes from the base of
104
the section data which owns the relocation record to the first
105
byte of relocatable information. The actual data relocated
106
will be relative to this point; for example, a relocation
107
type which modifies the bottom two bytes of a four byte word
108
would not touch the first byte pointed to in a big endian
109
world.
110
 
111
@itemize @bullet
112
 
113
@item
114
@code{addend}
115
@end itemize
116
The @code{addend} is a value provided by the back end to be added (!)
117
to the relocation offset. Its interpretation is dependent upon
118
the howto. For example, on the 68k the code:
119
 
120
@example
121
        char foo[];
122
        main()
123
                @{
124
                return foo[0x12345678];
125
                @}
126
@end example
127
 
128
Could be compiled into:
129
 
130
@example
131
        linkw fp,#-4
132
        moveb @@#12345678,d0
133
        extbl d0
134
        unlk fp
135
        rts
136
@end example
137
 
138
This could create a reloc pointing to @code{foo}, but leave the
139
offset in the data, something like:
140
 
141
@example
142
RELOCATION RECORDS FOR [.text]:
143
offset   type      value
144
00000006 32        _foo
145
 
146
00000000 4e56 fffc          ; linkw fp,#-4
147
00000004 1039 1234 5678     ; moveb @@#12345678,d0
148
0000000a 49c0               ; extbl d0
149
0000000c 4e5e               ; unlk fp
150
0000000e 4e75               ; rts
151
@end example
152
 
153
Using coff and an 88k, some instructions don't have enough
154
space in them to represent the full address range, and
155
pointers have to be loaded in two parts. So you'd get something like:
156
 
157
@example
158
        or.u     r13,r0,hi16(_foo+0x12345678)
159
        ld.b     r2,r13,lo16(_foo+0x12345678)
160
        jmp      r1
161
@end example
162
 
163
This should create two relocs, both pointing to @code{_foo}, and with
164
0x12340000 in their addend field. The data would consist of:
165
 
166
@example
167
RELOCATION RECORDS FOR [.text]:
168
offset   type      value
169
00000002 HVRT16    _foo+0x12340000
170
00000006 LVRT16    _foo+0x12340000
171
 
172
00000000 5da05678           ; or.u r13,r0,0x5678
173
00000004 1c4d5678           ; ld.b r2,r13,0x5678
174
00000008 f400c001           ; jmp r1
175
@end example
176
 
177
The relocation routine digs out the value from the data, adds
178
it to the addend to get the original offset, and then adds the
179
value of @code{_foo}. Note that all 32 bits have to be kept around
180
somewhere, to cope with carry from bit 15 to bit 16.
181
 
182
One further example is the sparc and the a.out format. The
183
sparc has a similar problem to the 88k, in that some
184
instructions don't have room for an entire offset, but on the
185
sparc the parts are created in odd sized lumps. The designers of
186
the a.out format chose to not use the data within the section
187
for storing part of the offset; all the offset is kept within
188
the reloc. Anything in the data should be ignored.
189
 
190
@example
191
        save %sp,-112,%sp
192
        sethi %hi(_foo+0x12345678),%g2
193
        ldsb [%g2+%lo(_foo+0x12345678)],%i0
194
        ret
195
        restore
196
@end example
197
 
198
Both relocs contain a pointer to @code{foo}, and the offsets
199
contain junk.
200
 
201
@example
202
RELOCATION RECORDS FOR [.text]:
203
offset   type      value
204
00000004 HI22      _foo+0x12345678
205
00000008 LO10      _foo+0x12345678
206
 
207
00000000 9de3bf90     ; save %sp,-112,%sp
208
00000004 05000000     ; sethi %hi(_foo+0),%g2
209
00000008 f048a000     ; ldsb [%g2+%lo(_foo+0)],%i0
210
0000000c 81c7e008     ; ret
211
00000010 81e80000     ; restore
212
@end example
213
 
214
@itemize @bullet
215
 
216
@item
217
@code{howto}
218
@end itemize
219
The @code{howto} field can be imagined as a
220
relocation instruction. It is a pointer to a structure which
221
contains information on what to do with all of the other
222
information in the reloc record and data section. A back end
223
would normally have a relocation instruction set and turn
224
relocations into pointers to the correct structure on input -
225
but it would be possible to create each howto field on demand.
226
 
227
@subsubsection @code{enum complain_overflow}
228
Indicates what sort of overflow checking should be done when
229
performing a relocation.
230
 
231
 
232
@example
233
 
234
enum complain_overflow
235
@{
236
  /* Do not complain on overflow.  */
237
  complain_overflow_dont,
238
 
239
  /* Complain if the value overflows when considered as a signed
240
     number one bit larger than the field.  ie. A bitfield of N bits
241
     is allowed to represent -2**n to 2**n-1.  */
242
  complain_overflow_bitfield,
243
 
244
  /* Complain if the value overflows when considered as a signed
245
     number.  */
246
  complain_overflow_signed,
247
 
248
  /* Complain if the value overflows when considered as an
249
     unsigned number.  */
250
  complain_overflow_unsigned
251
@};
252
@end example
253
@subsubsection @code{reloc_howto_type}
254
The @code{reloc_howto_type} is a structure which contains all the
255
information that libbfd needs to know to tie up a back end's data.
256
 
257
 
258
@example
259
struct bfd_symbol;             /* Forward declaration.  */
260
 
261
struct reloc_howto_struct
262
@{
263
  /*  The type field has mainly a documentary use - the back end can
264
      do what it wants with it, though normally the back end's
265
      external idea of what a reloc number is stored
266
      in this field.  For example, a PC relative word relocation
267
      in a coff environment has the type 023 - because that's
268
      what the outside world calls a R_PCRWORD reloc.  */
269
  unsigned int type;
270
 
271
  /*  The value the final relocation is shifted right by.  This drops
272
      unwanted data from the relocation.  */
273
  unsigned int rightshift;
274
 
275
  /*  The size of the item to be relocated.  This is *not* a
276
      power-of-two measure.  To get the number of bytes operated
277
      on by a type of relocation, use bfd_get_reloc_size.  */
278
  int size;
279
 
280
  /*  The number of bits in the item to be relocated.  This is used
281
      when doing overflow checking.  */
282
  unsigned int bitsize;
283
 
284
  /*  Notes that the relocation is relative to the location in the
285
      data section of the addend.  The relocation function will
286
      subtract from the relocation value the address of the location
287
      being relocated.  */
288
  bfd_boolean pc_relative;
289
 
290
  /*  The bit position of the reloc value in the destination.
291
      The relocated value is left shifted by this amount.  */
292
  unsigned int bitpos;
293
 
294
  /* What type of overflow error should be checked for when
295
     relocating.  */
296
  enum complain_overflow complain_on_overflow;
297
 
298
  /* If this field is non null, then the supplied function is
299
     called rather than the normal function.  This allows really
300
     strange relocation methods to be accommodated (e.g., i960 callj
301
     instructions).  */
302
  bfd_reloc_status_type (*special_function)
303
    (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
304
     bfd *, char **);
305
 
306
  /* The textual name of the relocation type.  */
307
  char *name;
308
 
309
  /* Some formats record a relocation addend in the section contents
310
     rather than with the relocation.  For ELF formats this is the
311
     distinction between USE_REL and USE_RELA (though the code checks
312
     for USE_REL == 1/0).  The value of this field is TRUE if the
313
     addend is recorded with the section contents; when performing a
314
     partial link (ld -r) the section contents (the data) will be
315
     modified.  The value of this field is FALSE if addends are
316
     recorded with the relocation (in arelent.addend); when performing
317
     a partial link the relocation will be modified.
318
     All relocations for all ELF USE_RELA targets should set this field
319
     to FALSE (values of TRUE should be looked on with suspicion).
320
     However, the converse is not true: not all relocations of all ELF
321
     USE_REL targets set this field to TRUE.  Why this is so is peculiar
322
     to each particular target.  For relocs that aren't used in partial
323
     links (e.g. GOT stuff) it doesn't matter what this is set to.  */
324
  bfd_boolean partial_inplace;
325
 
326
  /* src_mask selects the part of the instruction (or data) to be used
327
     in the relocation sum.  If the target relocations don't have an
328
     addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
329
     dst_mask to extract the addend from the section contents.  If
330
     relocations do have an addend in the reloc, eg. ELF USE_RELA, this
331
     field should be zero.  Non-zero values for ELF USE_RELA targets are
332
     bogus as in those cases the value in the dst_mask part of the
333
     section contents should be treated as garbage.  */
334
  bfd_vma src_mask;
335
 
336
  /* dst_mask selects which parts of the instruction (or data) are
337
     replaced with a relocated value.  */
338
  bfd_vma dst_mask;
339
 
340
  /* When some formats create PC relative instructions, they leave
341
     the value of the pc of the place being relocated in the offset
342
     slot of the instruction, so that a PC relative relocation can
343
     be made just by adding in an ordinary offset (e.g., sun3 a.out).
344
     Some formats leave the displacement part of an instruction
345
     empty (e.g., m88k bcs); this flag signals the fact.  */
346
  bfd_boolean pcrel_offset;
347
@};
348
 
349
@end example
350
@findex The HOWTO Macro
351
@subsubsection @code{The HOWTO Macro}
352
@strong{Description}@*
353
The HOWTO define is horrible and will go away.
354
@example
355
#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
356
  @{ (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC @}
357
@end example
358
 
359
@strong{Description}@*
360
And will be replaced with the totally magic way. But for the
361
moment, we are compatible, so do it this way.
362
@example
363
#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
364
  HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
365
         NAME, FALSE, 0, 0, IN)
366
 
367
@end example
368
 
369
@strong{Description}@*
370
This is used to fill in an empty howto entry in an array.
371
@example
372
#define EMPTY_HOWTO(C) \
373
  HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
374
         NULL, FALSE, 0, 0, FALSE)
375
 
376
@end example
377
 
378
@strong{Description}@*
379
Helper routine to turn a symbol into a relocation value.
380
@example
381
#define HOWTO_PREPARE(relocation, symbol)               \
382
  @{                                                     \
383
    if (symbol != NULL)                                 \
384
      @{                                                 \
385
        if (bfd_is_com_section (symbol->section))       \
386
          @{                                             \
387
            relocation = 0;                             \
388
          @}                                             \
389
        else                                            \
390
          @{                                             \
391
            relocation = symbol->value;                 \
392
          @}                                             \
393
      @}                                                 \
394
  @}
395
 
396
@end example
397
 
398
@findex bfd_get_reloc_size
399
@subsubsection @code{bfd_get_reloc_size}
400
@strong{Synopsis}
401
@example
402
unsigned int bfd_get_reloc_size (reloc_howto_type *);
403
@end example
404
@strong{Description}@*
405
For a reloc_howto_type that operates on a fixed number of bytes,
406
this returns the number of bytes operated on.
407
 
408
@findex arelent_chain
409
@subsubsection @code{arelent_chain}
410
@strong{Description}@*
411
How relocs are tied together in an @code{asection}:
412
@example
413
typedef struct relent_chain
414
@{
415
  arelent relent;
416
  struct relent_chain *next;
417
@}
418
arelent_chain;
419
 
420
@end example
421
 
422
@findex bfd_check_overflow
423
@subsubsection @code{bfd_check_overflow}
424
@strong{Synopsis}
425
@example
426
bfd_reloc_status_type bfd_check_overflow
427
   (enum complain_overflow how,
428
    unsigned int bitsize,
429
    unsigned int rightshift,
430
    unsigned int addrsize,
431
    bfd_vma relocation);
432
@end example
433
@strong{Description}@*
434
Perform overflow checking on @var{relocation} which has
435
@var{bitsize} significant bits and will be shifted right by
436
@var{rightshift} bits, on a machine with addresses containing
437
@var{addrsize} significant bits.  The result is either of
438
@code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
439
 
440
@findex bfd_perform_relocation
441
@subsubsection @code{bfd_perform_relocation}
442
@strong{Synopsis}
443
@example
444
bfd_reloc_status_type bfd_perform_relocation
445
   (bfd *abfd,
446
    arelent *reloc_entry,
447
    void *data,
448
    asection *input_section,
449
    bfd *output_bfd,
450
    char **error_message);
451
@end example
452
@strong{Description}@*
453
If @var{output_bfd} is supplied to this function, the
454
generated image will be relocatable; the relocations are
455
copied to the output file after they have been changed to
456
reflect the new state of the world. There are two ways of
457
reflecting the results of partial linkage in an output file:
458
by modifying the output data in place, and by modifying the
459
relocation record.  Some native formats (e.g., basic a.out and
460
basic coff) have no way of specifying an addend in the
461
relocation type, so the addend has to go in the output data.
462
This is no big deal since in these formats the output data
463
slot will always be big enough for the addend. Complex reloc
464
types with addends were invented to solve just this problem.
465
The @var{error_message} argument is set to an error message if
466
this return @code{bfd_reloc_dangerous}.
467
 
468
@findex bfd_install_relocation
469
@subsubsection @code{bfd_install_relocation}
470
@strong{Synopsis}
471
@example
472
bfd_reloc_status_type bfd_install_relocation
473
   (bfd *abfd,
474
    arelent *reloc_entry,
475
    void *data, bfd_vma data_start,
476
    asection *input_section,
477
    char **error_message);
478
@end example
479
@strong{Description}@*
480
This looks remarkably like @code{bfd_perform_relocation}, except it
481
does not expect that the section contents have been filled in.
482
I.e., it's suitable for use when creating, rather than applying
483
a relocation.
484
 
485
For now, this function should be considered reserved for the
486
assembler.
487
 
488
 
489
@node howto manager,  , typedef arelent, Relocations
490
@subsection The howto manager
491
When an application wants to create a relocation, but doesn't
492
know what the target machine might call it, it can find out by
493
using this bit of code.
494
 
495
@findex bfd_reloc_code_type
496
@subsubsection @code{bfd_reloc_code_type}
497
@strong{Description}@*
498
The insides of a reloc code.  The idea is that, eventually, there
499
will be one enumerator for every type of relocation we ever do.
500
Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll
501
return a howto pointer.
502
 
503
This does mean that the application must determine the correct
504
enumerator value; you can't get a howto pointer from a random set
505
of attributes.
506
 
507
Here are the possible values for @code{enum bfd_reloc_code_real}:
508
 
509
@deffn {} BFD_RELOC_64
510
@deffnx {} BFD_RELOC_32
511
@deffnx {} BFD_RELOC_26
512
@deffnx {} BFD_RELOC_24
513
@deffnx {} BFD_RELOC_16
514
@deffnx {} BFD_RELOC_14
515
@deffnx {} BFD_RELOC_8
516
Basic absolute relocations of N bits.
517
@end deffn
518
@deffn {} BFD_RELOC_64_PCREL
519
@deffnx {} BFD_RELOC_32_PCREL
520
@deffnx {} BFD_RELOC_24_PCREL
521
@deffnx {} BFD_RELOC_16_PCREL
522
@deffnx {} BFD_RELOC_12_PCREL
523
@deffnx {} BFD_RELOC_8_PCREL
524
PC-relative relocations.  Sometimes these are relative to the address
525
of the relocation itself; sometimes they are relative to the start of
526
the section containing the relocation.  It depends on the specific target.
527
 
528
The 24-bit relocation is used in some Intel 960 configurations.
529
@end deffn
530
@deffn {} BFD_RELOC_32_SECREL
531
Section relative relocations.  Some targets need this for DWARF2.
532
@end deffn
533
@deffn {} BFD_RELOC_32_GOT_PCREL
534
@deffnx {} BFD_RELOC_16_GOT_PCREL
535
@deffnx {} BFD_RELOC_8_GOT_PCREL
536
@deffnx {} BFD_RELOC_32_GOTOFF
537
@deffnx {} BFD_RELOC_16_GOTOFF
538
@deffnx {} BFD_RELOC_LO16_GOTOFF
539
@deffnx {} BFD_RELOC_HI16_GOTOFF
540
@deffnx {} BFD_RELOC_HI16_S_GOTOFF
541
@deffnx {} BFD_RELOC_8_GOTOFF
542
@deffnx {} BFD_RELOC_64_PLT_PCREL
543
@deffnx {} BFD_RELOC_32_PLT_PCREL
544
@deffnx {} BFD_RELOC_24_PLT_PCREL
545
@deffnx {} BFD_RELOC_16_PLT_PCREL
546
@deffnx {} BFD_RELOC_8_PLT_PCREL
547
@deffnx {} BFD_RELOC_64_PLTOFF
548
@deffnx {} BFD_RELOC_32_PLTOFF
549
@deffnx {} BFD_RELOC_16_PLTOFF
550
@deffnx {} BFD_RELOC_LO16_PLTOFF
551
@deffnx {} BFD_RELOC_HI16_PLTOFF
552
@deffnx {} BFD_RELOC_HI16_S_PLTOFF
553
@deffnx {} BFD_RELOC_8_PLTOFF
554
For ELF.
555
@end deffn
556
@deffn {} BFD_RELOC_68K_GLOB_DAT
557
@deffnx {} BFD_RELOC_68K_JMP_SLOT
558
@deffnx {} BFD_RELOC_68K_RELATIVE
559
@deffnx {} BFD_RELOC_68K_TLS_GD32
560
@deffnx {} BFD_RELOC_68K_TLS_GD16
561
@deffnx {} BFD_RELOC_68K_TLS_GD8
562
@deffnx {} BFD_RELOC_68K_TLS_LDM32
563
@deffnx {} BFD_RELOC_68K_TLS_LDM16
564
@deffnx {} BFD_RELOC_68K_TLS_LDM8
565
@deffnx {} BFD_RELOC_68K_TLS_LDO32
566
@deffnx {} BFD_RELOC_68K_TLS_LDO16
567
@deffnx {} BFD_RELOC_68K_TLS_LDO8
568
@deffnx {} BFD_RELOC_68K_TLS_IE32
569
@deffnx {} BFD_RELOC_68K_TLS_IE16
570
@deffnx {} BFD_RELOC_68K_TLS_IE8
571
@deffnx {} BFD_RELOC_68K_TLS_LE32
572
@deffnx {} BFD_RELOC_68K_TLS_LE16
573
@deffnx {} BFD_RELOC_68K_TLS_LE8
574
Relocations used by 68K ELF.
575
@end deffn
576
@deffn {} BFD_RELOC_32_BASEREL
577
@deffnx {} BFD_RELOC_16_BASEREL
578
@deffnx {} BFD_RELOC_LO16_BASEREL
579
@deffnx {} BFD_RELOC_HI16_BASEREL
580
@deffnx {} BFD_RELOC_HI16_S_BASEREL
581
@deffnx {} BFD_RELOC_8_BASEREL
582
@deffnx {} BFD_RELOC_RVA
583
Linkage-table relative.
584
@end deffn
585
@deffn {} BFD_RELOC_8_FFnn
586
Absolute 8-bit relocation, but used to form an address like 0xFFnn.
587
@end deffn
588
@deffn {} BFD_RELOC_32_PCREL_S2
589
@deffnx {} BFD_RELOC_16_PCREL_S2
590
@deffnx {} BFD_RELOC_23_PCREL_S2
591
These PC-relative relocations are stored as word displacements --
592
i.e., byte displacements shifted right two bits.  The 30-bit word
593
displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
594
SPARC.  (SPARC tools generally refer to this as <<WDISP30>>.)  The
595
signed 16-bit displacement is used on the MIPS, and the 23-bit
596
displacement is used on the Alpha.
597
@end deffn
598
@deffn {} BFD_RELOC_HI22
599
@deffnx {} BFD_RELOC_LO10
600
High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
601
the target word.  These are used on the SPARC.
602
@end deffn
603
@deffn {} BFD_RELOC_GPREL16
604
@deffnx {} BFD_RELOC_GPREL32
605
For systems that allocate a Global Pointer register, these are
606
displacements off that register.  These relocation types are
607
handled specially, because the value the register will have is
608
decided relatively late.
609
@end deffn
610
@deffn {} BFD_RELOC_I960_CALLJ
611
Reloc types used for i960/b.out.
612
@end deffn
613
@deffn {} BFD_RELOC_NONE
614
@deffnx {} BFD_RELOC_SPARC_WDISP22
615
@deffnx {} BFD_RELOC_SPARC22
616
@deffnx {} BFD_RELOC_SPARC13
617
@deffnx {} BFD_RELOC_SPARC_GOT10
618
@deffnx {} BFD_RELOC_SPARC_GOT13
619
@deffnx {} BFD_RELOC_SPARC_GOT22
620
@deffnx {} BFD_RELOC_SPARC_PC10
621
@deffnx {} BFD_RELOC_SPARC_PC22
622
@deffnx {} BFD_RELOC_SPARC_WPLT30
623
@deffnx {} BFD_RELOC_SPARC_COPY
624
@deffnx {} BFD_RELOC_SPARC_GLOB_DAT
625
@deffnx {} BFD_RELOC_SPARC_JMP_SLOT
626
@deffnx {} BFD_RELOC_SPARC_RELATIVE
627
@deffnx {} BFD_RELOC_SPARC_UA16
628
@deffnx {} BFD_RELOC_SPARC_UA32
629
@deffnx {} BFD_RELOC_SPARC_UA64
630
@deffnx {} BFD_RELOC_SPARC_GOTDATA_HIX22
631
@deffnx {} BFD_RELOC_SPARC_GOTDATA_LOX10
632
@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_HIX22
633
@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_LOX10
634
@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP
635
@deffnx {} BFD_RELOC_SPARC_JMP_IREL
636
@deffnx {} BFD_RELOC_SPARC_IRELATIVE
637
SPARC ELF relocations.  There is probably some overlap with other
638
relocation types already defined.
639
@end deffn
640
@deffn {} BFD_RELOC_SPARC_BASE13
641
@deffnx {} BFD_RELOC_SPARC_BASE22
642
I think these are specific to SPARC a.out (e.g., Sun 4).
643
@end deffn
644
@deffn {} BFD_RELOC_SPARC_64
645
@deffnx {} BFD_RELOC_SPARC_10
646
@deffnx {} BFD_RELOC_SPARC_11
647
@deffnx {} BFD_RELOC_SPARC_OLO10
648
@deffnx {} BFD_RELOC_SPARC_HH22
649
@deffnx {} BFD_RELOC_SPARC_HM10
650
@deffnx {} BFD_RELOC_SPARC_LM22
651
@deffnx {} BFD_RELOC_SPARC_PC_HH22
652
@deffnx {} BFD_RELOC_SPARC_PC_HM10
653
@deffnx {} BFD_RELOC_SPARC_PC_LM22
654
@deffnx {} BFD_RELOC_SPARC_WDISP16
655
@deffnx {} BFD_RELOC_SPARC_WDISP19
656
@deffnx {} BFD_RELOC_SPARC_7
657
@deffnx {} BFD_RELOC_SPARC_6
658
@deffnx {} BFD_RELOC_SPARC_5
659
@deffnx {} BFD_RELOC_SPARC_DISP64
660
@deffnx {} BFD_RELOC_SPARC_PLT32
661
@deffnx {} BFD_RELOC_SPARC_PLT64
662
@deffnx {} BFD_RELOC_SPARC_HIX22
663
@deffnx {} BFD_RELOC_SPARC_LOX10
664
@deffnx {} BFD_RELOC_SPARC_H44
665
@deffnx {} BFD_RELOC_SPARC_M44
666
@deffnx {} BFD_RELOC_SPARC_L44
667
@deffnx {} BFD_RELOC_SPARC_REGISTER
668
SPARC64 relocations
669
@end deffn
670
@deffn {} BFD_RELOC_SPARC_REV32
671
SPARC little endian relocation
672
@end deffn
673
@deffn {} BFD_RELOC_SPARC_TLS_GD_HI22
674
@deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10
675
@deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD
676
@deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL
677
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22
678
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10
679
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD
680
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL
681
@deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22
682
@deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10
683
@deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD
684
@deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22
685
@deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10
686
@deffnx {} BFD_RELOC_SPARC_TLS_IE_LD
687
@deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX
688
@deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD
689
@deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22
690
@deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10
691
@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32
692
@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64
693
@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32
694
@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64
695
@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32
696
@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64
697
SPARC TLS relocations
698
@end deffn
699
@deffn {} BFD_RELOC_SPU_IMM7
700
@deffnx {} BFD_RELOC_SPU_IMM8
701
@deffnx {} BFD_RELOC_SPU_IMM10
702
@deffnx {} BFD_RELOC_SPU_IMM10W
703
@deffnx {} BFD_RELOC_SPU_IMM16
704
@deffnx {} BFD_RELOC_SPU_IMM16W
705
@deffnx {} BFD_RELOC_SPU_IMM18
706
@deffnx {} BFD_RELOC_SPU_PCREL9a
707
@deffnx {} BFD_RELOC_SPU_PCREL9b
708
@deffnx {} BFD_RELOC_SPU_PCREL16
709
@deffnx {} BFD_RELOC_SPU_LO16
710
@deffnx {} BFD_RELOC_SPU_HI16
711
@deffnx {} BFD_RELOC_SPU_PPU32
712
@deffnx {} BFD_RELOC_SPU_PPU64
713
@deffnx {} BFD_RELOC_SPU_ADD_PIC
714
SPU Relocations.
715
@end deffn
716
@deffn {} BFD_RELOC_ALPHA_GPDISP_HI16
717
Alpha ECOFF and ELF relocations.  Some of these treat the symbol or
718
"addend" in some special way.
719
For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
720
writing; when reading, it will be the absolute section symbol.  The
721
addend is the displacement in bytes of the "lda" instruction from
722
the "ldah" instruction (which is at the address of this reloc).
723
@end deffn
724
@deffn {} BFD_RELOC_ALPHA_GPDISP_LO16
725
For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
726
with GPDISP_HI16 relocs.  The addend is ignored when writing the
727
relocations out, and is filled in with the file's GP value on
728
reading, for convenience.
729
@end deffn
730
@deffn {} BFD_RELOC_ALPHA_GPDISP
731
The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
732
relocation except that there is no accompanying GPDISP_LO16
733
relocation.
734
@end deffn
735
@deffn {} BFD_RELOC_ALPHA_LITERAL
736
@deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL
737
@deffnx {} BFD_RELOC_ALPHA_LITUSE
738
The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
739
the assembler turns it into a LDQ instruction to load the address of
740
the symbol, and then fills in a register in the real instruction.
741
 
742
The LITERAL reloc, at the LDQ instruction, refers to the .lita
743
section symbol.  The addend is ignored when writing, but is filled
744
in with the file's GP value on reading, for convenience, as with the
745
GPDISP_LO16 reloc.
746
 
747
The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
748
It should refer to the symbol to be referenced, as with 16_GOTOFF,
749
but it generates output not based on the position within the .got
750
section, but relative to the GP value chosen for the file during the
751
final link stage.
752
 
753
The LITUSE reloc, on the instruction using the loaded address, gives
754
information to the linker that it might be able to use to optimize
755
away some literal section references.  The symbol is ignored (read
756
as the absolute section symbol), and the "addend" indicates the type
757
of instruction using the register:
758
1 - "memory" fmt insn
759
2 - byte-manipulation (byte offset reg)
760
3 - jsr (target of branch)
761
@end deffn
762
@deffn {} BFD_RELOC_ALPHA_HINT
763
The HINT relocation indicates a value that should be filled into the
764
"hint" field of a jmp/jsr/ret instruction, for possible branch-
765
prediction logic which may be provided on some processors.
766
@end deffn
767
@deffn {} BFD_RELOC_ALPHA_LINKAGE
768
The LINKAGE relocation outputs a linkage pair in the object file,
769
which is filled by the linker.
770
@end deffn
771
@deffn {} BFD_RELOC_ALPHA_CODEADDR
772
The CODEADDR relocation outputs a STO_CA in the object file,
773
which is filled by the linker.
774
@end deffn
775
@deffn {} BFD_RELOC_ALPHA_GPREL_HI16
776
@deffnx {} BFD_RELOC_ALPHA_GPREL_LO16
777
The GPREL_HI/LO relocations together form a 32-bit offset from the
778
GP register.
779
@end deffn
780
@deffn {} BFD_RELOC_ALPHA_BRSGP
781
Like BFD_RELOC_23_PCREL_S2, except that the source and target must
782
share a common GP, and the target address is adjusted for
783
STO_ALPHA_STD_GPLOAD.
784
@end deffn
785
@deffn {} BFD_RELOC_ALPHA_NOP
786
The NOP relocation outputs a NOP if the longword displacement
787
between two procedure entry points is < 2^21.
788
@end deffn
789
@deffn {} BFD_RELOC_ALPHA_BSR
790
The BSR relocation outputs a BSR if the longword displacement
791
between two procedure entry points is < 2^21.
792
@end deffn
793
@deffn {} BFD_RELOC_ALPHA_LDA
794
The LDA relocation outputs a LDA if the longword displacement
795
between two procedure entry points is < 2^16.
796
@end deffn
797
@deffn {} BFD_RELOC_ALPHA_BOH
798
The BOH relocation outputs a BSR if the longword displacement
799
between two procedure entry points is < 2^21, or else a hint.
800
@end deffn
801
@deffn {} BFD_RELOC_ALPHA_TLSGD
802
@deffnx {} BFD_RELOC_ALPHA_TLSLDM
803
@deffnx {} BFD_RELOC_ALPHA_DTPMOD64
804
@deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16
805
@deffnx {} BFD_RELOC_ALPHA_DTPREL64
806
@deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16
807
@deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16
808
@deffnx {} BFD_RELOC_ALPHA_DTPREL16
809
@deffnx {} BFD_RELOC_ALPHA_GOTTPREL16
810
@deffnx {} BFD_RELOC_ALPHA_TPREL64
811
@deffnx {} BFD_RELOC_ALPHA_TPREL_HI16
812
@deffnx {} BFD_RELOC_ALPHA_TPREL_LO16
813
@deffnx {} BFD_RELOC_ALPHA_TPREL16
814
Alpha thread-local storage relocations.
815
@end deffn
816
@deffn {} BFD_RELOC_MIPS_JMP
817
Bits 27..2 of the relocation address shifted right 2 bits;
818
simple reloc otherwise.
819
@end deffn
820
@deffn {} BFD_RELOC_MIPS16_JMP
821
The MIPS16 jump instruction.
822
@end deffn
823
@deffn {} BFD_RELOC_MIPS16_GPREL
824
MIPS16 GP relative reloc.
825
@end deffn
826
@deffn {} BFD_RELOC_HI16
827
High 16 bits of 32-bit value; simple reloc.
828
@end deffn
829
@deffn {} BFD_RELOC_HI16_S
830
High 16 bits of 32-bit value but the low 16 bits will be sign
831
extended and added to form the final result.  If the low 16
832
bits form a negative number, we need to add one to the high value
833
to compensate for the borrow when the low bits are added.
834
@end deffn
835
@deffn {} BFD_RELOC_LO16
836
Low 16 bits.
837
@end deffn
838
@deffn {} BFD_RELOC_HI16_PCREL
839
High 16 bits of 32-bit pc-relative value
840
@end deffn
841
@deffn {} BFD_RELOC_HI16_S_PCREL
842
High 16 bits of 32-bit pc-relative value, adjusted
843
@end deffn
844
@deffn {} BFD_RELOC_LO16_PCREL
845
Low 16 bits of pc-relative value
846
@end deffn
847
@deffn {} BFD_RELOC_MIPS16_GOT16
848
@deffnx {} BFD_RELOC_MIPS16_CALL16
849
Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
850
16-bit immediate fields
851
@end deffn
852
@deffn {} BFD_RELOC_MIPS16_HI16
853
MIPS16 high 16 bits of 32-bit value.
854
@end deffn
855
@deffn {} BFD_RELOC_MIPS16_HI16_S
856
MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
857
extended and added to form the final result.  If the low 16
858
bits form a negative number, we need to add one to the high value
859
to compensate for the borrow when the low bits are added.
860
@end deffn
861
@deffn {} BFD_RELOC_MIPS16_LO16
862
MIPS16 low 16 bits.
863
@end deffn
864
@deffn {} BFD_RELOC_MIPS_LITERAL
865
Relocation against a MIPS literal section.
866
@end deffn
867
@deffn {} BFD_RELOC_MIPS_GOT16
868
@deffnx {} BFD_RELOC_MIPS_CALL16
869
@deffnx {} BFD_RELOC_MIPS_GOT_HI16
870
@deffnx {} BFD_RELOC_MIPS_GOT_LO16
871
@deffnx {} BFD_RELOC_MIPS_CALL_HI16
872
@deffnx {} BFD_RELOC_MIPS_CALL_LO16
873
@deffnx {} BFD_RELOC_MIPS_SUB
874
@deffnx {} BFD_RELOC_MIPS_GOT_PAGE
875
@deffnx {} BFD_RELOC_MIPS_GOT_OFST
876
@deffnx {} BFD_RELOC_MIPS_GOT_DISP
877
@deffnx {} BFD_RELOC_MIPS_SHIFT5
878
@deffnx {} BFD_RELOC_MIPS_SHIFT6
879
@deffnx {} BFD_RELOC_MIPS_INSERT_A
880
@deffnx {} BFD_RELOC_MIPS_INSERT_B
881
@deffnx {} BFD_RELOC_MIPS_DELETE
882
@deffnx {} BFD_RELOC_MIPS_HIGHEST
883
@deffnx {} BFD_RELOC_MIPS_HIGHER
884
@deffnx {} BFD_RELOC_MIPS_SCN_DISP
885
@deffnx {} BFD_RELOC_MIPS_REL16
886
@deffnx {} BFD_RELOC_MIPS_RELGOT
887
@deffnx {} BFD_RELOC_MIPS_JALR
888
@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD32
889
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL32
890
@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD64
891
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL64
892
@deffnx {} BFD_RELOC_MIPS_TLS_GD
893
@deffnx {} BFD_RELOC_MIPS_TLS_LDM
894
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_HI16
895
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_LO16
896
@deffnx {} BFD_RELOC_MIPS_TLS_GOTTPREL
897
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL32
898
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL64
899
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_HI16
900
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_LO16
901
MIPS ELF relocations.
902
@end deffn
903
@deffn {} BFD_RELOC_MIPS_COPY
904
@deffnx {} BFD_RELOC_MIPS_JUMP_SLOT
905
MIPS ELF relocations (VxWorks and PLT extensions).
906
@end deffn
907
@deffn {} BFD_RELOC_MOXIE_10_PCREL
908
Moxie ELF relocations.
909
@end deffn
910
@deffn {} BFD_RELOC_FRV_LABEL16
911
@deffnx {} BFD_RELOC_FRV_LABEL24
912
@deffnx {} BFD_RELOC_FRV_LO16
913
@deffnx {} BFD_RELOC_FRV_HI16
914
@deffnx {} BFD_RELOC_FRV_GPREL12
915
@deffnx {} BFD_RELOC_FRV_GPRELU12
916
@deffnx {} BFD_RELOC_FRV_GPREL32
917
@deffnx {} BFD_RELOC_FRV_GPRELHI
918
@deffnx {} BFD_RELOC_FRV_GPRELLO
919
@deffnx {} BFD_RELOC_FRV_GOT12
920
@deffnx {} BFD_RELOC_FRV_GOTHI
921
@deffnx {} BFD_RELOC_FRV_GOTLO
922
@deffnx {} BFD_RELOC_FRV_FUNCDESC
923
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12
924
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI
925
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO
926
@deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE
927
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12
928
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
929
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
930
@deffnx {} BFD_RELOC_FRV_GOTOFF12
931
@deffnx {} BFD_RELOC_FRV_GOTOFFHI
932
@deffnx {} BFD_RELOC_FRV_GOTOFFLO
933
@deffnx {} BFD_RELOC_FRV_GETTLSOFF
934
@deffnx {} BFD_RELOC_FRV_TLSDESC_VALUE
935
@deffnx {} BFD_RELOC_FRV_GOTTLSDESC12
936
@deffnx {} BFD_RELOC_FRV_GOTTLSDESCHI
937
@deffnx {} BFD_RELOC_FRV_GOTTLSDESCLO
938
@deffnx {} BFD_RELOC_FRV_TLSMOFF12
939
@deffnx {} BFD_RELOC_FRV_TLSMOFFHI
940
@deffnx {} BFD_RELOC_FRV_TLSMOFFLO
941
@deffnx {} BFD_RELOC_FRV_GOTTLSOFF12
942
@deffnx {} BFD_RELOC_FRV_GOTTLSOFFHI
943
@deffnx {} BFD_RELOC_FRV_GOTTLSOFFLO
944
@deffnx {} BFD_RELOC_FRV_TLSOFF
945
@deffnx {} BFD_RELOC_FRV_TLSDESC_RELAX
946
@deffnx {} BFD_RELOC_FRV_GETTLSOFF_RELAX
947
@deffnx {} BFD_RELOC_FRV_TLSOFF_RELAX
948
@deffnx {} BFD_RELOC_FRV_TLSMOFF
949
Fujitsu Frv Relocations.
950
@end deffn
951
@deffn {} BFD_RELOC_MN10300_GOTOFF24
952
This is a 24bit GOT-relative reloc for the mn10300.
953
@end deffn
954
@deffn {} BFD_RELOC_MN10300_GOT32
955
This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
956
in the instruction.
957
@end deffn
958
@deffn {} BFD_RELOC_MN10300_GOT24
959
This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
960
in the instruction.
961
@end deffn
962
@deffn {} BFD_RELOC_MN10300_GOT16
963
This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
964
in the instruction.
965
@end deffn
966
@deffn {} BFD_RELOC_MN10300_COPY
967
Copy symbol at runtime.
968
@end deffn
969
@deffn {} BFD_RELOC_MN10300_GLOB_DAT
970
Create GOT entry.
971
@end deffn
972
@deffn {} BFD_RELOC_MN10300_JMP_SLOT
973
Create PLT entry.
974
@end deffn
975
@deffn {} BFD_RELOC_MN10300_RELATIVE
976
Adjust by program base.
977
@end deffn
978
@deffn {} BFD_RELOC_MN10300_SYM_DIFF
979
Together with another reloc targeted at the same location,
980
allows for a value that is the difference of two symbols
981
in the same section.
982
@end deffn
983
@deffn {} BFD_RELOC_MN10300_ALIGN
984
The addend of this reloc is an alignment power that must
985
be honoured at the offset's location, regardless of linker
986
relaxation.
987
@end deffn
988
@deffn {} BFD_RELOC_386_GOT32
989
@deffnx {} BFD_RELOC_386_PLT32
990
@deffnx {} BFD_RELOC_386_COPY
991
@deffnx {} BFD_RELOC_386_GLOB_DAT
992
@deffnx {} BFD_RELOC_386_JUMP_SLOT
993
@deffnx {} BFD_RELOC_386_RELATIVE
994
@deffnx {} BFD_RELOC_386_GOTOFF
995
@deffnx {} BFD_RELOC_386_GOTPC
996
@deffnx {} BFD_RELOC_386_TLS_TPOFF
997
@deffnx {} BFD_RELOC_386_TLS_IE
998
@deffnx {} BFD_RELOC_386_TLS_GOTIE
999
@deffnx {} BFD_RELOC_386_TLS_LE
1000
@deffnx {} BFD_RELOC_386_TLS_GD
1001
@deffnx {} BFD_RELOC_386_TLS_LDM
1002
@deffnx {} BFD_RELOC_386_TLS_LDO_32
1003
@deffnx {} BFD_RELOC_386_TLS_IE_32
1004
@deffnx {} BFD_RELOC_386_TLS_LE_32
1005
@deffnx {} BFD_RELOC_386_TLS_DTPMOD32
1006
@deffnx {} BFD_RELOC_386_TLS_DTPOFF32
1007
@deffnx {} BFD_RELOC_386_TLS_TPOFF32
1008
@deffnx {} BFD_RELOC_386_TLS_GOTDESC
1009
@deffnx {} BFD_RELOC_386_TLS_DESC_CALL
1010
@deffnx {} BFD_RELOC_386_TLS_DESC
1011
@deffnx {} BFD_RELOC_386_IRELATIVE
1012
i386/elf relocations
1013
@end deffn
1014
@deffn {} BFD_RELOC_X86_64_GOT32
1015
@deffnx {} BFD_RELOC_X86_64_PLT32
1016
@deffnx {} BFD_RELOC_X86_64_COPY
1017
@deffnx {} BFD_RELOC_X86_64_GLOB_DAT
1018
@deffnx {} BFD_RELOC_X86_64_JUMP_SLOT
1019
@deffnx {} BFD_RELOC_X86_64_RELATIVE
1020
@deffnx {} BFD_RELOC_X86_64_GOTPCREL
1021
@deffnx {} BFD_RELOC_X86_64_32S
1022
@deffnx {} BFD_RELOC_X86_64_DTPMOD64
1023
@deffnx {} BFD_RELOC_X86_64_DTPOFF64
1024
@deffnx {} BFD_RELOC_X86_64_TPOFF64
1025
@deffnx {} BFD_RELOC_X86_64_TLSGD
1026
@deffnx {} BFD_RELOC_X86_64_TLSLD
1027
@deffnx {} BFD_RELOC_X86_64_DTPOFF32
1028
@deffnx {} BFD_RELOC_X86_64_GOTTPOFF
1029
@deffnx {} BFD_RELOC_X86_64_TPOFF32
1030
@deffnx {} BFD_RELOC_X86_64_GOTOFF64
1031
@deffnx {} BFD_RELOC_X86_64_GOTPC32
1032
@deffnx {} BFD_RELOC_X86_64_GOT64
1033
@deffnx {} BFD_RELOC_X86_64_GOTPCREL64
1034
@deffnx {} BFD_RELOC_X86_64_GOTPC64
1035
@deffnx {} BFD_RELOC_X86_64_GOTPLT64
1036
@deffnx {} BFD_RELOC_X86_64_PLTOFF64
1037
@deffnx {} BFD_RELOC_X86_64_GOTPC32_TLSDESC
1038
@deffnx {} BFD_RELOC_X86_64_TLSDESC_CALL
1039
@deffnx {} BFD_RELOC_X86_64_TLSDESC
1040
@deffnx {} BFD_RELOC_X86_64_IRELATIVE
1041
x86-64/elf relocations
1042
@end deffn
1043
@deffn {} BFD_RELOC_NS32K_IMM_8
1044
@deffnx {} BFD_RELOC_NS32K_IMM_16
1045
@deffnx {} BFD_RELOC_NS32K_IMM_32
1046
@deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL
1047
@deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL
1048
@deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL
1049
@deffnx {} BFD_RELOC_NS32K_DISP_8
1050
@deffnx {} BFD_RELOC_NS32K_DISP_16
1051
@deffnx {} BFD_RELOC_NS32K_DISP_32
1052
@deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL
1053
@deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL
1054
@deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL
1055
ns32k relocations
1056
@end deffn
1057
@deffn {} BFD_RELOC_PDP11_DISP_8_PCREL
1058
@deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL
1059
PDP11 relocations
1060
@end deffn
1061
@deffn {} BFD_RELOC_PJ_CODE_HI16
1062
@deffnx {} BFD_RELOC_PJ_CODE_LO16
1063
@deffnx {} BFD_RELOC_PJ_CODE_DIR16
1064
@deffnx {} BFD_RELOC_PJ_CODE_DIR32
1065
@deffnx {} BFD_RELOC_PJ_CODE_REL16
1066
@deffnx {} BFD_RELOC_PJ_CODE_REL32
1067
Picojava relocs.  Not all of these appear in object files.
1068
@end deffn
1069
@deffn {} BFD_RELOC_PPC_B26
1070
@deffnx {} BFD_RELOC_PPC_BA26
1071
@deffnx {} BFD_RELOC_PPC_TOC16
1072
@deffnx {} BFD_RELOC_PPC_B16
1073
@deffnx {} BFD_RELOC_PPC_B16_BRTAKEN
1074
@deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN
1075
@deffnx {} BFD_RELOC_PPC_BA16
1076
@deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN
1077
@deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN
1078
@deffnx {} BFD_RELOC_PPC_COPY
1079
@deffnx {} BFD_RELOC_PPC_GLOB_DAT
1080
@deffnx {} BFD_RELOC_PPC_JMP_SLOT
1081
@deffnx {} BFD_RELOC_PPC_RELATIVE
1082
@deffnx {} BFD_RELOC_PPC_LOCAL24PC
1083
@deffnx {} BFD_RELOC_PPC_EMB_NADDR32
1084
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16
1085
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO
1086
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI
1087
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA
1088
@deffnx {} BFD_RELOC_PPC_EMB_SDAI16
1089
@deffnx {} BFD_RELOC_PPC_EMB_SDA2I16
1090
@deffnx {} BFD_RELOC_PPC_EMB_SDA2REL
1091
@deffnx {} BFD_RELOC_PPC_EMB_SDA21
1092
@deffnx {} BFD_RELOC_PPC_EMB_MRKREF
1093
@deffnx {} BFD_RELOC_PPC_EMB_RELSEC16
1094
@deffnx {} BFD_RELOC_PPC_EMB_RELST_LO
1095
@deffnx {} BFD_RELOC_PPC_EMB_RELST_HI
1096
@deffnx {} BFD_RELOC_PPC_EMB_RELST_HA
1097
@deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD
1098
@deffnx {} BFD_RELOC_PPC_EMB_RELSDA
1099
@deffnx {} BFD_RELOC_PPC64_HIGHER
1100
@deffnx {} BFD_RELOC_PPC64_HIGHER_S
1101
@deffnx {} BFD_RELOC_PPC64_HIGHEST
1102
@deffnx {} BFD_RELOC_PPC64_HIGHEST_S
1103
@deffnx {} BFD_RELOC_PPC64_TOC16_LO
1104
@deffnx {} BFD_RELOC_PPC64_TOC16_HI
1105
@deffnx {} BFD_RELOC_PPC64_TOC16_HA
1106
@deffnx {} BFD_RELOC_PPC64_TOC
1107
@deffnx {} BFD_RELOC_PPC64_PLTGOT16
1108
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO
1109
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI
1110
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA
1111
@deffnx {} BFD_RELOC_PPC64_ADDR16_DS
1112
@deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS
1113
@deffnx {} BFD_RELOC_PPC64_GOT16_DS
1114
@deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS
1115
@deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS
1116
@deffnx {} BFD_RELOC_PPC64_SECTOFF_DS
1117
@deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS
1118
@deffnx {} BFD_RELOC_PPC64_TOC16_DS
1119
@deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS
1120
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS
1121
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS
1122
Power(rs6000) and PowerPC relocations.
1123
@end deffn
1124
@deffn {} BFD_RELOC_PPC_TLS
1125
@deffnx {} BFD_RELOC_PPC_TLSGD
1126
@deffnx {} BFD_RELOC_PPC_TLSLD
1127
@deffnx {} BFD_RELOC_PPC_DTPMOD
1128
@deffnx {} BFD_RELOC_PPC_TPREL16
1129
@deffnx {} BFD_RELOC_PPC_TPREL16_LO
1130
@deffnx {} BFD_RELOC_PPC_TPREL16_HI
1131
@deffnx {} BFD_RELOC_PPC_TPREL16_HA
1132
@deffnx {} BFD_RELOC_PPC_TPREL
1133
@deffnx {} BFD_RELOC_PPC_DTPREL16
1134
@deffnx {} BFD_RELOC_PPC_DTPREL16_LO
1135
@deffnx {} BFD_RELOC_PPC_DTPREL16_HI
1136
@deffnx {} BFD_RELOC_PPC_DTPREL16_HA
1137
@deffnx {} BFD_RELOC_PPC_DTPREL
1138
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16
1139
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO
1140
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI
1141
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA
1142
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16
1143
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO
1144
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI
1145
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA
1146
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16
1147
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO
1148
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI
1149
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA
1150
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16
1151
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO
1152
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI
1153
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA
1154
@deffnx {} BFD_RELOC_PPC64_TPREL16_DS
1155
@deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS
1156
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER
1157
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA
1158
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST
1159
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA
1160
@deffnx {} BFD_RELOC_PPC64_DTPREL16_DS
1161
@deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS
1162
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER
1163
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA
1164
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST
1165
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA
1166
PowerPC and PowerPC64 thread-local storage relocations.
1167
@end deffn
1168
@deffn {} BFD_RELOC_I370_D12
1169
IBM 370/390 relocations
1170
@end deffn
1171
@deffn {} BFD_RELOC_CTOR
1172
The type of reloc used to build a constructor table - at the moment
1173
probably a 32 bit wide absolute relocation, but the target can choose.
1174
It generally does map to one of the other relocation types.
1175
@end deffn
1176
@deffn {} BFD_RELOC_ARM_PCREL_BRANCH
1177
ARM 26 bit pc-relative branch.  The lowest two bits must be zero and are
1178
not stored in the instruction.
1179
@end deffn
1180
@deffn {} BFD_RELOC_ARM_PCREL_BLX
1181
ARM 26 bit pc-relative branch.  The lowest bit must be zero and is
1182
not stored in the instruction.  The 2nd lowest bit comes from a 1 bit
1183
field in the instruction.
1184
@end deffn
1185
@deffn {} BFD_RELOC_THUMB_PCREL_BLX
1186
Thumb 22 bit pc-relative branch.  The lowest bit must be zero and is
1187
not stored in the instruction.  The 2nd lowest bit comes from a 1 bit
1188
field in the instruction.
1189
@end deffn
1190
@deffn {} BFD_RELOC_ARM_PCREL_CALL
1191
ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
1192
@end deffn
1193
@deffn {} BFD_RELOC_ARM_PCREL_JUMP
1194
ARM 26-bit pc-relative branch for B or conditional BL instruction.
1195
@end deffn
1196
@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH7
1197
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH9
1198
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12
1199
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH20
1200
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23
1201
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH25
1202
Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
1203
The lowest bit must be zero and is not stored in the instruction.
1204
Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
1205
"nn" one smaller in all cases.  Note further that BRANCH23
1206
corresponds to R_ARM_THM_CALL.
1207
@end deffn
1208
@deffn {} BFD_RELOC_ARM_OFFSET_IMM
1209
12-bit immediate offset, used in ARM-format ldr and str instructions.
1210
@end deffn
1211
@deffn {} BFD_RELOC_ARM_THUMB_OFFSET
1212
5-bit immediate offset, used in Thumb-format ldr and str instructions.
1213
@end deffn
1214
@deffn {} BFD_RELOC_ARM_TARGET1
1215
Pc-relative or absolute relocation depending on target.  Used for
1216
entries in .init_array sections.
1217
@end deffn
1218
@deffn {} BFD_RELOC_ARM_ROSEGREL32
1219
Read-only segment base relative address.
1220
@end deffn
1221
@deffn {} BFD_RELOC_ARM_SBREL32
1222
Data segment base relative address.
1223
@end deffn
1224
@deffn {} BFD_RELOC_ARM_TARGET2
1225
This reloc is used for references to RTTI data from exception handling
1226
tables.  The actual definition depends on the target.  It may be a
1227
pc-relative or some form of GOT-indirect relocation.
1228
@end deffn
1229
@deffn {} BFD_RELOC_ARM_PREL31
1230
31-bit PC relative address.
1231
@end deffn
1232
@deffn {} BFD_RELOC_ARM_MOVW
1233
@deffnx {} BFD_RELOC_ARM_MOVT
1234
@deffnx {} BFD_RELOC_ARM_MOVW_PCREL
1235
@deffnx {} BFD_RELOC_ARM_MOVT_PCREL
1236
@deffnx {} BFD_RELOC_ARM_THUMB_MOVW
1237
@deffnx {} BFD_RELOC_ARM_THUMB_MOVT
1238
@deffnx {} BFD_RELOC_ARM_THUMB_MOVW_PCREL
1239
@deffnx {} BFD_RELOC_ARM_THUMB_MOVT_PCREL
1240
Low and High halfword relocations for MOVW and MOVT instructions.
1241
@end deffn
1242
@deffn {} BFD_RELOC_ARM_JUMP_SLOT
1243
@deffnx {} BFD_RELOC_ARM_GLOB_DAT
1244
@deffnx {} BFD_RELOC_ARM_GOT32
1245
@deffnx {} BFD_RELOC_ARM_PLT32
1246
@deffnx {} BFD_RELOC_ARM_RELATIVE
1247
@deffnx {} BFD_RELOC_ARM_GOTOFF
1248
@deffnx {} BFD_RELOC_ARM_GOTPC
1249
Relocations for setting up GOTs and PLTs for shared libraries.
1250
@end deffn
1251
@deffn {} BFD_RELOC_ARM_TLS_GD32
1252
@deffnx {} BFD_RELOC_ARM_TLS_LDO32
1253
@deffnx {} BFD_RELOC_ARM_TLS_LDM32
1254
@deffnx {} BFD_RELOC_ARM_TLS_DTPOFF32
1255
@deffnx {} BFD_RELOC_ARM_TLS_DTPMOD32
1256
@deffnx {} BFD_RELOC_ARM_TLS_TPOFF32
1257
@deffnx {} BFD_RELOC_ARM_TLS_IE32
1258
@deffnx {} BFD_RELOC_ARM_TLS_LE32
1259
ARM thread-local storage relocations.
1260
@end deffn
1261
@deffn {} BFD_RELOC_ARM_ALU_PC_G0_NC
1262
@deffnx {} BFD_RELOC_ARM_ALU_PC_G0
1263
@deffnx {} BFD_RELOC_ARM_ALU_PC_G1_NC
1264
@deffnx {} BFD_RELOC_ARM_ALU_PC_G1
1265
@deffnx {} BFD_RELOC_ARM_ALU_PC_G2
1266
@deffnx {} BFD_RELOC_ARM_LDR_PC_G0
1267
@deffnx {} BFD_RELOC_ARM_LDR_PC_G1
1268
@deffnx {} BFD_RELOC_ARM_LDR_PC_G2
1269
@deffnx {} BFD_RELOC_ARM_LDRS_PC_G0
1270
@deffnx {} BFD_RELOC_ARM_LDRS_PC_G1
1271
@deffnx {} BFD_RELOC_ARM_LDRS_PC_G2
1272
@deffnx {} BFD_RELOC_ARM_LDC_PC_G0
1273
@deffnx {} BFD_RELOC_ARM_LDC_PC_G1
1274
@deffnx {} BFD_RELOC_ARM_LDC_PC_G2
1275
@deffnx {} BFD_RELOC_ARM_ALU_SB_G0_NC
1276
@deffnx {} BFD_RELOC_ARM_ALU_SB_G0
1277
@deffnx {} BFD_RELOC_ARM_ALU_SB_G1_NC
1278
@deffnx {} BFD_RELOC_ARM_ALU_SB_G1
1279
@deffnx {} BFD_RELOC_ARM_ALU_SB_G2
1280
@deffnx {} BFD_RELOC_ARM_LDR_SB_G0
1281
@deffnx {} BFD_RELOC_ARM_LDR_SB_G1
1282
@deffnx {} BFD_RELOC_ARM_LDR_SB_G2
1283
@deffnx {} BFD_RELOC_ARM_LDRS_SB_G0
1284
@deffnx {} BFD_RELOC_ARM_LDRS_SB_G1
1285
@deffnx {} BFD_RELOC_ARM_LDRS_SB_G2
1286
@deffnx {} BFD_RELOC_ARM_LDC_SB_G0
1287
@deffnx {} BFD_RELOC_ARM_LDC_SB_G1
1288
@deffnx {} BFD_RELOC_ARM_LDC_SB_G2
1289
ARM group relocations.
1290
@end deffn
1291
@deffn {} BFD_RELOC_ARM_V4BX
1292
Annotation of BX instructions.
1293
@end deffn
1294
@deffn {} BFD_RELOC_ARM_IMMEDIATE
1295
@deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE
1296
@deffnx {} BFD_RELOC_ARM_T32_IMMEDIATE
1297
@deffnx {} BFD_RELOC_ARM_T32_ADD_IMM
1298
@deffnx {} BFD_RELOC_ARM_T32_IMM12
1299
@deffnx {} BFD_RELOC_ARM_T32_ADD_PC12
1300
@deffnx {} BFD_RELOC_ARM_SHIFT_IMM
1301
@deffnx {} BFD_RELOC_ARM_SMC
1302
@deffnx {} BFD_RELOC_ARM_SWI
1303
@deffnx {} BFD_RELOC_ARM_MULTI
1304
@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM
1305
@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2
1306
@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM
1307
@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
1308
@deffnx {} BFD_RELOC_ARM_ADR_IMM
1309
@deffnx {} BFD_RELOC_ARM_LDR_IMM
1310
@deffnx {} BFD_RELOC_ARM_LITERAL
1311
@deffnx {} BFD_RELOC_ARM_IN_POOL
1312
@deffnx {} BFD_RELOC_ARM_OFFSET_IMM8
1313
@deffnx {} BFD_RELOC_ARM_T32_OFFSET_U8
1314
@deffnx {} BFD_RELOC_ARM_T32_OFFSET_IMM
1315
@deffnx {} BFD_RELOC_ARM_HWLITERAL
1316
@deffnx {} BFD_RELOC_ARM_THUMB_ADD
1317
@deffnx {} BFD_RELOC_ARM_THUMB_IMM
1318
@deffnx {} BFD_RELOC_ARM_THUMB_SHIFT
1319
These relocs are only used within the ARM assembler.  They are not
1320
(at present) written to any object files.
1321
@end deffn
1322
@deffn {} BFD_RELOC_SH_PCDISP8BY2
1323
@deffnx {} BFD_RELOC_SH_PCDISP12BY2
1324
@deffnx {} BFD_RELOC_SH_IMM3
1325
@deffnx {} BFD_RELOC_SH_IMM3U
1326
@deffnx {} BFD_RELOC_SH_DISP12
1327
@deffnx {} BFD_RELOC_SH_DISP12BY2
1328
@deffnx {} BFD_RELOC_SH_DISP12BY4
1329
@deffnx {} BFD_RELOC_SH_DISP12BY8
1330
@deffnx {} BFD_RELOC_SH_DISP20
1331
@deffnx {} BFD_RELOC_SH_DISP20BY8
1332
@deffnx {} BFD_RELOC_SH_IMM4
1333
@deffnx {} BFD_RELOC_SH_IMM4BY2
1334
@deffnx {} BFD_RELOC_SH_IMM4BY4
1335
@deffnx {} BFD_RELOC_SH_IMM8
1336
@deffnx {} BFD_RELOC_SH_IMM8BY2
1337
@deffnx {} BFD_RELOC_SH_IMM8BY4
1338
@deffnx {} BFD_RELOC_SH_PCRELIMM8BY2
1339
@deffnx {} BFD_RELOC_SH_PCRELIMM8BY4
1340
@deffnx {} BFD_RELOC_SH_SWITCH16
1341
@deffnx {} BFD_RELOC_SH_SWITCH32
1342
@deffnx {} BFD_RELOC_SH_USES
1343
@deffnx {} BFD_RELOC_SH_COUNT
1344
@deffnx {} BFD_RELOC_SH_ALIGN
1345
@deffnx {} BFD_RELOC_SH_CODE
1346
@deffnx {} BFD_RELOC_SH_DATA
1347
@deffnx {} BFD_RELOC_SH_LABEL
1348
@deffnx {} BFD_RELOC_SH_LOOP_START
1349
@deffnx {} BFD_RELOC_SH_LOOP_END
1350
@deffnx {} BFD_RELOC_SH_COPY
1351
@deffnx {} BFD_RELOC_SH_GLOB_DAT
1352
@deffnx {} BFD_RELOC_SH_JMP_SLOT
1353
@deffnx {} BFD_RELOC_SH_RELATIVE
1354
@deffnx {} BFD_RELOC_SH_GOTPC
1355
@deffnx {} BFD_RELOC_SH_GOT_LOW16
1356
@deffnx {} BFD_RELOC_SH_GOT_MEDLOW16
1357
@deffnx {} BFD_RELOC_SH_GOT_MEDHI16
1358
@deffnx {} BFD_RELOC_SH_GOT_HI16
1359
@deffnx {} BFD_RELOC_SH_GOTPLT_LOW16
1360
@deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16
1361
@deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16
1362
@deffnx {} BFD_RELOC_SH_GOTPLT_HI16
1363
@deffnx {} BFD_RELOC_SH_PLT_LOW16
1364
@deffnx {} BFD_RELOC_SH_PLT_MEDLOW16
1365
@deffnx {} BFD_RELOC_SH_PLT_MEDHI16
1366
@deffnx {} BFD_RELOC_SH_PLT_HI16
1367
@deffnx {} BFD_RELOC_SH_GOTOFF_LOW16
1368
@deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16
1369
@deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16
1370
@deffnx {} BFD_RELOC_SH_GOTOFF_HI16
1371
@deffnx {} BFD_RELOC_SH_GOTPC_LOW16
1372
@deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16
1373
@deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16
1374
@deffnx {} BFD_RELOC_SH_GOTPC_HI16
1375
@deffnx {} BFD_RELOC_SH_COPY64
1376
@deffnx {} BFD_RELOC_SH_GLOB_DAT64
1377
@deffnx {} BFD_RELOC_SH_JMP_SLOT64
1378
@deffnx {} BFD_RELOC_SH_RELATIVE64
1379
@deffnx {} BFD_RELOC_SH_GOT10BY4
1380
@deffnx {} BFD_RELOC_SH_GOT10BY8
1381
@deffnx {} BFD_RELOC_SH_GOTPLT10BY4
1382
@deffnx {} BFD_RELOC_SH_GOTPLT10BY8
1383
@deffnx {} BFD_RELOC_SH_GOTPLT32
1384
@deffnx {} BFD_RELOC_SH_SHMEDIA_CODE
1385
@deffnx {} BFD_RELOC_SH_IMMU5
1386
@deffnx {} BFD_RELOC_SH_IMMS6
1387
@deffnx {} BFD_RELOC_SH_IMMS6BY32
1388
@deffnx {} BFD_RELOC_SH_IMMU6
1389
@deffnx {} BFD_RELOC_SH_IMMS10
1390
@deffnx {} BFD_RELOC_SH_IMMS10BY2
1391
@deffnx {} BFD_RELOC_SH_IMMS10BY4
1392
@deffnx {} BFD_RELOC_SH_IMMS10BY8
1393
@deffnx {} BFD_RELOC_SH_IMMS16
1394
@deffnx {} BFD_RELOC_SH_IMMU16
1395
@deffnx {} BFD_RELOC_SH_IMM_LOW16
1396
@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL
1397
@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16
1398
@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL
1399
@deffnx {} BFD_RELOC_SH_IMM_MEDHI16
1400
@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL
1401
@deffnx {} BFD_RELOC_SH_IMM_HI16
1402
@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL
1403
@deffnx {} BFD_RELOC_SH_PT_16
1404
@deffnx {} BFD_RELOC_SH_TLS_GD_32
1405
@deffnx {} BFD_RELOC_SH_TLS_LD_32
1406
@deffnx {} BFD_RELOC_SH_TLS_LDO_32
1407
@deffnx {} BFD_RELOC_SH_TLS_IE_32
1408
@deffnx {} BFD_RELOC_SH_TLS_LE_32
1409
@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32
1410
@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32
1411
@deffnx {} BFD_RELOC_SH_TLS_TPOFF32
1412
Renesas / SuperH SH relocs.  Not all of these appear in object files.
1413
@end deffn
1414
@deffn {} BFD_RELOC_ARC_B22_PCREL
1415
ARC Cores relocs.
1416
ARC 22 bit pc-relative branch.  The lowest two bits must be zero and are
1417
not stored in the instruction.  The high 20 bits are installed in bits 26
1418
through 7 of the instruction.
1419
@end deffn
1420
@deffn {} BFD_RELOC_ARC_B26
1421
ARC 26 bit absolute branch.  The lowest two bits must be zero and are not
1422
stored in the instruction.  The high 24 bits are installed in bits 23
1423
through 0.
1424
@end deffn
1425
@deffn {} BFD_RELOC_BFIN_16_IMM
1426
ADI Blackfin 16 bit immediate absolute reloc.
1427
@end deffn
1428
@deffn {} BFD_RELOC_BFIN_16_HIGH
1429
ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
1430
@end deffn
1431
@deffn {} BFD_RELOC_BFIN_4_PCREL
1432
ADI Blackfin 'a' part of LSETUP.
1433
@end deffn
1434
@deffn {} BFD_RELOC_BFIN_5_PCREL
1435
ADI Blackfin.
1436
@end deffn
1437
@deffn {} BFD_RELOC_BFIN_16_LOW
1438
ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
1439
@end deffn
1440
@deffn {} BFD_RELOC_BFIN_10_PCREL
1441
ADI Blackfin.
1442
@end deffn
1443
@deffn {} BFD_RELOC_BFIN_11_PCREL
1444
ADI Blackfin 'b' part of LSETUP.
1445
@end deffn
1446
@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP
1447
ADI Blackfin.
1448
@end deffn
1449
@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP_S
1450
ADI Blackfin Short jump, pcrel.
1451
@end deffn
1452
@deffn {} BFD_RELOC_BFIN_24_PCREL_CALL_X
1453
ADI Blackfin Call.x not implemented.
1454
@end deffn
1455
@deffn {} BFD_RELOC_BFIN_24_PCREL_JUMP_L
1456
ADI Blackfin Long Jump pcrel.
1457
@end deffn
1458
@deffn {} BFD_RELOC_BFIN_GOT17M4
1459
@deffnx {} BFD_RELOC_BFIN_GOTHI
1460
@deffnx {} BFD_RELOC_BFIN_GOTLO
1461
@deffnx {} BFD_RELOC_BFIN_FUNCDESC
1462
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOT17M4
1463
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTHI
1464
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTLO
1465
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_VALUE
1466
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
1467
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
1468
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
1469
@deffnx {} BFD_RELOC_BFIN_GOTOFF17M4
1470
@deffnx {} BFD_RELOC_BFIN_GOTOFFHI
1471
@deffnx {} BFD_RELOC_BFIN_GOTOFFLO
1472
ADI Blackfin FD-PIC relocations.
1473
@end deffn
1474
@deffn {} BFD_RELOC_BFIN_GOT
1475
ADI Blackfin GOT relocation.
1476
@end deffn
1477
@deffn {} BFD_RELOC_BFIN_PLTPC
1478
ADI Blackfin PLTPC relocation.
1479
@end deffn
1480
@deffn {} BFD_ARELOC_BFIN_PUSH
1481
ADI Blackfin arithmetic relocation.
1482
@end deffn
1483
@deffn {} BFD_ARELOC_BFIN_CONST
1484
ADI Blackfin arithmetic relocation.
1485
@end deffn
1486
@deffn {} BFD_ARELOC_BFIN_ADD
1487
ADI Blackfin arithmetic relocation.
1488
@end deffn
1489
@deffn {} BFD_ARELOC_BFIN_SUB
1490
ADI Blackfin arithmetic relocation.
1491
@end deffn
1492
@deffn {} BFD_ARELOC_BFIN_MULT
1493
ADI Blackfin arithmetic relocation.
1494
@end deffn
1495
@deffn {} BFD_ARELOC_BFIN_DIV
1496
ADI Blackfin arithmetic relocation.
1497
@end deffn
1498
@deffn {} BFD_ARELOC_BFIN_MOD
1499
ADI Blackfin arithmetic relocation.
1500
@end deffn
1501
@deffn {} BFD_ARELOC_BFIN_LSHIFT
1502
ADI Blackfin arithmetic relocation.
1503
@end deffn
1504
@deffn {} BFD_ARELOC_BFIN_RSHIFT
1505
ADI Blackfin arithmetic relocation.
1506
@end deffn
1507
@deffn {} BFD_ARELOC_BFIN_AND
1508
ADI Blackfin arithmetic relocation.
1509
@end deffn
1510
@deffn {} BFD_ARELOC_BFIN_OR
1511
ADI Blackfin arithmetic relocation.
1512
@end deffn
1513
@deffn {} BFD_ARELOC_BFIN_XOR
1514
ADI Blackfin arithmetic relocation.
1515
@end deffn
1516
@deffn {} BFD_ARELOC_BFIN_LAND
1517
ADI Blackfin arithmetic relocation.
1518
@end deffn
1519
@deffn {} BFD_ARELOC_BFIN_LOR
1520
ADI Blackfin arithmetic relocation.
1521
@end deffn
1522
@deffn {} BFD_ARELOC_BFIN_LEN
1523
ADI Blackfin arithmetic relocation.
1524
@end deffn
1525
@deffn {} BFD_ARELOC_BFIN_NEG
1526
ADI Blackfin arithmetic relocation.
1527
@end deffn
1528
@deffn {} BFD_ARELOC_BFIN_COMP
1529
ADI Blackfin arithmetic relocation.
1530
@end deffn
1531
@deffn {} BFD_ARELOC_BFIN_PAGE
1532
ADI Blackfin arithmetic relocation.
1533
@end deffn
1534
@deffn {} BFD_ARELOC_BFIN_HWPAGE
1535
ADI Blackfin arithmetic relocation.
1536
@end deffn
1537
@deffn {} BFD_ARELOC_BFIN_ADDR
1538
ADI Blackfin arithmetic relocation.
1539
@end deffn
1540
@deffn {} BFD_RELOC_D10V_10_PCREL_R
1541
Mitsubishi D10V relocs.
1542
This is a 10-bit reloc with the right 2 bits
1543
assumed to be 0.
1544
@end deffn
1545
@deffn {} BFD_RELOC_D10V_10_PCREL_L
1546
Mitsubishi D10V relocs.
1547
This is a 10-bit reloc with the right 2 bits
1548
assumed to be 0.  This is the same as the previous reloc
1549
except it is in the left container, i.e.,
1550
shifted left 15 bits.
1551
@end deffn
1552
@deffn {} BFD_RELOC_D10V_18
1553
This is an 18-bit reloc with the right 2 bits
1554
assumed to be 0.
1555
@end deffn
1556
@deffn {} BFD_RELOC_D10V_18_PCREL
1557
This is an 18-bit reloc with the right 2 bits
1558
assumed to be 0.
1559
@end deffn
1560
@deffn {} BFD_RELOC_D30V_6
1561
Mitsubishi D30V relocs.
1562
This is a 6-bit absolute reloc.
1563
@end deffn
1564
@deffn {} BFD_RELOC_D30V_9_PCREL
1565
This is a 6-bit pc-relative reloc with
1566
the right 3 bits assumed to be 0.
1567
@end deffn
1568
@deffn {} BFD_RELOC_D30V_9_PCREL_R
1569
This is a 6-bit pc-relative reloc with
1570
the right 3 bits assumed to be 0. Same
1571
as the previous reloc but on the right side
1572
of the container.
1573
@end deffn
1574
@deffn {} BFD_RELOC_D30V_15
1575
This is a 12-bit absolute reloc with the
1576
right 3 bitsassumed to be 0.
1577
@end deffn
1578
@deffn {} BFD_RELOC_D30V_15_PCREL
1579
This is a 12-bit pc-relative reloc with
1580
the right 3 bits assumed to be 0.
1581
@end deffn
1582
@deffn {} BFD_RELOC_D30V_15_PCREL_R
1583
This is a 12-bit pc-relative reloc with
1584
the right 3 bits assumed to be 0. Same
1585
as the previous reloc but on the right side
1586
of the container.
1587
@end deffn
1588
@deffn {} BFD_RELOC_D30V_21
1589
This is an 18-bit absolute reloc with
1590
the right 3 bits assumed to be 0.
1591
@end deffn
1592
@deffn {} BFD_RELOC_D30V_21_PCREL
1593
This is an 18-bit pc-relative reloc with
1594
the right 3 bits assumed to be 0.
1595
@end deffn
1596
@deffn {} BFD_RELOC_D30V_21_PCREL_R
1597
This is an 18-bit pc-relative reloc with
1598
the right 3 bits assumed to be 0. Same
1599
as the previous reloc but on the right side
1600
of the container.
1601
@end deffn
1602
@deffn {} BFD_RELOC_D30V_32
1603
This is a 32-bit absolute reloc.
1604
@end deffn
1605
@deffn {} BFD_RELOC_D30V_32_PCREL
1606
This is a 32-bit pc-relative reloc.
1607
@end deffn
1608
@deffn {} BFD_RELOC_DLX_HI16_S
1609
DLX relocs
1610
@end deffn
1611
@deffn {} BFD_RELOC_DLX_LO16
1612
DLX relocs
1613
@end deffn
1614
@deffn {} BFD_RELOC_DLX_JMP26
1615
DLX relocs
1616
@end deffn
1617
@deffn {} BFD_RELOC_M32C_HI8
1618
@deffnx {} BFD_RELOC_M32C_RL_JUMP
1619
@deffnx {} BFD_RELOC_M32C_RL_1ADDR
1620
@deffnx {} BFD_RELOC_M32C_RL_2ADDR
1621
Renesas M16C/M32C Relocations.
1622
@end deffn
1623
@deffn {} BFD_RELOC_M32R_24
1624
Renesas M32R (formerly Mitsubishi M32R) relocs.
1625
This is a 24 bit absolute address.
1626
@end deffn
1627
@deffn {} BFD_RELOC_M32R_10_PCREL
1628
This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
1629
@end deffn
1630
@deffn {} BFD_RELOC_M32R_18_PCREL
1631
This is an 18-bit reloc with the right 2 bits assumed to be 0.
1632
@end deffn
1633
@deffn {} BFD_RELOC_M32R_26_PCREL
1634
This is a 26-bit reloc with the right 2 bits assumed to be 0.
1635
@end deffn
1636
@deffn {} BFD_RELOC_M32R_HI16_ULO
1637
This is a 16-bit reloc containing the high 16 bits of an address
1638
used when the lower 16 bits are treated as unsigned.
1639
@end deffn
1640
@deffn {} BFD_RELOC_M32R_HI16_SLO
1641
This is a 16-bit reloc containing the high 16 bits of an address
1642
used when the lower 16 bits are treated as signed.
1643
@end deffn
1644
@deffn {} BFD_RELOC_M32R_LO16
1645
This is a 16-bit reloc containing the lower 16 bits of an address.
1646
@end deffn
1647
@deffn {} BFD_RELOC_M32R_SDA16
1648
This is a 16-bit reloc containing the small data area offset for use in
1649
add3, load, and store instructions.
1650
@end deffn
1651
@deffn {} BFD_RELOC_M32R_GOT24
1652
@deffnx {} BFD_RELOC_M32R_26_PLTREL
1653
@deffnx {} BFD_RELOC_M32R_COPY
1654
@deffnx {} BFD_RELOC_M32R_GLOB_DAT
1655
@deffnx {} BFD_RELOC_M32R_JMP_SLOT
1656
@deffnx {} BFD_RELOC_M32R_RELATIVE
1657
@deffnx {} BFD_RELOC_M32R_GOTOFF
1658
@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_ULO
1659
@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_SLO
1660
@deffnx {} BFD_RELOC_M32R_GOTOFF_LO
1661
@deffnx {} BFD_RELOC_M32R_GOTPC24
1662
@deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO
1663
@deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO
1664
@deffnx {} BFD_RELOC_M32R_GOT16_LO
1665
@deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO
1666
@deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO
1667
@deffnx {} BFD_RELOC_M32R_GOTPC_LO
1668
For PIC.
1669
@end deffn
1670
@deffn {} BFD_RELOC_V850_9_PCREL
1671
This is a 9-bit reloc
1672
@end deffn
1673
@deffn {} BFD_RELOC_V850_22_PCREL
1674
This is a 22-bit reloc
1675
@end deffn
1676
@deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET
1677
This is a 16 bit offset from the short data area pointer.
1678
@end deffn
1679
@deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET
1680
This is a 16 bit offset (of which only 15 bits are used) from the
1681
short data area pointer.
1682
@end deffn
1683
@deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET
1684
This is a 16 bit offset from the zero data area pointer.
1685
@end deffn
1686
@deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET
1687
This is a 16 bit offset (of which only 15 bits are used) from the
1688
zero data area pointer.
1689
@end deffn
1690
@deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET
1691
This is an 8 bit offset (of which only 6 bits are used) from the
1692
tiny data area pointer.
1693
@end deffn
1694
@deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET
1695
This is an 8bit offset (of which only 7 bits are used) from the tiny
1696
data area pointer.
1697
@end deffn
1698
@deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET
1699
This is a 7 bit offset from the tiny data area pointer.
1700
@end deffn
1701
@deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET
1702
This is a 16 bit offset from the tiny data area pointer.
1703
@end deffn
1704
@deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET
1705
This is a 5 bit offset (of which only 4 bits are used) from the tiny
1706
data area pointer.
1707
@end deffn
1708
@deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET
1709
This is a 4 bit offset from the tiny data area pointer.
1710
@end deffn
1711
@deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
1712
This is a 16 bit offset from the short data area pointer, with the
1713
bits placed non-contiguously in the instruction.
1714
@end deffn
1715
@deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
1716
This is a 16 bit offset from the zero data area pointer, with the
1717
bits placed non-contiguously in the instruction.
1718
@end deffn
1719
@deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET
1720
This is a 6 bit offset from the call table base pointer.
1721
@end deffn
1722
@deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET
1723
This is a 16 bit offset from the call table base pointer.
1724
@end deffn
1725
@deffn {} BFD_RELOC_V850_LONGCALL
1726
Used for relaxing indirect function calls.
1727
@end deffn
1728
@deffn {} BFD_RELOC_V850_LONGJUMP
1729
Used for relaxing indirect jumps.
1730
@end deffn
1731
@deffn {} BFD_RELOC_V850_ALIGN
1732
Used to maintain alignment whilst relaxing.
1733
@end deffn
1734
@deffn {} BFD_RELOC_V850_LO16_SPLIT_OFFSET
1735
This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
1736
instructions.
1737
@end deffn
1738
@deffn {} BFD_RELOC_MN10300_32_PCREL
1739
This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
1740
instruction.
1741
@end deffn
1742
@deffn {} BFD_RELOC_MN10300_16_PCREL
1743
This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
1744
instruction.
1745
@end deffn
1746
@deffn {} BFD_RELOC_TIC30_LDP
1747
This is a 8bit DP reloc for the tms320c30, where the most
1748
significant 8 bits of a 24 bit word are placed into the least
1749
significant 8 bits of the opcode.
1750
@end deffn
1751
@deffn {} BFD_RELOC_TIC54X_PARTLS7
1752
This is a 7bit reloc for the tms320c54x, where the least
1753
significant 7 bits of a 16 bit word are placed into the least
1754
significant 7 bits of the opcode.
1755
@end deffn
1756
@deffn {} BFD_RELOC_TIC54X_PARTMS9
1757
This is a 9bit DP reloc for the tms320c54x, where the most
1758
significant 9 bits of a 16 bit word are placed into the least
1759
significant 9 bits of the opcode.
1760
@end deffn
1761
@deffn {} BFD_RELOC_TIC54X_23
1762
This is an extended address 23-bit reloc for the tms320c54x.
1763
@end deffn
1764
@deffn {} BFD_RELOC_TIC54X_16_OF_23
1765
This is a 16-bit reloc for the tms320c54x, where the least
1766
significant 16 bits of a 23-bit extended address are placed into
1767
the opcode.
1768
@end deffn
1769
@deffn {} BFD_RELOC_TIC54X_MS7_OF_23
1770
This is a reloc for the tms320c54x, where the most
1771
significant 7 bits of a 23-bit extended address are placed into
1772
the opcode.
1773
@end deffn
1774
@deffn {} BFD_RELOC_FR30_48
1775
This is a 48 bit reloc for the FR30 that stores 32 bits.
1776
@end deffn
1777
@deffn {} BFD_RELOC_FR30_20
1778
This is a 32 bit reloc for the FR30 that stores 20 bits split up into
1779
two sections.
1780
@end deffn
1781
@deffn {} BFD_RELOC_FR30_6_IN_4
1782
This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
1783
4 bits.
1784
@end deffn
1785
@deffn {} BFD_RELOC_FR30_8_IN_8
1786
This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
1787
into 8 bits.
1788
@end deffn
1789
@deffn {} BFD_RELOC_FR30_9_IN_8
1790
This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
1791
into 8 bits.
1792
@end deffn
1793
@deffn {} BFD_RELOC_FR30_10_IN_8
1794
This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
1795
into 8 bits.
1796
@end deffn
1797
@deffn {} BFD_RELOC_FR30_9_PCREL
1798
This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
1799
short offset into 8 bits.
1800
@end deffn
1801
@deffn {} BFD_RELOC_FR30_12_PCREL
1802
This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
1803
short offset into 11 bits.
1804
@end deffn
1805
@deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4
1806
@deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2
1807
@deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2
1808
@deffnx {} BFD_RELOC_MCORE_PCREL_32
1809
@deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
1810
@deffnx {} BFD_RELOC_MCORE_RVA
1811
Motorola Mcore relocations.
1812
@end deffn
1813
@deffn {} BFD_RELOC_MEP_8
1814
@deffnx {} BFD_RELOC_MEP_16
1815
@deffnx {} BFD_RELOC_MEP_32
1816
@deffnx {} BFD_RELOC_MEP_PCREL8A2
1817
@deffnx {} BFD_RELOC_MEP_PCREL12A2
1818
@deffnx {} BFD_RELOC_MEP_PCREL17A2
1819
@deffnx {} BFD_RELOC_MEP_PCREL24A2
1820
@deffnx {} BFD_RELOC_MEP_PCABS24A2
1821
@deffnx {} BFD_RELOC_MEP_LOW16
1822
@deffnx {} BFD_RELOC_MEP_HI16U
1823
@deffnx {} BFD_RELOC_MEP_HI16S
1824
@deffnx {} BFD_RELOC_MEP_GPREL
1825
@deffnx {} BFD_RELOC_MEP_TPREL
1826
@deffnx {} BFD_RELOC_MEP_TPREL7
1827
@deffnx {} BFD_RELOC_MEP_TPREL7A2
1828
@deffnx {} BFD_RELOC_MEP_TPREL7A4
1829
@deffnx {} BFD_RELOC_MEP_UIMM24
1830
@deffnx {} BFD_RELOC_MEP_ADDR24A4
1831
@deffnx {} BFD_RELOC_MEP_GNU_VTINHERIT
1832
@deffnx {} BFD_RELOC_MEP_GNU_VTENTRY
1833
Toshiba Media Processor Relocations.
1834
@end deffn
1835
@deffn {} BFD_RELOC_MMIX_GETA
1836
@deffnx {} BFD_RELOC_MMIX_GETA_1
1837
@deffnx {} BFD_RELOC_MMIX_GETA_2
1838
@deffnx {} BFD_RELOC_MMIX_GETA_3
1839
These are relocations for the GETA instruction.
1840
@end deffn
1841
@deffn {} BFD_RELOC_MMIX_CBRANCH
1842
@deffnx {} BFD_RELOC_MMIX_CBRANCH_J
1843
@deffnx {} BFD_RELOC_MMIX_CBRANCH_1
1844
@deffnx {} BFD_RELOC_MMIX_CBRANCH_2
1845
@deffnx {} BFD_RELOC_MMIX_CBRANCH_3
1846
These are relocations for a conditional branch instruction.
1847
@end deffn
1848
@deffn {} BFD_RELOC_MMIX_PUSHJ
1849
@deffnx {} BFD_RELOC_MMIX_PUSHJ_1
1850
@deffnx {} BFD_RELOC_MMIX_PUSHJ_2
1851
@deffnx {} BFD_RELOC_MMIX_PUSHJ_3
1852
@deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE
1853
These are relocations for the PUSHJ instruction.
1854
@end deffn
1855
@deffn {} BFD_RELOC_MMIX_JMP
1856
@deffnx {} BFD_RELOC_MMIX_JMP_1
1857
@deffnx {} BFD_RELOC_MMIX_JMP_2
1858
@deffnx {} BFD_RELOC_MMIX_JMP_3
1859
These are relocations for the JMP instruction.
1860
@end deffn
1861
@deffn {} BFD_RELOC_MMIX_ADDR19
1862
This is a relocation for a relative address as in a GETA instruction or
1863
a branch.
1864
@end deffn
1865
@deffn {} BFD_RELOC_MMIX_ADDR27
1866
This is a relocation for a relative address as in a JMP instruction.
1867
@end deffn
1868
@deffn {} BFD_RELOC_MMIX_REG_OR_BYTE
1869
This is a relocation for an instruction field that may be a general
1870
register or a value 0..255.
1871
@end deffn
1872
@deffn {} BFD_RELOC_MMIX_REG
1873
This is a relocation for an instruction field that may be a general
1874
register.
1875
@end deffn
1876
@deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET
1877
This is a relocation for two instruction fields holding a register and
1878
an offset, the equivalent of the relocation.
1879
@end deffn
1880
@deffn {} BFD_RELOC_MMIX_LOCAL
1881
This relocation is an assertion that the expression is not allocated as
1882
a global register.  It does not modify contents.
1883
@end deffn
1884
@deffn {} BFD_RELOC_AVR_7_PCREL
1885
This is a 16 bit reloc for the AVR that stores 8 bit pc relative
1886
short offset into 7 bits.
1887
@end deffn
1888
@deffn {} BFD_RELOC_AVR_13_PCREL
1889
This is a 16 bit reloc for the AVR that stores 13 bit pc relative
1890
short offset into 12 bits.
1891
@end deffn
1892
@deffn {} BFD_RELOC_AVR_16_PM
1893
This is a 16 bit reloc for the AVR that stores 17 bit value (usually
1894
program memory address) into 16 bits.
1895
@end deffn
1896
@deffn {} BFD_RELOC_AVR_LO8_LDI
1897
This is a 16 bit reloc for the AVR that stores 8 bit value (usually
1898
data memory address) into 8 bit immediate value of LDI insn.
1899
@end deffn
1900
@deffn {} BFD_RELOC_AVR_HI8_LDI
1901
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1902
of data memory address) into 8 bit immediate value of LDI insn.
1903
@end deffn
1904
@deffn {} BFD_RELOC_AVR_HH8_LDI
1905
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1906
of program memory address) into 8 bit immediate value of LDI insn.
1907
@end deffn
1908
@deffn {} BFD_RELOC_AVR_MS8_LDI
1909
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1910
of 32 bit value) into 8 bit immediate value of LDI insn.
1911
@end deffn
1912
@deffn {} BFD_RELOC_AVR_LO8_LDI_NEG
1913
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1914
(usually data memory address) into 8 bit immediate value of SUBI insn.
1915
@end deffn
1916
@deffn {} BFD_RELOC_AVR_HI8_LDI_NEG
1917
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1918
(high 8 bit of data memory address) into 8 bit immediate value of
1919
SUBI insn.
1920
@end deffn
1921
@deffn {} BFD_RELOC_AVR_HH8_LDI_NEG
1922
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1923
(most high 8 bit of program memory address) into 8 bit immediate value
1924
of LDI or SUBI insn.
1925
@end deffn
1926
@deffn {} BFD_RELOC_AVR_MS8_LDI_NEG
1927
This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
1928
of 32 bit value) into 8 bit immediate value of LDI insn.
1929
@end deffn
1930
@deffn {} BFD_RELOC_AVR_LO8_LDI_PM
1931
This is a 16 bit reloc for the AVR that stores 8 bit value (usually
1932
command address) into 8 bit immediate value of LDI insn.
1933
@end deffn
1934
@deffn {} BFD_RELOC_AVR_LO8_LDI_GS
1935
This is a 16 bit reloc for the AVR that stores 8 bit value
1936
(command address) into 8 bit immediate value of LDI insn. If the address
1937
is beyond the 128k boundary, the linker inserts a jump stub for this reloc
1938
in the lower 128k.
1939
@end deffn
1940
@deffn {} BFD_RELOC_AVR_HI8_LDI_PM
1941
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1942
of command address) into 8 bit immediate value of LDI insn.
1943
@end deffn
1944
@deffn {} BFD_RELOC_AVR_HI8_LDI_GS
1945
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1946
of command address) into 8 bit immediate value of LDI insn.  If the address
1947
is beyond the 128k boundary, the linker inserts a jump stub for this reloc
1948
below 128k.
1949
@end deffn
1950
@deffn {} BFD_RELOC_AVR_HH8_LDI_PM
1951
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1952
of command address) into 8 bit immediate value of LDI insn.
1953
@end deffn
1954
@deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG
1955
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1956
(usually command address) into 8 bit immediate value of SUBI insn.
1957
@end deffn
1958
@deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG
1959
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1960
(high 8 bit of 16 bit command address) into 8 bit immediate value
1961
of SUBI insn.
1962
@end deffn
1963
@deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG
1964
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1965
(high 6 bit of 22 bit command address) into 8 bit immediate
1966
value of SUBI insn.
1967
@end deffn
1968
@deffn {} BFD_RELOC_AVR_CALL
1969
This is a 32 bit reloc for the AVR that stores 23 bit value
1970
into 22 bits.
1971
@end deffn
1972
@deffn {} BFD_RELOC_AVR_LDI
1973
This is a 16 bit reloc for the AVR that stores all needed bits
1974
for absolute addressing with ldi with overflow check to linktime
1975
@end deffn
1976
@deffn {} BFD_RELOC_AVR_6
1977
This is a 6 bit reloc for the AVR that stores offset for ldd/std
1978
instructions
1979
@end deffn
1980
@deffn {} BFD_RELOC_AVR_6_ADIW
1981
This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
1982
instructions
1983
@end deffn
1984
@deffn {} BFD_RELOC_RX_NEG8
1985
@deffnx {} BFD_RELOC_RX_NEG16
1986
@deffnx {} BFD_RELOC_RX_NEG24
1987
@deffnx {} BFD_RELOC_RX_NEG32
1988
@deffnx {} BFD_RELOC_RX_16_OP
1989
@deffnx {} BFD_RELOC_RX_24_OP
1990
@deffnx {} BFD_RELOC_RX_32_OP
1991
@deffnx {} BFD_RELOC_RX_8U
1992
@deffnx {} BFD_RELOC_RX_16U
1993
@deffnx {} BFD_RELOC_RX_24U
1994
@deffnx {} BFD_RELOC_RX_DIR3U_PCREL
1995
@deffnx {} BFD_RELOC_RX_DIFF
1996
@deffnx {} BFD_RELOC_RX_GPRELB
1997
@deffnx {} BFD_RELOC_RX_GPRELW
1998
@deffnx {} BFD_RELOC_RX_GPRELL
1999
@deffnx {} BFD_RELOC_RX_SYM
2000
@deffnx {} BFD_RELOC_RX_OP_SUBTRACT
2001
@deffnx {} BFD_RELOC_RX_ABS8
2002
@deffnx {} BFD_RELOC_RX_ABS16
2003
@deffnx {} BFD_RELOC_RX_ABS32
2004
@deffnx {} BFD_RELOC_RX_ABS16U
2005
@deffnx {} BFD_RELOC_RX_ABS16UW
2006
@deffnx {} BFD_RELOC_RX_ABS16UL
2007
@deffnx {} BFD_RELOC_RX_RELAX
2008
Renesas RX Relocations.
2009
@end deffn
2010
@deffn {} BFD_RELOC_390_12
2011
Direct 12 bit.
2012
@end deffn
2013
@deffn {} BFD_RELOC_390_GOT12
2014
12 bit GOT offset.
2015
@end deffn
2016
@deffn {} BFD_RELOC_390_PLT32
2017
32 bit PC relative PLT address.
2018
@end deffn
2019
@deffn {} BFD_RELOC_390_COPY
2020
Copy symbol at runtime.
2021
@end deffn
2022
@deffn {} BFD_RELOC_390_GLOB_DAT
2023
Create GOT entry.
2024
@end deffn
2025
@deffn {} BFD_RELOC_390_JMP_SLOT
2026
Create PLT entry.
2027
@end deffn
2028
@deffn {} BFD_RELOC_390_RELATIVE
2029
Adjust by program base.
2030
@end deffn
2031
@deffn {} BFD_RELOC_390_GOTPC
2032
32 bit PC relative offset to GOT.
2033
@end deffn
2034
@deffn {} BFD_RELOC_390_GOT16
2035
16 bit GOT offset.
2036
@end deffn
2037
@deffn {} BFD_RELOC_390_PC16DBL
2038
PC relative 16 bit shifted by 1.
2039
@end deffn
2040
@deffn {} BFD_RELOC_390_PLT16DBL
2041
16 bit PC rel. PLT shifted by 1.
2042
@end deffn
2043
@deffn {} BFD_RELOC_390_PC32DBL
2044
PC relative 32 bit shifted by 1.
2045
@end deffn
2046
@deffn {} BFD_RELOC_390_PLT32DBL
2047
32 bit PC rel. PLT shifted by 1.
2048
@end deffn
2049
@deffn {} BFD_RELOC_390_GOTPCDBL
2050
32 bit PC rel. GOT shifted by 1.
2051
@end deffn
2052
@deffn {} BFD_RELOC_390_GOT64
2053
64 bit GOT offset.
2054
@end deffn
2055
@deffn {} BFD_RELOC_390_PLT64
2056
64 bit PC relative PLT address.
2057
@end deffn
2058
@deffn {} BFD_RELOC_390_GOTENT
2059
32 bit rel. offset to GOT entry.
2060
@end deffn
2061
@deffn {} BFD_RELOC_390_GOTOFF64
2062
64 bit offset to GOT.
2063
@end deffn
2064
@deffn {} BFD_RELOC_390_GOTPLT12
2065
12-bit offset to symbol-entry within GOT, with PLT handling.
2066
@end deffn
2067
@deffn {} BFD_RELOC_390_GOTPLT16
2068
16-bit offset to symbol-entry within GOT, with PLT handling.
2069
@end deffn
2070
@deffn {} BFD_RELOC_390_GOTPLT32
2071
32-bit offset to symbol-entry within GOT, with PLT handling.
2072
@end deffn
2073
@deffn {} BFD_RELOC_390_GOTPLT64
2074
64-bit offset to symbol-entry within GOT, with PLT handling.
2075
@end deffn
2076
@deffn {} BFD_RELOC_390_GOTPLTENT
2077
32-bit rel. offset to symbol-entry within GOT, with PLT handling.
2078
@end deffn
2079
@deffn {} BFD_RELOC_390_PLTOFF16
2080
16-bit rel. offset from the GOT to a PLT entry.
2081
@end deffn
2082
@deffn {} BFD_RELOC_390_PLTOFF32
2083
32-bit rel. offset from the GOT to a PLT entry.
2084
@end deffn
2085
@deffn {} BFD_RELOC_390_PLTOFF64
2086
64-bit rel. offset from the GOT to a PLT entry.
2087
@end deffn
2088
@deffn {} BFD_RELOC_390_TLS_LOAD
2089
@deffnx {} BFD_RELOC_390_TLS_GDCALL
2090
@deffnx {} BFD_RELOC_390_TLS_LDCALL
2091
@deffnx {} BFD_RELOC_390_TLS_GD32
2092
@deffnx {} BFD_RELOC_390_TLS_GD64
2093
@deffnx {} BFD_RELOC_390_TLS_GOTIE12
2094
@deffnx {} BFD_RELOC_390_TLS_GOTIE32
2095
@deffnx {} BFD_RELOC_390_TLS_GOTIE64
2096
@deffnx {} BFD_RELOC_390_TLS_LDM32
2097
@deffnx {} BFD_RELOC_390_TLS_LDM64
2098
@deffnx {} BFD_RELOC_390_TLS_IE32
2099
@deffnx {} BFD_RELOC_390_TLS_IE64
2100
@deffnx {} BFD_RELOC_390_TLS_IEENT
2101
@deffnx {} BFD_RELOC_390_TLS_LE32
2102
@deffnx {} BFD_RELOC_390_TLS_LE64
2103
@deffnx {} BFD_RELOC_390_TLS_LDO32
2104
@deffnx {} BFD_RELOC_390_TLS_LDO64
2105
@deffnx {} BFD_RELOC_390_TLS_DTPMOD
2106
@deffnx {} BFD_RELOC_390_TLS_DTPOFF
2107
@deffnx {} BFD_RELOC_390_TLS_TPOFF
2108
s390 tls relocations.
2109
@end deffn
2110
@deffn {} BFD_RELOC_390_20
2111
@deffnx {} BFD_RELOC_390_GOT20
2112
@deffnx {} BFD_RELOC_390_GOTPLT20
2113
@deffnx {} BFD_RELOC_390_TLS_GOTIE20
2114
Long displacement extension.
2115
@end deffn
2116
@deffn {} BFD_RELOC_SCORE_GPREL15
2117
Score relocations
2118
Low 16 bit for load/store
2119
@end deffn
2120
@deffn {} BFD_RELOC_SCORE_DUMMY2
2121
@deffnx {} BFD_RELOC_SCORE_JMP
2122
This is a 24-bit reloc with the right 1 bit assumed to be 0
2123
@end deffn
2124
@deffn {} BFD_RELOC_SCORE_BRANCH
2125
This is a 19-bit reloc with the right 1 bit assumed to be 0
2126
@end deffn
2127
@deffn {} BFD_RELOC_SCORE_IMM30
2128
This is a 32-bit reloc for 48-bit instructions.
2129
@end deffn
2130
@deffn {} BFD_RELOC_SCORE_IMM32
2131
This is a 32-bit reloc for 48-bit instructions.
2132
@end deffn
2133
@deffn {} BFD_RELOC_SCORE16_JMP
2134
This is a 11-bit reloc with the right 1 bit assumed to be 0
2135
@end deffn
2136
@deffn {} BFD_RELOC_SCORE16_BRANCH
2137
This is a 8-bit reloc with the right 1 bit assumed to be 0
2138
@end deffn
2139
@deffn {} BFD_RELOC_SCORE_BCMP
2140
This is a 9-bit reloc with the right 1 bit assumed to be 0
2141
@end deffn
2142
@deffn {} BFD_RELOC_SCORE_GOT15
2143
@deffnx {} BFD_RELOC_SCORE_GOT_LO16
2144
@deffnx {} BFD_RELOC_SCORE_CALL15
2145
@deffnx {} BFD_RELOC_SCORE_DUMMY_HI16
2146
Undocumented Score relocs
2147
@end deffn
2148
@deffn {} BFD_RELOC_IP2K_FR9
2149
Scenix IP2K - 9-bit register number / data address
2150
@end deffn
2151
@deffn {} BFD_RELOC_IP2K_BANK
2152
Scenix IP2K - 4-bit register/data bank number
2153
@end deffn
2154
@deffn {} BFD_RELOC_IP2K_ADDR16CJP
2155
Scenix IP2K - low 13 bits of instruction word address
2156
@end deffn
2157
@deffn {} BFD_RELOC_IP2K_PAGE3
2158
Scenix IP2K - high 3 bits of instruction word address
2159
@end deffn
2160
@deffn {} BFD_RELOC_IP2K_LO8DATA
2161
@deffnx {} BFD_RELOC_IP2K_HI8DATA
2162
@deffnx {} BFD_RELOC_IP2K_EX8DATA
2163
Scenix IP2K - ext/low/high 8 bits of data address
2164
@end deffn
2165
@deffn {} BFD_RELOC_IP2K_LO8INSN
2166
@deffnx {} BFD_RELOC_IP2K_HI8INSN
2167
Scenix IP2K - low/high 8 bits of instruction word address
2168
@end deffn
2169
@deffn {} BFD_RELOC_IP2K_PC_SKIP
2170
Scenix IP2K - even/odd PC modifier to modify snb pcl.0
2171
@end deffn
2172
@deffn {} BFD_RELOC_IP2K_TEXT
2173
Scenix IP2K - 16 bit word address in text section.
2174
@end deffn
2175
@deffn {} BFD_RELOC_IP2K_FR_OFFSET
2176
Scenix IP2K - 7-bit sp or dp offset
2177
@end deffn
2178
@deffn {} BFD_RELOC_VPE4KMATH_DATA
2179
@deffnx {} BFD_RELOC_VPE4KMATH_INSN
2180
Scenix VPE4K coprocessor - data/insn-space addressing
2181
@end deffn
2182
@deffn {} BFD_RELOC_VTABLE_INHERIT
2183
@deffnx {} BFD_RELOC_VTABLE_ENTRY
2184
These two relocations are used by the linker to determine which of
2185
the entries in a C++ virtual function table are actually used.  When
2186
the --gc-sections option is given, the linker will zero out the entries
2187
that are not used, so that the code for those functions need not be
2188
included in the output.
2189
 
2190
VTABLE_INHERIT is a zero-space relocation used to describe to the
2191
linker the inheritance tree of a C++ virtual function table.  The
2192
relocation's symbol should be the parent class' vtable, and the
2193
relocation should be located at the child vtable.
2194
 
2195
VTABLE_ENTRY is a zero-space relocation that describes the use of a
2196
virtual function table entry.  The reloc's symbol should refer to the
2197
table of the class mentioned in the code.  Off of that base, an offset
2198
describes the entry that is being used.  For Rela hosts, this offset
2199
is stored in the reloc's addend.  For Rel hosts, we are forced to put
2200
this offset in the reloc's section offset.
2201
@end deffn
2202
@deffn {} BFD_RELOC_IA64_IMM14
2203
@deffnx {} BFD_RELOC_IA64_IMM22
2204
@deffnx {} BFD_RELOC_IA64_IMM64
2205
@deffnx {} BFD_RELOC_IA64_DIR32MSB
2206
@deffnx {} BFD_RELOC_IA64_DIR32LSB
2207
@deffnx {} BFD_RELOC_IA64_DIR64MSB
2208
@deffnx {} BFD_RELOC_IA64_DIR64LSB
2209
@deffnx {} BFD_RELOC_IA64_GPREL22
2210
@deffnx {} BFD_RELOC_IA64_GPREL64I
2211
@deffnx {} BFD_RELOC_IA64_GPREL32MSB
2212
@deffnx {} BFD_RELOC_IA64_GPREL32LSB
2213
@deffnx {} BFD_RELOC_IA64_GPREL64MSB
2214
@deffnx {} BFD_RELOC_IA64_GPREL64LSB
2215
@deffnx {} BFD_RELOC_IA64_LTOFF22
2216
@deffnx {} BFD_RELOC_IA64_LTOFF64I
2217
@deffnx {} BFD_RELOC_IA64_PLTOFF22
2218
@deffnx {} BFD_RELOC_IA64_PLTOFF64I
2219
@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB
2220
@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB
2221
@deffnx {} BFD_RELOC_IA64_FPTR64I
2222
@deffnx {} BFD_RELOC_IA64_FPTR32MSB
2223
@deffnx {} BFD_RELOC_IA64_FPTR32LSB
2224
@deffnx {} BFD_RELOC_IA64_FPTR64MSB
2225
@deffnx {} BFD_RELOC_IA64_FPTR64LSB
2226
@deffnx {} BFD_RELOC_IA64_PCREL21B
2227
@deffnx {} BFD_RELOC_IA64_PCREL21BI
2228
@deffnx {} BFD_RELOC_IA64_PCREL21M
2229
@deffnx {} BFD_RELOC_IA64_PCREL21F
2230
@deffnx {} BFD_RELOC_IA64_PCREL22
2231
@deffnx {} BFD_RELOC_IA64_PCREL60B
2232
@deffnx {} BFD_RELOC_IA64_PCREL64I
2233
@deffnx {} BFD_RELOC_IA64_PCREL32MSB
2234
@deffnx {} BFD_RELOC_IA64_PCREL32LSB
2235
@deffnx {} BFD_RELOC_IA64_PCREL64MSB
2236
@deffnx {} BFD_RELOC_IA64_PCREL64LSB
2237
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22
2238
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I
2239
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB
2240
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB
2241
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB
2242
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB
2243
@deffnx {} BFD_RELOC_IA64_SEGREL32MSB
2244
@deffnx {} BFD_RELOC_IA64_SEGREL32LSB
2245
@deffnx {} BFD_RELOC_IA64_SEGREL64MSB
2246
@deffnx {} BFD_RELOC_IA64_SEGREL64LSB
2247
@deffnx {} BFD_RELOC_IA64_SECREL32MSB
2248
@deffnx {} BFD_RELOC_IA64_SECREL32LSB
2249
@deffnx {} BFD_RELOC_IA64_SECREL64MSB
2250
@deffnx {} BFD_RELOC_IA64_SECREL64LSB
2251
@deffnx {} BFD_RELOC_IA64_REL32MSB
2252
@deffnx {} BFD_RELOC_IA64_REL32LSB
2253
@deffnx {} BFD_RELOC_IA64_REL64MSB
2254
@deffnx {} BFD_RELOC_IA64_REL64LSB
2255
@deffnx {} BFD_RELOC_IA64_LTV32MSB
2256
@deffnx {} BFD_RELOC_IA64_LTV32LSB
2257
@deffnx {} BFD_RELOC_IA64_LTV64MSB
2258
@deffnx {} BFD_RELOC_IA64_LTV64LSB
2259
@deffnx {} BFD_RELOC_IA64_IPLTMSB
2260
@deffnx {} BFD_RELOC_IA64_IPLTLSB
2261
@deffnx {} BFD_RELOC_IA64_COPY
2262
@deffnx {} BFD_RELOC_IA64_LTOFF22X
2263
@deffnx {} BFD_RELOC_IA64_LDXMOV
2264
@deffnx {} BFD_RELOC_IA64_TPREL14
2265
@deffnx {} BFD_RELOC_IA64_TPREL22
2266
@deffnx {} BFD_RELOC_IA64_TPREL64I
2267
@deffnx {} BFD_RELOC_IA64_TPREL64MSB
2268
@deffnx {} BFD_RELOC_IA64_TPREL64LSB
2269
@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22
2270
@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB
2271
@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB
2272
@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22
2273
@deffnx {} BFD_RELOC_IA64_DTPREL14
2274
@deffnx {} BFD_RELOC_IA64_DTPREL22
2275
@deffnx {} BFD_RELOC_IA64_DTPREL64I
2276
@deffnx {} BFD_RELOC_IA64_DTPREL32MSB
2277
@deffnx {} BFD_RELOC_IA64_DTPREL32LSB
2278
@deffnx {} BFD_RELOC_IA64_DTPREL64MSB
2279
@deffnx {} BFD_RELOC_IA64_DTPREL64LSB
2280
@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22
2281
Intel IA64 Relocations.
2282
@end deffn
2283
@deffn {} BFD_RELOC_M68HC11_HI8
2284
Motorola 68HC11 reloc.
2285
This is the 8 bit high part of an absolute address.
2286
@end deffn
2287
@deffn {} BFD_RELOC_M68HC11_LO8
2288
Motorola 68HC11 reloc.
2289
This is the 8 bit low part of an absolute address.
2290
@end deffn
2291
@deffn {} BFD_RELOC_M68HC11_3B
2292
Motorola 68HC11 reloc.
2293
This is the 3 bit of a value.
2294
@end deffn
2295
@deffn {} BFD_RELOC_M68HC11_RL_JUMP
2296
Motorola 68HC11 reloc.
2297
This reloc marks the beginning of a jump/call instruction.
2298
It is used for linker relaxation to correctly identify beginning
2299
of instruction and change some branches to use PC-relative
2300
addressing mode.
2301
@end deffn
2302
@deffn {} BFD_RELOC_M68HC11_RL_GROUP
2303
Motorola 68HC11 reloc.
2304
This reloc marks a group of several instructions that gcc generates
2305
and for which the linker relaxation pass can modify and/or remove
2306
some of them.
2307
@end deffn
2308
@deffn {} BFD_RELOC_M68HC11_LO16
2309
Motorola 68HC11 reloc.
2310
This is the 16-bit lower part of an address.  It is used for 'call'
2311
instruction to specify the symbol address without any special
2312
transformation (due to memory bank window).
2313
@end deffn
2314
@deffn {} BFD_RELOC_M68HC11_PAGE
2315
Motorola 68HC11 reloc.
2316
This is a 8-bit reloc that specifies the page number of an address.
2317
It is used by 'call' instruction to specify the page number of
2318
the symbol.
2319
@end deffn
2320
@deffn {} BFD_RELOC_M68HC11_24
2321
Motorola 68HC11 reloc.
2322
This is a 24-bit reloc that represents the address with a 16-bit
2323
value and a 8-bit page number.  The symbol address is transformed
2324
to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
2325
@end deffn
2326
@deffn {} BFD_RELOC_M68HC12_5B
2327
Motorola 68HC12 reloc.
2328
This is the 5 bits of a value.
2329
@end deffn
2330
@deffn {} BFD_RELOC_16C_NUM08
2331
@deffnx {} BFD_RELOC_16C_NUM08_C
2332
@deffnx {} BFD_RELOC_16C_NUM16
2333
@deffnx {} BFD_RELOC_16C_NUM16_C
2334
@deffnx {} BFD_RELOC_16C_NUM32
2335
@deffnx {} BFD_RELOC_16C_NUM32_C
2336
@deffnx {} BFD_RELOC_16C_DISP04
2337
@deffnx {} BFD_RELOC_16C_DISP04_C
2338
@deffnx {} BFD_RELOC_16C_DISP08
2339
@deffnx {} BFD_RELOC_16C_DISP08_C
2340
@deffnx {} BFD_RELOC_16C_DISP16
2341
@deffnx {} BFD_RELOC_16C_DISP16_C
2342
@deffnx {} BFD_RELOC_16C_DISP24
2343
@deffnx {} BFD_RELOC_16C_DISP24_C
2344
@deffnx {} BFD_RELOC_16C_DISP24a
2345
@deffnx {} BFD_RELOC_16C_DISP24a_C
2346
@deffnx {} BFD_RELOC_16C_REG04
2347
@deffnx {} BFD_RELOC_16C_REG04_C
2348
@deffnx {} BFD_RELOC_16C_REG04a
2349
@deffnx {} BFD_RELOC_16C_REG04a_C
2350
@deffnx {} BFD_RELOC_16C_REG14
2351
@deffnx {} BFD_RELOC_16C_REG14_C
2352
@deffnx {} BFD_RELOC_16C_REG16
2353
@deffnx {} BFD_RELOC_16C_REG16_C
2354
@deffnx {} BFD_RELOC_16C_REG20
2355
@deffnx {} BFD_RELOC_16C_REG20_C
2356
@deffnx {} BFD_RELOC_16C_ABS20
2357
@deffnx {} BFD_RELOC_16C_ABS20_C
2358
@deffnx {} BFD_RELOC_16C_ABS24
2359
@deffnx {} BFD_RELOC_16C_ABS24_C
2360
@deffnx {} BFD_RELOC_16C_IMM04
2361
@deffnx {} BFD_RELOC_16C_IMM04_C
2362
@deffnx {} BFD_RELOC_16C_IMM16
2363
@deffnx {} BFD_RELOC_16C_IMM16_C
2364
@deffnx {} BFD_RELOC_16C_IMM20
2365
@deffnx {} BFD_RELOC_16C_IMM20_C
2366
@deffnx {} BFD_RELOC_16C_IMM24
2367
@deffnx {} BFD_RELOC_16C_IMM24_C
2368
@deffnx {} BFD_RELOC_16C_IMM32
2369
@deffnx {} BFD_RELOC_16C_IMM32_C
2370
NS CR16C Relocations.
2371
@end deffn
2372
@deffn {} BFD_RELOC_CR16_NUM8
2373
@deffnx {} BFD_RELOC_CR16_NUM16
2374
@deffnx {} BFD_RELOC_CR16_NUM32
2375
@deffnx {} BFD_RELOC_CR16_NUM32a
2376
@deffnx {} BFD_RELOC_CR16_REGREL0
2377
@deffnx {} BFD_RELOC_CR16_REGREL4
2378
@deffnx {} BFD_RELOC_CR16_REGREL4a
2379
@deffnx {} BFD_RELOC_CR16_REGREL14
2380
@deffnx {} BFD_RELOC_CR16_REGREL14a
2381
@deffnx {} BFD_RELOC_CR16_REGREL16
2382
@deffnx {} BFD_RELOC_CR16_REGREL20
2383
@deffnx {} BFD_RELOC_CR16_REGREL20a
2384
@deffnx {} BFD_RELOC_CR16_ABS20
2385
@deffnx {} BFD_RELOC_CR16_ABS24
2386
@deffnx {} BFD_RELOC_CR16_IMM4
2387
@deffnx {} BFD_RELOC_CR16_IMM8
2388
@deffnx {} BFD_RELOC_CR16_IMM16
2389
@deffnx {} BFD_RELOC_CR16_IMM20
2390
@deffnx {} BFD_RELOC_CR16_IMM24
2391
@deffnx {} BFD_RELOC_CR16_IMM32
2392
@deffnx {} BFD_RELOC_CR16_IMM32a
2393
@deffnx {} BFD_RELOC_CR16_DISP4
2394
@deffnx {} BFD_RELOC_CR16_DISP8
2395
@deffnx {} BFD_RELOC_CR16_DISP16
2396
@deffnx {} BFD_RELOC_CR16_DISP20
2397
@deffnx {} BFD_RELOC_CR16_DISP24
2398
@deffnx {} BFD_RELOC_CR16_DISP24a
2399
@deffnx {} BFD_RELOC_CR16_SWITCH8
2400
@deffnx {} BFD_RELOC_CR16_SWITCH16
2401
@deffnx {} BFD_RELOC_CR16_SWITCH32
2402
@deffnx {} BFD_RELOC_CR16_GOT_REGREL20
2403
@deffnx {} BFD_RELOC_CR16_GOTC_REGREL20
2404
@deffnx {} BFD_RELOC_CR16_GLOB_DAT
2405
NS CR16 Relocations.
2406
@end deffn
2407
@deffn {} BFD_RELOC_CRX_REL4
2408
@deffnx {} BFD_RELOC_CRX_REL8
2409
@deffnx {} BFD_RELOC_CRX_REL8_CMP
2410
@deffnx {} BFD_RELOC_CRX_REL16
2411
@deffnx {} BFD_RELOC_CRX_REL24
2412
@deffnx {} BFD_RELOC_CRX_REL32
2413
@deffnx {} BFD_RELOC_CRX_REGREL12
2414
@deffnx {} BFD_RELOC_CRX_REGREL22
2415
@deffnx {} BFD_RELOC_CRX_REGREL28
2416
@deffnx {} BFD_RELOC_CRX_REGREL32
2417
@deffnx {} BFD_RELOC_CRX_ABS16
2418
@deffnx {} BFD_RELOC_CRX_ABS32
2419
@deffnx {} BFD_RELOC_CRX_NUM8
2420
@deffnx {} BFD_RELOC_CRX_NUM16
2421
@deffnx {} BFD_RELOC_CRX_NUM32
2422
@deffnx {} BFD_RELOC_CRX_IMM16
2423
@deffnx {} BFD_RELOC_CRX_IMM32
2424
@deffnx {} BFD_RELOC_CRX_SWITCH8
2425
@deffnx {} BFD_RELOC_CRX_SWITCH16
2426
@deffnx {} BFD_RELOC_CRX_SWITCH32
2427
NS CRX Relocations.
2428
@end deffn
2429
@deffn {} BFD_RELOC_CRIS_BDISP8
2430
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_5
2431
@deffnx {} BFD_RELOC_CRIS_SIGNED_6
2432
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_6
2433
@deffnx {} BFD_RELOC_CRIS_SIGNED_8
2434
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_8
2435
@deffnx {} BFD_RELOC_CRIS_SIGNED_16
2436
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_16
2437
@deffnx {} BFD_RELOC_CRIS_LAPCQ_OFFSET
2438
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_4
2439
These relocs are only used within the CRIS assembler.  They are not
2440
(at present) written to any object files.
2441
@end deffn
2442
@deffn {} BFD_RELOC_CRIS_COPY
2443
@deffnx {} BFD_RELOC_CRIS_GLOB_DAT
2444
@deffnx {} BFD_RELOC_CRIS_JUMP_SLOT
2445
@deffnx {} BFD_RELOC_CRIS_RELATIVE
2446
Relocs used in ELF shared libraries for CRIS.
2447
@end deffn
2448
@deffn {} BFD_RELOC_CRIS_32_GOT
2449
32-bit offset to symbol-entry within GOT.
2450
@end deffn
2451
@deffn {} BFD_RELOC_CRIS_16_GOT
2452
16-bit offset to symbol-entry within GOT.
2453
@end deffn
2454
@deffn {} BFD_RELOC_CRIS_32_GOTPLT
2455
32-bit offset to symbol-entry within GOT, with PLT handling.
2456
@end deffn
2457
@deffn {} BFD_RELOC_CRIS_16_GOTPLT
2458
16-bit offset to symbol-entry within GOT, with PLT handling.
2459
@end deffn
2460
@deffn {} BFD_RELOC_CRIS_32_GOTREL
2461
32-bit offset to symbol, relative to GOT.
2462
@end deffn
2463
@deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL
2464
32-bit offset to symbol with PLT entry, relative to GOT.
2465
@end deffn
2466
@deffn {} BFD_RELOC_CRIS_32_PLT_PCREL
2467
32-bit offset to symbol with PLT entry, relative to this relocation.
2468
@end deffn
2469
@deffn {} BFD_RELOC_CRIS_32_GOT_GD
2470
@deffnx {} BFD_RELOC_CRIS_16_GOT_GD
2471
@deffnx {} BFD_RELOC_CRIS_32_GD
2472
@deffnx {} BFD_RELOC_CRIS_DTP
2473
@deffnx {} BFD_RELOC_CRIS_32_DTPREL
2474
@deffnx {} BFD_RELOC_CRIS_16_DTPREL
2475
@deffnx {} BFD_RELOC_CRIS_32_GOT_TPREL
2476
@deffnx {} BFD_RELOC_CRIS_16_GOT_TPREL
2477
@deffnx {} BFD_RELOC_CRIS_32_TPREL
2478
@deffnx {} BFD_RELOC_CRIS_16_TPREL
2479
@deffnx {} BFD_RELOC_CRIS_DTPMOD
2480
@deffnx {} BFD_RELOC_CRIS_32_IE
2481
Relocs used in TLS code for CRIS.
2482
@end deffn
2483
@deffn {} BFD_RELOC_860_COPY
2484
@deffnx {} BFD_RELOC_860_GLOB_DAT
2485
@deffnx {} BFD_RELOC_860_JUMP_SLOT
2486
@deffnx {} BFD_RELOC_860_RELATIVE
2487
@deffnx {} BFD_RELOC_860_PC26
2488
@deffnx {} BFD_RELOC_860_PLT26
2489
@deffnx {} BFD_RELOC_860_PC16
2490
@deffnx {} BFD_RELOC_860_LOW0
2491
@deffnx {} BFD_RELOC_860_SPLIT0
2492
@deffnx {} BFD_RELOC_860_LOW1
2493
@deffnx {} BFD_RELOC_860_SPLIT1
2494
@deffnx {} BFD_RELOC_860_LOW2
2495
@deffnx {} BFD_RELOC_860_SPLIT2
2496
@deffnx {} BFD_RELOC_860_LOW3
2497
@deffnx {} BFD_RELOC_860_LOGOT0
2498
@deffnx {} BFD_RELOC_860_SPGOT0
2499
@deffnx {} BFD_RELOC_860_LOGOT1
2500
@deffnx {} BFD_RELOC_860_SPGOT1
2501
@deffnx {} BFD_RELOC_860_LOGOTOFF0
2502
@deffnx {} BFD_RELOC_860_SPGOTOFF0
2503
@deffnx {} BFD_RELOC_860_LOGOTOFF1
2504
@deffnx {} BFD_RELOC_860_SPGOTOFF1
2505
@deffnx {} BFD_RELOC_860_LOGOTOFF2
2506
@deffnx {} BFD_RELOC_860_LOGOTOFF3
2507
@deffnx {} BFD_RELOC_860_LOPC
2508
@deffnx {} BFD_RELOC_860_HIGHADJ
2509
@deffnx {} BFD_RELOC_860_HAGOT
2510
@deffnx {} BFD_RELOC_860_HAGOTOFF
2511
@deffnx {} BFD_RELOC_860_HAPC
2512
@deffnx {} BFD_RELOC_860_HIGH
2513
@deffnx {} BFD_RELOC_860_HIGOT
2514
@deffnx {} BFD_RELOC_860_HIGOTOFF
2515
Intel i860 Relocations.
2516
@end deffn
2517
@deffn {} BFD_RELOC_OPENRISC_ABS_26
2518
@deffnx {} BFD_RELOC_OPENRISC_REL_26
2519
OpenRISC Relocations.
2520
@end deffn
2521
@deffn {} BFD_RELOC_H8_DIR16A8
2522
@deffnx {} BFD_RELOC_H8_DIR16R8
2523
@deffnx {} BFD_RELOC_H8_DIR24A8
2524
@deffnx {} BFD_RELOC_H8_DIR24R8
2525
@deffnx {} BFD_RELOC_H8_DIR32A16
2526
H8 elf Relocations.
2527
@end deffn
2528
@deffn {} BFD_RELOC_XSTORMY16_REL_12
2529
@deffnx {} BFD_RELOC_XSTORMY16_12
2530
@deffnx {} BFD_RELOC_XSTORMY16_24
2531
@deffnx {} BFD_RELOC_XSTORMY16_FPTR16
2532
Sony Xstormy16 Relocations.
2533
@end deffn
2534
@deffn {} BFD_RELOC_RELC
2535
Self-describing complex relocations.
2536
@end deffn
2537
@deffn {} BFD_RELOC_XC16X_PAG
2538
@deffnx {} BFD_RELOC_XC16X_POF
2539
@deffnx {} BFD_RELOC_XC16X_SEG
2540
@deffnx {} BFD_RELOC_XC16X_SOF
2541
Infineon Relocations.
2542
@end deffn
2543
@deffn {} BFD_RELOC_VAX_GLOB_DAT
2544
@deffnx {} BFD_RELOC_VAX_JMP_SLOT
2545
@deffnx {} BFD_RELOC_VAX_RELATIVE
2546
Relocations used by VAX ELF.
2547
@end deffn
2548
@deffn {} BFD_RELOC_MT_PC16
2549
Morpho MT - 16 bit immediate relocation.
2550
@end deffn
2551
@deffn {} BFD_RELOC_MT_HI16
2552
Morpho MT - Hi 16 bits of an address.
2553
@end deffn
2554
@deffn {} BFD_RELOC_MT_LO16
2555
Morpho MT - Low 16 bits of an address.
2556
@end deffn
2557
@deffn {} BFD_RELOC_MT_GNU_VTINHERIT
2558
Morpho MT - Used to tell the linker which vtable entries are used.
2559
@end deffn
2560
@deffn {} BFD_RELOC_MT_GNU_VTENTRY
2561
Morpho MT - Used to tell the linker which vtable entries are used.
2562
@end deffn
2563
@deffn {} BFD_RELOC_MT_PCINSN8
2564
Morpho MT - 8 bit immediate relocation.
2565
@end deffn
2566
@deffn {} BFD_RELOC_MSP430_10_PCREL
2567
@deffnx {} BFD_RELOC_MSP430_16_PCREL
2568
@deffnx {} BFD_RELOC_MSP430_16
2569
@deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE
2570
@deffnx {} BFD_RELOC_MSP430_16_BYTE
2571
@deffnx {} BFD_RELOC_MSP430_2X_PCREL
2572
@deffnx {} BFD_RELOC_MSP430_RL_PCREL
2573
msp430 specific relocation codes
2574
@end deffn
2575
@deffn {} BFD_RELOC_IQ2000_OFFSET_16
2576
@deffnx {} BFD_RELOC_IQ2000_OFFSET_21
2577
@deffnx {} BFD_RELOC_IQ2000_UHI16
2578
IQ2000 Relocations.
2579
@end deffn
2580
@deffn {} BFD_RELOC_XTENSA_RTLD
2581
Special Xtensa relocation used only by PLT entries in ELF shared
2582
objects to indicate that the runtime linker should set the value
2583
to one of its own internal functions or data structures.
2584
@end deffn
2585
@deffn {} BFD_RELOC_XTENSA_GLOB_DAT
2586
@deffnx {} BFD_RELOC_XTENSA_JMP_SLOT
2587
@deffnx {} BFD_RELOC_XTENSA_RELATIVE
2588
Xtensa relocations for ELF shared objects.
2589
@end deffn
2590
@deffn {} BFD_RELOC_XTENSA_PLT
2591
Xtensa relocation used in ELF object files for symbols that may require
2592
PLT entries.  Otherwise, this is just a generic 32-bit relocation.
2593
@end deffn
2594
@deffn {} BFD_RELOC_XTENSA_DIFF8
2595
@deffnx {} BFD_RELOC_XTENSA_DIFF16
2596
@deffnx {} BFD_RELOC_XTENSA_DIFF32
2597
Xtensa relocations to mark the difference of two local symbols.
2598
These are only needed to support linker relaxation and can be ignored
2599
when not relaxing.  The field is set to the value of the difference
2600
assuming no relaxation.  The relocation encodes the position of the
2601
first symbol so the linker can determine whether to adjust the field
2602
value.
2603
@end deffn
2604
@deffn {} BFD_RELOC_XTENSA_SLOT0_OP
2605
@deffnx {} BFD_RELOC_XTENSA_SLOT1_OP
2606
@deffnx {} BFD_RELOC_XTENSA_SLOT2_OP
2607
@deffnx {} BFD_RELOC_XTENSA_SLOT3_OP
2608
@deffnx {} BFD_RELOC_XTENSA_SLOT4_OP
2609
@deffnx {} BFD_RELOC_XTENSA_SLOT5_OP
2610
@deffnx {} BFD_RELOC_XTENSA_SLOT6_OP
2611
@deffnx {} BFD_RELOC_XTENSA_SLOT7_OP
2612
@deffnx {} BFD_RELOC_XTENSA_SLOT8_OP
2613
@deffnx {} BFD_RELOC_XTENSA_SLOT9_OP
2614
@deffnx {} BFD_RELOC_XTENSA_SLOT10_OP
2615
@deffnx {} BFD_RELOC_XTENSA_SLOT11_OP
2616
@deffnx {} BFD_RELOC_XTENSA_SLOT12_OP
2617
@deffnx {} BFD_RELOC_XTENSA_SLOT13_OP
2618
@deffnx {} BFD_RELOC_XTENSA_SLOT14_OP
2619
Generic Xtensa relocations for instruction operands.  Only the slot
2620
number is encoded in the relocation.  The relocation applies to the
2621
last PC-relative immediate operand, or if there are no PC-relative
2622
immediates, to the last immediate operand.
2623
@end deffn
2624
@deffn {} BFD_RELOC_XTENSA_SLOT0_ALT
2625
@deffnx {} BFD_RELOC_XTENSA_SLOT1_ALT
2626
@deffnx {} BFD_RELOC_XTENSA_SLOT2_ALT
2627
@deffnx {} BFD_RELOC_XTENSA_SLOT3_ALT
2628
@deffnx {} BFD_RELOC_XTENSA_SLOT4_ALT
2629
@deffnx {} BFD_RELOC_XTENSA_SLOT5_ALT
2630
@deffnx {} BFD_RELOC_XTENSA_SLOT6_ALT
2631
@deffnx {} BFD_RELOC_XTENSA_SLOT7_ALT
2632
@deffnx {} BFD_RELOC_XTENSA_SLOT8_ALT
2633
@deffnx {} BFD_RELOC_XTENSA_SLOT9_ALT
2634
@deffnx {} BFD_RELOC_XTENSA_SLOT10_ALT
2635
@deffnx {} BFD_RELOC_XTENSA_SLOT11_ALT
2636
@deffnx {} BFD_RELOC_XTENSA_SLOT12_ALT
2637
@deffnx {} BFD_RELOC_XTENSA_SLOT13_ALT
2638
@deffnx {} BFD_RELOC_XTENSA_SLOT14_ALT
2639
Alternate Xtensa relocations.  Only the slot is encoded in the
2640
relocation.  The meaning of these relocations is opcode-specific.
2641
@end deffn
2642
@deffn {} BFD_RELOC_XTENSA_OP0
2643
@deffnx {} BFD_RELOC_XTENSA_OP1
2644
@deffnx {} BFD_RELOC_XTENSA_OP2
2645
Xtensa relocations for backward compatibility.  These have all been
2646
replaced by BFD_RELOC_XTENSA_SLOT0_OP.
2647
@end deffn
2648
@deffn {} BFD_RELOC_XTENSA_ASM_EXPAND
2649
Xtensa relocation to mark that the assembler expanded the
2650
instructions from an original target.  The expansion size is
2651
encoded in the reloc size.
2652
@end deffn
2653
@deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY
2654
Xtensa relocation to mark that the linker should simplify
2655
assembler-expanded instructions.  This is commonly used
2656
internally by the linker after analysis of a
2657
BFD_RELOC_XTENSA_ASM_EXPAND.
2658
@end deffn
2659
@deffn {} BFD_RELOC_XTENSA_TLSDESC_FN
2660
@deffnx {} BFD_RELOC_XTENSA_TLSDESC_ARG
2661
@deffnx {} BFD_RELOC_XTENSA_TLS_DTPOFF
2662
@deffnx {} BFD_RELOC_XTENSA_TLS_TPOFF
2663
@deffnx {} BFD_RELOC_XTENSA_TLS_FUNC
2664
@deffnx {} BFD_RELOC_XTENSA_TLS_ARG
2665
@deffnx {} BFD_RELOC_XTENSA_TLS_CALL
2666
Xtensa TLS relocations.
2667
@end deffn
2668
@deffn {} BFD_RELOC_Z80_DISP8
2669
8 bit signed offset in (ix+d) or (iy+d).
2670
@end deffn
2671
@deffn {} BFD_RELOC_Z8K_DISP7
2672
DJNZ offset.
2673
@end deffn
2674
@deffn {} BFD_RELOC_Z8K_CALLR
2675
CALR offset.
2676
@end deffn
2677
@deffn {} BFD_RELOC_Z8K_IMM4L
2678
4 bit value.
2679
@end deffn
2680
@deffn {} BFD_RELOC_LM32_CALL
2681
@deffnx {} BFD_RELOC_LM32_BRANCH
2682
@deffnx {} BFD_RELOC_LM32_16_GOT
2683
@deffnx {} BFD_RELOC_LM32_GOTOFF_HI16
2684
@deffnx {} BFD_RELOC_LM32_GOTOFF_LO16
2685
@deffnx {} BFD_RELOC_LM32_COPY
2686
@deffnx {} BFD_RELOC_LM32_GLOB_DAT
2687
@deffnx {} BFD_RELOC_LM32_JMP_SLOT
2688
@deffnx {} BFD_RELOC_LM32_RELATIVE
2689
Lattice Mico32 relocations.
2690
@end deffn
2691
@deffn {} BFD_RELOC_MACH_O_SECTDIFF
2692
Difference between two section addreses.  Must be followed by a
2693
BFD_RELOC_MACH_O_PAIR.
2694
@end deffn
2695
@deffn {} BFD_RELOC_MACH_O_PAIR
2696
Pair of relocation.  Contains the first symbol.
2697
@end deffn
2698
@deffn {} BFD_RELOC_MACH_O_X86_64_BRANCH32
2699
@deffnx {} BFD_RELOC_MACH_O_X86_64_BRANCH8
2700
PCREL relocations.  They are marked as branch to create PLT entry if
2701
required.
2702
@end deffn
2703
@deffn {} BFD_RELOC_MACH_O_X86_64_GOT
2704
Used when referencing a GOT entry.
2705
@end deffn
2706
@deffn {} BFD_RELOC_MACH_O_X86_64_GOT_LOAD
2707
Used when loading a GOT entry with movq.  It is specially marked so that
2708
the linker could optimize the movq to a leaq if possible.
2709
@end deffn
2710
@deffn {} BFD_RELOC_MACH_O_X86_64_SUBTRACTOR32
2711
Symbol will be substracted.  Must be followed by a BFD_RELOC_64.
2712
@end deffn
2713
@deffn {} BFD_RELOC_MACH_O_X86_64_SUBTRACTOR64
2714
Symbol will be substracted.  Must be followed by a BFD_RELOC_64.
2715
@end deffn
2716
@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_1
2717
Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
2718
@end deffn
2719
@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_2
2720
Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
2721
@end deffn
2722
@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_4
2723
Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
2724
@end deffn
2725
@deffn {} BFD_RELOC_MICROBLAZE_32_LO
2726
This is a 32 bit reloc for the microblaze that stores the
2727
low 16 bits of a value
2728
@end deffn
2729
@deffn {} BFD_RELOC_MICROBLAZE_32_LO_PCREL
2730
This is a 32 bit pc-relative reloc for the microblaze that
2731
stores the low 16 bits of a value
2732
@end deffn
2733
@deffn {} BFD_RELOC_MICROBLAZE_32_ROSDA
2734
This is a 32 bit reloc for the microblaze that stores a
2735
value relative to the read-only small data area anchor
2736
@end deffn
2737
@deffn {} BFD_RELOC_MICROBLAZE_32_RWSDA
2738
This is a 32 bit reloc for the microblaze that stores a
2739
value relative to the read-write small data area anchor
2740
@end deffn
2741
@deffn {} BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
2742
This is a 32 bit reloc for the microblaze to handle
2743
expressions of the form "Symbol Op Symbol"
2744
@end deffn
2745
@deffn {} BFD_RELOC_MICROBLAZE_64_NONE
2746
This is a 64 bit reloc that stores the 32 bit pc relative
2747
value in two words (with an imm instruction).  No relocation is
2748
done here - only used for relaxing
2749
@end deffn
2750
@deffn {} BFD_RELOC_MICROBLAZE_64_GOTPC
2751
This is a 64 bit reloc that stores the 32 bit pc relative
2752
value in two words (with an imm instruction).  The relocation is
2753
PC-relative GOT offset
2754
@end deffn
2755
@deffn {} BFD_RELOC_MICROBLAZE_64_GOT
2756
This is a 64 bit reloc that stores the 32 bit pc relative
2757
value in two words (with an imm instruction).  The relocation is
2758
GOT offset
2759
@end deffn
2760
@deffn {} BFD_RELOC_MICROBLAZE_64_PLT
2761
This is a 64 bit reloc that stores the 32 bit pc relative
2762
value in two words (with an imm instruction).  The relocation is
2763
PC-relative offset into PLT
2764
@end deffn
2765
@deffn {} BFD_RELOC_MICROBLAZE_64_GOTOFF
2766
This is a 64 bit reloc that stores the 32 bit GOT relative
2767
value in two words (with an imm instruction).  The relocation is
2768
relative offset from _GLOBAL_OFFSET_TABLE_
2769
@end deffn
2770
@deffn {} BFD_RELOC_MICROBLAZE_32_GOTOFF
2771
This is a 32 bit reloc that stores the 32 bit GOT relative
2772
value in a word.  The relocation is relative offset from
2773
@end deffn
2774
@deffn {} BFD_RELOC_MICROBLAZE_COPY
2775
This is used to tell the dynamic linker to copy the value out of
2776
the dynamic object into the runtime process image.
2777
@end deffn
2778
 
2779
@example
2780
 
2781
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
2782
@end example
2783
@findex bfd_reloc_type_lookup
2784
@subsubsection @code{bfd_reloc_type_lookup}
2785
@strong{Synopsis}
2786
@example
2787
reloc_howto_type *bfd_reloc_type_lookup
2788
   (bfd *abfd, bfd_reloc_code_real_type code);
2789
reloc_howto_type *bfd_reloc_name_lookup
2790
   (bfd *abfd, const char *reloc_name);
2791
@end example
2792
@strong{Description}@*
2793
Return a pointer to a howto structure which, when
2794
invoked, will perform the relocation @var{code} on data from the
2795
architecture noted.
2796
 
2797
@findex bfd_default_reloc_type_lookup
2798
@subsubsection @code{bfd_default_reloc_type_lookup}
2799
@strong{Synopsis}
2800
@example
2801
reloc_howto_type *bfd_default_reloc_type_lookup
2802
   (bfd *abfd, bfd_reloc_code_real_type  code);
2803
@end example
2804
@strong{Description}@*
2805
Provides a default relocation lookup routine for any architecture.
2806
 
2807
@findex bfd_get_reloc_code_name
2808
@subsubsection @code{bfd_get_reloc_code_name}
2809
@strong{Synopsis}
2810
@example
2811
const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
2812
@end example
2813
@strong{Description}@*
2814
Provides a printable name for the supplied relocation code.
2815
Useful mainly for printing error messages.
2816
 
2817
@findex bfd_generic_relax_section
2818
@subsubsection @code{bfd_generic_relax_section}
2819
@strong{Synopsis}
2820
@example
2821
bfd_boolean bfd_generic_relax_section
2822
   (bfd *abfd,
2823
    asection *section,
2824
    struct bfd_link_info *,
2825
    bfd_boolean *);
2826
@end example
2827
@strong{Description}@*
2828
Provides default handling for relaxing for back ends which
2829
don't do relaxing.
2830
 
2831
@findex bfd_generic_gc_sections
2832
@subsubsection @code{bfd_generic_gc_sections}
2833
@strong{Synopsis}
2834
@example
2835
bfd_boolean bfd_generic_gc_sections
2836
   (bfd *, struct bfd_link_info *);
2837
@end example
2838
@strong{Description}@*
2839
Provides default handling for relaxing for back ends which
2840
don't do section gc -- i.e., does nothing.
2841
 
2842
@findex bfd_generic_merge_sections
2843
@subsubsection @code{bfd_generic_merge_sections}
2844
@strong{Synopsis}
2845
@example
2846
bfd_boolean bfd_generic_merge_sections
2847
   (bfd *, struct bfd_link_info *);
2848
@end example
2849
@strong{Description}@*
2850
Provides default handling for SEC_MERGE section merging for back ends
2851
which don't have SEC_MERGE support -- i.e., does nothing.
2852
 
2853
@findex bfd_generic_get_relocated_section_contents
2854
@subsubsection @code{bfd_generic_get_relocated_section_contents}
2855
@strong{Synopsis}
2856
@example
2857
bfd_byte *bfd_generic_get_relocated_section_contents
2858
   (bfd *abfd,
2859
    struct bfd_link_info *link_info,
2860
    struct bfd_link_order *link_order,
2861
    bfd_byte *data,
2862
    bfd_boolean relocatable,
2863
    asymbol **symbols);
2864
@end example
2865
@strong{Description}@*
2866
Provides default handling of relocation effort for back ends
2867
which can't be bothered to do it efficiently.
2868
 

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