Subversion Repositories openrisc_me

/* alpha-opc.c -- Alpha AXP opcode list

   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007

   Free Software Foundation, Inc.

   Contributed by Richard Henderson <rth@cygnus.com>,

   patterned after the PPC opcode handling written by Ian Lance Taylor.

   This file is part of libopcodes.

   This library is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 3, or (at your option)

   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT

   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public

   License for more details.

   You should have received a copy of the GNU General Public License

   along with this file; see the file COPYING.  If not, write to the

   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA

   02110-1301, USA.  */

#include <stdio.h>

#include "sysdep.h"

#include "opcode/alpha.h"

#include "bfd.h"

#include "opintl.h"

/* This file holds the Alpha AXP opcode table.  The opcode table includes

   almost all of the extended instruction mnemonics.  This permits the

   disassembler to use them, and simplifies the assembler logic, at the

   cost of increasing the table size.  The table is strictly constant

   data, so the compiler should be able to put it in the text segment.

   This file also holds the operand table.  All knowledge about inserting

   and extracting operands from instructions is kept in this file.

   The information for the base instruction set was compiled from the

   _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE,

   version 2.

   The information for the post-ev5 architecture extensions BWX, CIX and

   MAX came from version 3 of this same document, which is also available

   on-line at http://ftp.digital.com/pub/Digital/info/semiconductor

   /literature/alphahb2.pdf

   The information for the EV4 PALcode instructions was compiled from

   _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware

   Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary

   revision dated June 1994.

   The information for the EV5 PALcode instructions was compiled from

   _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital

   Order Number EC-QAEQB-TE, preliminary revision dated April 1995.  */

/* The RB field when it is the same as the RA field in the same insn.

   This operand is marked fake.  The insertion function just copies

   the RA field into the RB field, and the extraction function just

   checks that the fields are the same. */

static unsigned

insert_rba (unsigned insn,

            int value ATTRIBUTE_UNUSED,

            const char **errmsg ATTRIBUTE_UNUSED)

{

  return insn | (((insn >> 21) & 0x1f) << 16);

}

static int

extract_rba (unsigned insn, int *invalid)

{

  if (invalid != (int *) NULL

      && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))

    *invalid = 1;

  return 0;

}

/* The same for the RC field.  */

static unsigned

insert_rca (unsigned insn,

            int value ATTRIBUTE_UNUSED,

            const char **errmsg ATTRIBUTE_UNUSED)

{

  return insn | ((insn >> 21) & 0x1f);

}

static int

extract_rca (unsigned insn, int *invalid)

{

  if (invalid != (int *) NULL

      && ((insn >> 21) & 0x1f) != (insn & 0x1f))

    *invalid = 1;

  return 0;

}

/* Fake arguments in which the registers must be set to ZERO.  */

static unsigned

insert_za (unsigned insn,

           int value ATTRIBUTE_UNUSED,

           const char **errmsg ATTRIBUTE_UNUSED)

{

  return insn | (31 << 21);

}

static int

extract_za (unsigned insn, int *invalid)

{

  if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31)

    *invalid = 1;

  return 0;

}

static unsigned

insert_zb (unsigned insn,

           int value ATTRIBUTE_UNUSED,

           const char **errmsg ATTRIBUTE_UNUSED)

{

  return insn | (31 << 16);

}

static int

extract_zb (unsigned insn, int *invalid)

{

  if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31)

    *invalid = 1;

  return 0;

}

static unsigned

insert_zc (unsigned insn,

           int value ATTRIBUTE_UNUSED,

           const char **errmsg ATTRIBUTE_UNUSED)

{

  return insn | 31;

}

static int

extract_zc (unsigned insn, int *invalid)

{

  if (invalid != (int *) NULL && (insn & 0x1f) != 31)

    *invalid = 1;

  return 0;

}

/* The displacement field of a Branch format insn.  */

static unsigned

insert_bdisp (unsigned insn, int value, const char **errmsg)

{

  if (errmsg != (const char **)NULL && (value & 3))

    *errmsg = _("branch operand unaligned");

  return insn | ((value / 4) & 0x1FFFFF);

}

static int

extract_bdisp (unsigned insn, int *invalid ATTRIBUTE_UNUSED)

{

  return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000);

}

/* The hint field of a JMP/JSR insn.  */

static unsigned

insert_jhint (unsigned insn, int value, const char **errmsg)

{

  if (errmsg != (const char **)NULL && (value & 3))

    *errmsg = _("jump hint unaligned");

  return insn | ((value / 4) & 0x3FFF);

}

static int

extract_jhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED)

{

  return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000);

}

/* The hint field of an EV6 HW_JMP/JSR insn.  */

static unsigned

insert_ev6hwjhint (unsigned insn, int value, const char **errmsg)

{

  if (errmsg != (const char **)NULL && (value & 3))

    *errmsg = _("jump hint unaligned");

  return insn | ((value / 4) & 0x1FFF);

}

static int

extract_ev6hwjhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED)

{

  return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000);

}

/* The operands table.   */

const struct alpha_operand alpha_operands[] =

{

  /* The fields are bits, shift, insert, extract, flags */

  /* The zero index is used to indicate end-of-list */

#define UNUSED          0

  { 0, 0, 0, 0, 0, 0 },

  /* The plain integer register fields.  */

#define RA              (UNUSED + 1)

  { 5, 21, 0, AXP_OPERAND_IR, 0, 0 },

#define RB              (RA + 1)

  { 5, 16, 0, AXP_OPERAND_IR, 0, 0 },

#define RC              (RB + 1)

  { 5, 0, 0, AXP_OPERAND_IR, 0, 0 },

  /* The plain fp register fields.  */

#define FA              (RC + 1)

  { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 },

#define FB              (FA + 1)

  { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 },

#define FC              (FB + 1)

  { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 },

  /* The integer registers when they are ZERO.  */

#define ZA              (FC + 1)

  { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za },

#define ZB              (ZA + 1)

  { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb },

#define ZC              (ZB + 1)

  { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc },

  /* The RB field when it needs parentheses.  */

#define PRB             (ZC + 1)

  { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 },

  /* The RB field when it needs parentheses _and_ a preceding comma.  */

#define CPRB            (PRB + 1)

  { 5, 16, 0,

    AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 },

  /* The RB field when it must be the same as the RA field.  */

#define RBA             (CPRB + 1)

  { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba },

  /* The RC field when it must be the same as the RB field.  */

#define RCA             (RBA + 1)

  { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca },

  /* The RC field when it can *default* to RA.  */

#define DRC1            (RCA + 1)

  { 5, 0, 0,

    AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },

  /* The RC field when it can *default* to RB.  */

#define DRC2            (DRC1 + 1)

  { 5, 0, 0,

    AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },

  /* The FC field when it can *default* to RA.  */

#define DFC1            (DRC2 + 1)

  { 5, 0, 0,

    AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },

  /* The FC field when it can *default* to RB.  */

#define DFC2            (DFC1 + 1)

  { 5, 0, 0,

    AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },

  /* The unsigned 8-bit literal of Operate format insns.  */

#define LIT             (DFC2 + 1)

  { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 },

  /* The signed 16-bit displacement of Memory format insns.  From here

     we can't tell what relocation should be used, so don't use a default.  */

#define MDISP           (LIT + 1)

  { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 },

  /* The signed "23-bit" aligned displacement of Branch format insns.  */

#define BDISP           (MDISP + 1)

  { 21, 0, BFD_RELOC_23_PCREL_S2,

    AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },

  /* The 26-bit PALcode function */

#define PALFN           (BDISP + 1)

  { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 },

  /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint.  */

#define JMPHINT         (PALFN + 1)

  { 14, 0, BFD_RELOC_ALPHA_HINT,

    AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,

    insert_jhint, extract_jhint },

  /* The optional hint to RET/JSR_COROUTINE.  */

#define RETHINT         (JMPHINT + 1)

  { 14, 0, -RETHINT,

    AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 },

  /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns.  */

#define EV4HWDISP       (RETHINT + 1)

#define EV6HWDISP       (EV4HWDISP)

  { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 },

  /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns.  */

#define EV4HWINDEX      (EV4HWDISP + 1)

  { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },

  /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns

     that occur in DEC PALcode.  */

#define EV4EXTHWINDEX   (EV4HWINDEX + 1)

  { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },

  /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns.  */

#define EV5HWDISP       (EV4EXTHWINDEX + 1)

  { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 },

  /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns.  */

#define EV5HWINDEX      (EV5HWDISP + 1)

  { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },

  /* The 16-bit combined index/scoreboard mask for the ev6

     hw_m[ft]pr (pal19/pal1d) insns.  */

#define EV6HWINDEX      (EV5HWINDEX + 1)

  { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },

  /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn.  */

#define EV6HWJMPHINT    (EV6HWINDEX+ 1)

  { 8, 0, -EV6HWJMPHINT,

    AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,

    insert_ev6hwjhint, extract_ev6hwjhint }

};

const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands);

/* Macros used to form opcodes.  */

/* The main opcode.  */

#define OP(x)           (((x) & 0x3F) << 26)

#define OP_MASK         0xFC000000

/* Branch format instructions.  */

#define BRA_(oo)        OP(oo)

#define BRA_MASK        OP_MASK

#define BRA(oo)         BRA_(oo), BRA_MASK

/* Floating point format instructions.  */

#define FP_(oo,fff)     (OP(oo) | (((fff) & 0x7FF) << 5))

#define FP_MASK         (OP_MASK | 0xFFE0)

#define FP(oo,fff)      FP_(oo,fff), FP_MASK

/* Memory format instructions.  */

#define MEM_(oo)        OP(oo)

#define MEM_MASK        OP_MASK

#define MEM(oo)         MEM_(oo), MEM_MASK

/* Memory/Func Code format instructions.  */

#define MFC_(oo,ffff)   (OP(oo) | ((ffff) & 0xFFFF))

#define MFC_MASK        (OP_MASK | 0xFFFF)

#define MFC(oo,ffff)    MFC_(oo,ffff), MFC_MASK

/* Memory/Branch format instructions.  */

#define MBR_(oo,h)      (OP(oo) | (((h) & 3) << 14))

#define MBR_MASK        (OP_MASK | 0xC000)

#define MBR(oo,h)       MBR_(oo,h), MBR_MASK

/* Operate format instructions.  The OPRL variant specifies a

   literal second argument.  */

#define OPR_(oo,ff)     (OP(oo) | (((ff) & 0x7F) << 5))

#define OPRL_(oo,ff)    (OPR_((oo),(ff)) | 0x1000)

#define OPR_MASK        (OP_MASK | 0x1FE0)

#define OPR(oo,ff)      OPR_(oo,ff), OPR_MASK

#define OPRL(oo,ff)     OPRL_(oo,ff), OPR_MASK

/* Generic PALcode format instructions.  */

#define PCD_(oo)        OP(oo)

#define PCD_MASK        OP_MASK

#define PCD(oo)         PCD_(oo), PCD_MASK

/* Specific PALcode instructions.  */

#define SPCD_(oo,ffff)  (OP(oo) | ((ffff) & 0x3FFFFFF))

#define SPCD_MASK       0xFFFFFFFF

#define SPCD(oo,ffff)   SPCD_(oo,ffff), SPCD_MASK

/* Hardware memory (hw_{ld,st}) instructions.  */

#define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))

#define EV4HWMEM_MASK   (OP_MASK | 0xF000)

#define EV4HWMEM(oo,f)  EV4HWMEM_(oo,f), EV4HWMEM_MASK

#define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10))

#define EV5HWMEM_MASK   (OP_MASK | 0xF800)

#define EV5HWMEM(oo,f)  EV5HWMEM_(oo,f), EV5HWMEM_MASK

#define EV6HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))

#define EV6HWMEM_MASK   (OP_MASK | 0xF000)

#define EV6HWMEM(oo,f)  EV6HWMEM_(oo,f), EV6HWMEM_MASK

#define EV6HWMBR_(oo,h) (OP(oo) | (((h) & 7) << 13))

#define EV6HWMBR_MASK   (OP_MASK | 0xE000)

#define EV6HWMBR(oo,h)  EV6HWMBR_(oo,h), EV6HWMBR_MASK

/* Abbreviations for instruction subsets.  */

#define BASE                    AXP_OPCODE_BASE

#define EV4                     AXP_OPCODE_EV4

#define EV5                     AXP_OPCODE_EV5

#define EV6                     AXP_OPCODE_EV6

#define BWX                     AXP_OPCODE_BWX

#define CIX                     AXP_OPCODE_CIX

#define MAX                     AXP_OPCODE_MAX

/* Common combinations of arguments.  */

#define ARG_NONE                { 0 }

#define ARG_BRA                 { RA, BDISP }

#define ARG_FBRA                { FA, BDISP }

#define ARG_FP                  { FA, FB, DFC1 }

#define ARG_FPZ1                { ZA, FB, DFC1 }

#define ARG_MEM                 { RA, MDISP, PRB }

#define ARG_FMEM                { FA, MDISP, PRB }

#define ARG_OPR                 { RA, RB, DRC1 }

#define ARG_OPRL                { RA, LIT, DRC1 }

#define ARG_OPRZ1               { ZA, RB, DRC1 }

#define ARG_OPRLZ1              { ZA, LIT, RC }

#define ARG_PCD                 { PALFN }

#define ARG_EV4HWMEM            { RA, EV4HWDISP, PRB }

#define ARG_EV4HWMPR            { RA, RBA, EV4HWINDEX }

#define ARG_EV5HWMEM            { RA, EV5HWDISP, PRB }

#define ARG_EV6HWMEM            { RA, EV6HWDISP, PRB }

/* The opcode table.

   The format of the opcode table is:

   NAME OPCODE MASK { OPERANDS }

   NAME         is the name of the instruction.

   OPCODE       is the instruction opcode.

   MASK         is the opcode mask; this is used to tell the disassembler

                which bits in the actual opcode must match OPCODE.

   OPERANDS     is the list of operands.

   The preceding macros merge the text of the OPCODE and MASK fields.

   The disassembler reads the table in order and prints the first

   instruction which matches, so this table is sorted to put more

   specific instructions before more general instructions.

   Otherwise, it is sorted by major opcode and minor function code.

   There are three classes of not-really-instructions in this table:

   ALIAS        is another name for another instruction.  Some of

                these come from the Architecture Handbook, some

                come from the original gas opcode tables.  In all

                cases, the functionality of the opcode is unchanged.

   PSEUDO       a stylized code form endorsed by Chapter A.4 of the

                Architecture Handbook.

   EXTRA        a stylized code form found in the original gas tables.

   And two annotations:

   EV56 BUT     opcodes that are officially introduced as of the ev56,

                but with defined results on previous implementations.

   EV56 UNA     opcodes that were introduced as of the ev56 with

                presumably undefined results on previous implementations

                that were not assigned to a particular extension.  */

const struct alpha_opcode alpha_opcodes[] =

{

  { "halt",             SPCD(0x00,0x0000), BASE, ARG_NONE },

  { "draina",           SPCD(0x00,0x0002), BASE, ARG_NONE },

  { "bpt",              SPCD(0x00,0x0080), BASE, ARG_NONE },

  { "bugchk",           SPCD(0x00,0x0081), BASE, ARG_NONE },

  { "callsys",          SPCD(0x00,0x0083), BASE, ARG_NONE },

  { "chmk",             SPCD(0x00,0x0083), BASE, ARG_NONE },

  { "imb",              SPCD(0x00,0x0086), BASE, ARG_NONE },

  { "rduniq",           SPCD(0x00,0x009e), BASE, ARG_NONE },

  { "wruniq",           SPCD(0x00,0x009f), BASE, ARG_NONE },

  { "gentrap",          SPCD(0x00,0x00aa), BASE, ARG_NONE },

  { "call_pal",         PCD(0x00), BASE, ARG_PCD },

  { "pal",              PCD(0x00), BASE, ARG_PCD },             /* alias */

  { "lda",              MEM(0x08), BASE, { RA, MDISP, ZB } },   /* pseudo */

  { "lda",              MEM(0x08), BASE, ARG_MEM },

  { "ldah",             MEM(0x09), BASE, { RA, MDISP, ZB } },   /* pseudo */

  { "ldah",             MEM(0x09), BASE, ARG_MEM },

  { "ldbu",             MEM(0x0A), BWX, ARG_MEM },

  { "unop",             MEM_(0x0B) | (30 << 16),

                        MEM_MASK, BASE, { ZA } },               /* pseudo */

  { "ldq_u",            MEM(0x0B), BASE, ARG_MEM },

  { "ldwu",             MEM(0x0C), BWX, ARG_MEM },

  { "stw",              MEM(0x0D), BWX, ARG_MEM },

  { "stb",              MEM(0x0E), BWX, ARG_MEM },

  { "stq_u",            MEM(0x0F), BASE, ARG_MEM },

  { "sextl",            OPR(0x10,0x00), BASE, ARG_OPRZ1 },      /* pseudo */

  { "sextl",            OPRL(0x10,0x00), BASE, ARG_OPRLZ1 },    /* pseudo */

  { "addl",             OPR(0x10,0x00), BASE, ARG_OPR },

  { "addl",             OPRL(0x10,0x00), BASE, ARG_OPRL },

  { "s4addl",           OPR(0x10,0x02), BASE, ARG_OPR },

  { "s4addl",           OPRL(0x10,0x02), BASE, ARG_OPRL },

  { "negl",             OPR(0x10,0x09), BASE, ARG_OPRZ1 },      /* pseudo */

  { "negl",             OPRL(0x10,0x09), BASE, ARG_OPRLZ1 },    /* pseudo */

  { "subl",             OPR(0x10,0x09), BASE, ARG_OPR },

  { "subl",             OPRL(0x10,0x09), BASE, ARG_OPRL },

  { "s4subl",           OPR(0x10,0x0B), BASE, ARG_OPR },

  { "s4subl",           OPRL(0x10,0x0B), BASE, ARG_OPRL },

  { "cmpbge",           OPR(0x10,0x0F), BASE, ARG_OPR },

  { "cmpbge",           OPRL(0x10,0x0F), BASE, ARG_OPRL },

  { "s8addl",           OPR(0x10,0x12), BASE, ARG_OPR },

  { "s8addl",           OPRL(0x10,0x12), BASE, ARG_OPRL },

  { "s8subl",           OPR(0x10,0x1B), BASE, ARG_OPR },

  { "s8subl",           OPRL(0x10,0x1B), BASE, ARG_OPRL },

  { "cmpult",           OPR(0x10,0x1D), BASE, ARG_OPR },

  { "cmpult",           OPRL(0x10,0x1D), BASE, ARG_OPRL },

  { "addq",             OPR(0x10,0x20), BASE, ARG_OPR },

  { "addq",             OPRL(0x10,0x20), BASE, ARG_OPRL },

  { "s4addq",           OPR(0x10,0x22), BASE, ARG_OPR },

  { "s4addq",           OPRL(0x10,0x22), BASE, ARG_OPRL },

  { "negq",             OPR(0x10,0x29), BASE, ARG_OPRZ1 },      /* pseudo */

  { "negq",             OPRL(0x10,0x29), BASE, ARG_OPRLZ1 },    /* pseudo */

  { "subq",             OPR(0x10,0x29), BASE, ARG_OPR },

  { "subq",             OPRL(0x10,0x29), BASE, ARG_OPRL },

  { "s4subq",           OPR(0x10,0x2B), BASE, ARG_OPR },

  { "s4subq",           OPRL(0x10,0x2B), BASE, ARG_OPRL },

  { "cmpeq",            OPR(0x10,0x2D), BASE, ARG_OPR },

  { "cmpeq",            OPRL(0x10,0x2D), BASE, ARG_OPRL },

  { "s8addq",           OPR(0x10,0x32), BASE, ARG_OPR },

  { "s8addq",           OPRL(0x10,0x32), BASE, ARG_OPRL },

  { "s8subq",           OPR(0x10,0x3B), BASE, ARG_OPR },

  { "s8subq",           OPRL(0x10,0x3B), BASE, ARG_OPRL },

  { "cmpule",           OPR(0x10,0x3D), BASE, ARG_OPR },

  { "cmpule",           OPRL(0x10,0x3D), BASE, ARG_OPRL },

  { "addl/v",           OPR(0x10,0x40), BASE, ARG_OPR },

  { "addl/v",           OPRL(0x10,0x40), BASE, ARG_OPRL },

  { "negl/v",           OPR(0x10,0x49), BASE, ARG_OPRZ1 },      /* pseudo */

  { "negl/v",           OPRL(0x10,0x49), BASE, ARG_OPRLZ1 },    /* pseudo */

  { "subl/v",           OPR(0x10,0x49), BASE, ARG_OPR },

  { "subl/v",           OPRL(0x10,0x49), BASE, ARG_OPRL },

  { "cmplt",            OPR(0x10,0x4D), BASE, ARG_OPR },

  { "cmplt",            OPRL(0x10,0x4D), BASE, ARG_OPRL },

  { "addq/v",           OPR(0x10,0x60), BASE, ARG_OPR },

  { "addq/v",           OPRL(0x10,0x60), BASE, ARG_OPRL },

  { "negq/v",           OPR(0x10,0x69), BASE, ARG_OPRZ1 },      /* pseudo */

  { "negq/v",           OPRL(0x10,0x69), BASE, ARG_OPRLZ1 },    /* pseudo */

  { "subq/v",           OPR(0x10,0x69), BASE, ARG_OPR },

  { "subq/v",           OPRL(0x10,0x69), BASE, ARG_OPRL },

  { "cmple",            OPR(0x10,0x6D), BASE, ARG_OPR },

  { "cmple",            OPRL(0x10,0x6D), BASE, ARG_OPRL },

  { "and",              OPR(0x11,0x00), BASE, ARG_OPR },

  { "and",              OPRL(0x11,0x00), BASE, ARG_OPRL },

  { "andnot",           OPR(0x11,0x08), BASE, ARG_OPR },        /* alias */

  { "andnot",           OPRL(0x11,0x08), BASE, ARG_OPRL },      /* alias */

  { "bic",              OPR(0x11,0x08), BASE, ARG_OPR },

  { "bic",              OPRL(0x11,0x08), BASE, ARG_OPRL },

  { "cmovlbs",          OPR(0x11,0x14), BASE, ARG_OPR },

  { "cmovlbs",          OPRL(0x11,0x14), BASE, ARG_OPRL },

  { "cmovlbc",          OPR(0x11,0x16), BASE, ARG_OPR },

  { "cmovlbc",          OPRL(0x11,0x16), BASE, ARG_OPRL },

  { "nop",              OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */

  { "clr",              OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */

  { "mov",              OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */

  { "mov",              OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */

  { "mov",              OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */

  { "or",               OPR(0x11,0x20), BASE, ARG_OPR },        /* alias */

  { "or",               OPRL(0x11,0x20), BASE, ARG_OPRL },      /* alias */

  { "bis",              OPR(0x11,0x20), BASE, ARG_OPR },

  { "bis",              OPRL(0x11,0x20), BASE, ARG_OPRL },

  { "cmoveq",           OPR(0x11,0x24), BASE, ARG_OPR },

  { "cmoveq",           OPRL(0x11,0x24), BASE, ARG_OPRL },

  { "cmovne",           OPR(0x11,0x26), BASE, ARG_OPR },

  { "cmovne",           OPRL(0x11,0x26), BASE, ARG_OPRL },

  { "not",              OPR(0x11,0x28), BASE, ARG_OPRZ1 },      /* pseudo */

  { "not",              OPRL(0x11,0x28), BASE, ARG_OPRLZ1 },    /* pseudo */

  { "ornot",            OPR(0x11,0x28), BASE, ARG_OPR },

  { "ornot",            OPRL(0x11,0x28), BASE, ARG_OPRL },

  { "xor",              OPR(0x11,0x40), BASE, ARG_OPR },

  { "xor",              OPRL(0x11,0x40), BASE, ARG_OPRL },

  { "cmovlt",           OPR(0x11,0x44), BASE, ARG_OPR },

  { "cmovlt",           OPRL(0x11,0x44), BASE, ARG_OPRL },

  { "cmovge",           OPR(0x11,0x46), BASE, ARG_OPR },

  { "cmovge",           OPRL(0x11,0x46), BASE, ARG_OPRL },

  { "eqv",              OPR(0x11,0x48), BASE, ARG_OPR },

  { "eqv",              OPRL(0x11,0x48), BASE, ARG_OPRL },