Subversion Repositories openrisc_2011-10-31

/* i370-opc.c -- Instruction 370 (ESA/390) architecture opcode list

   Copyright 1994, 1999, 2000, 2001, 2003, 2005, 2007

   Free Software Foundation, Inc.

   PowerPC version written by Ian Lance Taylor, Cygnus Support

   Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org> 1998, 1999

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 3, or (at your option)

   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT

   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public

   License for more details.

   You should have received a copy of the GNU General Public License

   along with this file; see the file COPYING.  If not, write to the Free

   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA

   02110-1301, USA.  */

#include <stdio.h>

#include "sysdep.h"

#include "opcode/i370.h"

/* This file holds the i370 opcode table.  The opcode table

   includes almost all of the extended instruction mnemonics.  This

   permits the disassembler to use them, and simplifies the assembler

   logic, at the cost of increasing the table size.  The table is

   strictly constant data, so the compiler should be able to put it in

   the .text section.

   This file also holds the operand table.  All knowledge about

   inserting operands into instructions and vice-versa is kept in this

   file.  */

/* The functions used to insert and extract complicated operands.  */

static i370_insn_t

insert_ss_b2 (i370_insn_t insn, long value,

              const char **errmsg ATTRIBUTE_UNUSED)

{

  insn.i[1] |= (value & 0xf) << 28;

  return insn;

}

static i370_insn_t

insert_ss_d2 (i370_insn_t insn, long value,

              const char **errmsg ATTRIBUTE_UNUSED)

{

  insn.i[1] |= (value & 0xfff) << 16;

  return insn;

}

static i370_insn_t

insert_rxf_r3 (i370_insn_t insn, long value,

               const char **errmsg ATTRIBUTE_UNUSED)

{

  insn.i[1] |= (value & 0xf) << 28;

  return insn;

}

static long

extract_ss_b2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)

{

  return (insn.i[1] >>28) & 0xf;

}

static long

extract_ss_d2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)

{

  return (insn.i[1] >>16) & 0xfff;

}

static long

extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)

{

  return (insn.i[1] >>28) & 0xf;

}

/* The operands table.

   The fields are bits, shift, insert, extract, flags, name.

   The types:

   I370_OPERAND_GPR register, must name a register, must be present

   I370_OPERAND_RELATIVE displacement or legnth field, must be present

   I370_OPERAND_BASE base register; if present, must name a register

                      if absent, should take value of zero

   I370_OPERAND_INDEX index register; if present, must name a register

                      if absent, should take value of zero

   I370_OPERAND_OPTIONAL other optional operand (usuall reg?).  */

const struct i370_operand i370_operands[] =

{

  /* The zero index is used to indicate the end of the list of

     operands.  */

#define UNUSED 0

  { 0, 0, 0, 0, 0, "unused" },

  /* The R1 register field in an RR form instruction.  */

#define RR_R1 (UNUSED + 1)

#define RR_R1_MASK (0xf << 4)

  { 4, 4, 0, 0, I370_OPERAND_GPR, "RR R1" },

  /* The R2 register field in an RR form instruction.  */

#define RR_R2 (RR_R1 + 1)

#define RR_R2_MASK (0xf)

  { 4, 0, 0, 0, I370_OPERAND_GPR, "RR R2" },

  /* The I field in an RR form SVC-style instruction.  */

#define RR_I (RR_R2 + 1)

#define RR_I_MASK (0xff)

  { 8, 0, 0, 0, I370_OPERAND_RELATIVE, "RR I (svc)" },

  /* The R1 register field in an RRE form instruction.  */

#define RRE_R1 (RR_I + 1)

#define RRE_R1_MASK (0xf << 4)

  { 4, 4, 0, 0, I370_OPERAND_GPR, "RRE R1" },

  /* The R2 register field in an RRE form instruction.  */

#define RRE_R2 (RRE_R1 + 1)

#define RRE_R2_MASK (0xf)

  { 4, 0, 0, 0, I370_OPERAND_GPR, "RRE R2" },

  /* The R1 register field in an RRF form instruction.  */

#define RRF_R1 (RRE_R2 + 1)

#define RRF_R1_MASK (0xf << 4)

  { 4, 4, 0, 0, I370_OPERAND_GPR, "RRF R1" },

  /* The R2 register field in an RRF form instruction.  */

#define RRF_R2 (RRF_R1 + 1)

#define RRF_R2_MASK (0xf)

  { 4, 0, 0, 0, I370_OPERAND_GPR, "RRF R2" },

  /* The R3 register field in an RRF form instruction.  */

#define RRF_R3 (RRF_R2 + 1)

#define RRF_R3_MASK (0xf << 12)

  { 4, 12, 0, 0, I370_OPERAND_GPR, "RRF R3" },

  /* The R1 register field in an RX or RS form instruction.  */

#define RX_R1 (RRF_R3 + 1)

#define RX_R1_MASK (0xf << 20)

  { 4, 20, 0, 0, I370_OPERAND_GPR, "RX R1" },

  /* The X2 index field in an RX form instruction.  */

#define RX_X2 (RX_R1 + 1)

#define RX_X2_MASK (0xf << 16)

  { 4, 16, 0, 0, I370_OPERAND_GPR | I370_OPERAND_INDEX, "RX X2"},

  /* The B2 base field in an RX form instruction.  */

#define RX_B2 (RX_X2 + 1)

#define RX_B2_MASK (0xf << 12)

  { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE, "RX B2"},

  /* The D2 displacement field in an RX form instruction.  */

#define RX_D2 (RX_B2 + 1)

#define RX_D2_MASK (0xfff)

  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RX D2"},

 /* The R3 register field in an RXF form instruction.  */

#define RXF_R3 (RX_D2 + 1)

#define RXF_R3_MASK (0xf << 12)

  { 4, 12, insert_rxf_r3, extract_rxf_r3, I370_OPERAND_GPR, "RXF R3" },

  /* The D2 displacement field in an RS form instruction.  */

#define RS_D2 (RXF_R3 + 1)

#define RS_D2_MASK (0xfff)

  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RS D2"},

  /* The R3 register field in an RS form instruction.  */

#define RS_R3 (RS_D2 + 1)

#define RS_R3_MASK (0xf << 16)

  { 4, 16, 0, 0, I370_OPERAND_GPR, "RS R3" },

  /* The B2 base field in an RS form instruction.  */

#define RS_B2 (RS_R3 + 1)

#define RS_B2_MASK (0xf << 12)

  { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "RS B2"},

  /* The optional B2 base field in an RS form instruction.  */

  /* Note that this field will almost always be absent */

#define RS_B2_OPT (RS_B2 + 1)

#define RS_B2_OPT_MASK (0xf << 12)

  { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_OPTIONAL, "RS B2 OPT"},

  /* The R1 register field in an RSI form instruction.  */

#define RSI_R1 (RS_B2_OPT + 1)

#define RSI_R1_MASK (0xf << 20)

  { 4, 20, 0, 0, I370_OPERAND_GPR, "RSI R1" },

  /* The R3 register field in an RSI form instruction.  */

#define RSI_R3 (RSI_R1 + 1)

#define RSI_R3_MASK (0xf << 16)

  { 4, 16, 0, 0, I370_OPERAND_GPR, "RSI R3" },

  /* The I2 immediate field in an RSI form instruction.  */

#define RSI_I2 (RSI_R3 + 1)

#define RSI_I2_MASK (0xffff)

  { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RSI I2" },

  /* The R1 register field in an RI form instruction.  */

#define RI_R1 (RSI_I2 + 1)

#define RI_R1_MASK (0xf << 20)

  { 4, 20, 0, 0, I370_OPERAND_GPR, "RI R1" },

  /* The I2 immediate field in an RI form instruction.  */

#define RI_I2 (RI_R1 + 1)

#define RI_I2_MASK (0xffff)

  { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RI I2" },

 /* The I2 index field in an SI form instruction.  */

#define SI_I2 (RI_I2 + 1)

#define SI_I2_MASK (0xff << 16)

  { 8, 16, 0, 0, I370_OPERAND_RELATIVE, "SI I2"},

 /* The B1 base register field in an SI form instruction.  */

#define SI_B1 (SI_I2 + 1)

#define SI_B1_MASK (0xf << 12)

  { 4, 12, 0, 0, I370_OPERAND_GPR, "SI B1" },

  /* The D1 displacement field in an SI form instruction.  */

#define SI_D1 (SI_B1 + 1)

#define SI_D1_MASK (0xfff)

  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SI D1" },

 /* The B2 base register field in an S form instruction.  */

#define S_B2 (SI_D1 + 1)

#define S_B2_MASK (0xf << 12)

  { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "S B2" },

  /* The D2 displacement field in an S form instruction.  */

#define S_D2 (S_B2 + 1)

#define S_D2_MASK (0xfff)

  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "S D2" },

  /* The L length field in an SS form instruction.  */

#define SS_L (S_D2 + 1)

#define SS_L_MASK (0xffff<<16)

  { 8, 16, 0, 0, I370_OPERAND_RELATIVE | I370_OPERAND_LENGTH, "SS L" },

 /* The B1 base register field in an SS form instruction.  */

#define SS_B1 (SS_L + 1)

#define SS_B1_MASK (0xf << 12)

  { 4, 12, 0, 0, I370_OPERAND_GPR, "SS B1" },

  /* The D1 displacement field in an SS form instruction.  */

#define SS_D1 (SS_B1 + 1)

#define SS_D1_MASK (0xfff)

  { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SS D1" },

 /* The B2 base register field in an SS form instruction.  */

#define SS_B2 (SS_D1 + 1)

#define SS_B2_MASK (0xf << 12)

  { 4, 12, insert_ss_b2, extract_ss_b2, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "SS B2" },

  /* The D2 displacement field in an SS form instruction.  */

#define SS_D2 (SS_B2 + 1)

#define SS_D2_MASK (0xfff)

  { 12, 0, insert_ss_d2, extract_ss_d2, I370_OPERAND_RELATIVE, "SS D2" },

};

/* Macros used to form opcodes.  */

/* The short-instruction opcode.  */

#define OPS(x) ((((unsigned short) (x)) & 0xff) << 8)

#define OPS_MASK OPS (0xff)

/* the extended instruction opcode */

#define XOPS(x) ((((unsigned short) (x)) & 0xff) << 24)

#define XOPS_MASK XOPS (0xff)

/* the S instruction opcode */

#define SOPS(x) ((((unsigned short) (x)) & 0xffff) << 16)

#define SOPS_MASK SOPS (0xffff)

/* the E instruction opcode */

#define EOPS(x) (((unsigned short) (x)) & 0xffff)

#define EOPS_MASK EOPS (0xffff)

/* the RI instruction opcode */

#define ROPS(x) (((((unsigned short) (x)) & 0xff0) << 20) | \

                 ((((unsigned short) (x)) & 0x00f) << 16))

#define ROPS_MASK ROPS (0xfff)

/* An E form instruction.  */

#define E(op)  (EOPS (op))

#define E_MASK E (0xffff)

/* An RR form instruction.  */

#define RR(op, r1, r2) \

  (OPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) |   \

              ((((unsigned short) (r2)) & 0xf) ))

#define RR_MASK RR (0xff, 0x0, 0x0)

/* An SVC-style instruction.  */

#define SVC(op, i) \

  (OPS (op) | (((unsigned short) (i)) & 0xff))

#define SVC_MASK SVC (0xff, 0x0)

/* An RRE form instruction.  */

#define RRE(op, r1, r2) \

  (SOPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) |   \

               ((((unsigned short) (r2)) & 0xf) ))

#define RRE_MASK RRE (0xffff, 0x0, 0x0)

/* An RRF form instruction.  */

#define RRF(op, r3, r1, r2) \

  (SOPS (op) | ((((unsigned short) (r3)) & 0xf) << 12) |   \

               ((((unsigned short) (r1)) & 0xf) << 4)  |   \

               ((((unsigned short) (r2)) & 0xf) ))

#define RRF_MASK RRF (0xffff, 0x0, 0x0, 0x0)

/* An RX form instruction.  */

#define RX(op, r1, x2, b2, d2) \

  (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) |  \

              ((((unsigned short) (x2)) & 0xf) << 16) |  \

              ((((unsigned short) (b2)) & 0xf) << 12) |  \

              ((((unsigned short) (d2)) & 0xfff)))

#define RX_MASK RX (0xff, 0x0, 0x0, 0x0, 0x0)

/* An RXE form instruction high word.  */

#define RXEH(op, r1, x2, b2, d2) \

  (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) |  \

              ((((unsigned short) (x2)) & 0xf) << 16) |  \

              ((((unsigned short) (b2)) & 0xf) << 12) |  \

              ((((unsigned short) (d2)) & 0xfff)))

#define RXEH_MASK RXEH (0xff, 0, 0, 0, 0)

/* An RXE form instruction low word.  */

#define RXEL(op) \

              ((((unsigned short) (op)) & 0xff) << 16 )

#define RXEL_MASK RXEL (0xff)

/* An RXF form instruction high word.  */

#define RXFH(op, r1, x2, b2, d2) \

  (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) |  \

              ((((unsigned short) (x2)) & 0xf) << 16) |  \

              ((((unsigned short) (b2)) & 0xf) << 12) |  \

              ((((unsigned short) (d2)) & 0xfff)))

#define RXFH_MASK RXFH (0xff, 0, 0, 0, 0)

/* An RXF form instruction low word.  */

#define RXFL(op, r3) \

              (((((unsigned short) (r3)) & 0xf)  << 28 ) | \

               ((((unsigned short) (op)) & 0xff) << 16 ))

#define RXFL_MASK RXFL (0xff, 0)

/* An RS form instruction.  */

#define RS(op, r1, b3, b2, d2) \

  (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) |  \

              ((((unsigned short) (b3)) & 0xf) << 16) |  \

              ((((unsigned short) (b2)) & 0xf) << 12) |  \

              ((((unsigned short) (d2)) & 0xfff)))

#define RS_MASK RS (0xff, 0x0, 0x0, 0x0, 0x0)

/* An RSI form instruction.  */

#define RSI(op, r1, r3, i2) \

  (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) |  \

              ((((unsigned short) (r3)) & 0xf) << 16) |  \

              ((((unsigned short) (i2)) & 0xffff)))

#define RSI_MASK RSI (0xff, 0x0, 0x0, 0x0)

/* An RI form instruction.  */

#define RI(op, r1, i2) \

  (ROPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) |  \

              ((((unsigned short) (i2)) & 0xffff)))

#define RI_MASK RI (0xfff, 0x0, 0x0)

/* An SI form instruction.  */

#define SI(op, i2, b1, d1) \

  (XOPS(op) | ((((unsigned short) (i2)) & 0xff) << 16) |  \

              ((((unsigned short) (b1)) & 0xf)  << 12) |  \

              ((((unsigned short) (d1)) & 0xfff)))

#define SI_MASK SI (0xff, 0x0, 0x0, 0x0)

/* An S form instruction.  */

#define S(op, b2, d2) \

  (SOPS(op) | ((((unsigned short)(b2)) & 0xf) << 12) |  \

              ((((unsigned short)(d2)) & 0xfff)))

#define S_MASK S (0xffff, 0x0, 0x0)

/* An SS form instruction high word.  */

#define SSH(op, l, b1, d1) \

  (XOPS(op) | ((((unsigned short) (l)) & 0xff) << 16) |  \

              ((((unsigned short) (b1)) & 0xf)  << 12) |  \

              ((((unsigned short) (d1)) & 0xfff)))

/* An SS form instruction low word.  */

#define SSL(b2, d2) \

            ( ((((unsigned short) (b1)) & 0xf)   << 28) |  \

              ((((unsigned short) (d1)) & 0xfff) << 16 ))

#define SS_MASK SSH (0xff, 0x0, 0x0, 0x0)

/* An SSE form instruction high word.  */

#define SSEH(op, b1, d1) \

  (SOPS(op) | ((((unsigned short) (b1)) & 0xf)  << 12) |  \

              ((((unsigned short) (d1)) & 0xfff)))

/* An SSE form instruction low word.  */

#define SSEL(b2, d2) \

            ( ((((unsigned short) (b1)) & 0xf)   << 28) |  \

              ((((unsigned short) (d1)) & 0xfff) << 16 ))

#define SSE_MASK SSEH (0xffff, 0x0, 0x0)

/* Smaller names for the flags so each entry in the opcodes table will

   fit on a single line.  These flags are set up so that e.g. IXA means

   the insn is supported on the 370/XA or newer architecture.

   Note that 370 or older obsolete insn's are not supported ...  */

#define IBF     I370_OPCODE_ESA390_BF

#define IBS     I370_OPCODE_ESA390_BS

#define ICK     I370_OPCODE_ESA390_CK

#define ICM     I370_OPCODE_ESA390_CM

#define IFX     I370_OPCODE_ESA390_FX

#define IHX     I370_OPCODE_ESA390_HX

#define IIR     I370_OPCODE_ESA390_IR

#define IMI     I370_OPCODE_ESA390_MI

#define IPC     I370_OPCODE_ESA390_PC

#define IPL     I370_OPCODE_ESA390_PL

#define IQR     I370_OPCODE_ESA390_QR

#define IRP     I370_OPCODE_ESA390_RP

#define ISA     I370_OPCODE_ESA390_SA

#define ISG     I370_OPCODE_ESA390_SG

#define ISR     I370_OPCODE_ESA390_SR

#define ITR     I370_OPCODE_ESA390_SR

#define I390    IBF  | IBS | ICK | ICM | IIR | IFX | IHX | IMI | IPC | IPL | IQR | IRP | ISA | ISG | ISR | ITR | I370_OPCODE_ESA390

#define IESA    I390 | I370_OPCODE_ESA370

#define IXA     IESA | I370_OPCODE_370_XA

#define I370    IXA  | I370_OPCODE_370

#define I360    I370 | I370_OPCODE_360

/* The opcode table.

   The format of the opcode table is:

   NAME     LEN  OPCODE_HI  OPCODE_LO   MASK_HI MASK_LO FLAGS           { OPERANDS }

   NAME is the name of the instruction.

   OPCODE is the instruction opcode.

   MASK is the opcode mask; this is used to tell the disassembler

     which bits in the actual opcode must match OPCODE.

   FLAGS are flags indicated what processors support the instruction.

   OPERANDS is the list of operands.

   The disassembler reads the table in order and prints the first

   instruction which matches, so this table is sorted to put more

   specific instructions before more general instructions.  It is also

   sorted by major opcode.  */

const struct i370_opcode i370_opcodes[] =

{

/* E form instructions */

{ "pr",     2, {{E(0x0101),    0}}, {{E_MASK,  0}}, IESA,  {0} },

{ "trap2",  2, {{E(0x01FF),    0}}, {{E_MASK,  0}}, ITR,   {0} },

{ "upt",    2, {{E(0x0102),    0}}, {{E_MASK,  0}}, IXA,   {0} },

/* RR form instructions */

{ "ar",     2, {{RR(0x1a,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "adr",    2, {{RR(0x2a,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "aer",    2, {{RR(0x3a,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "alr",    2, {{RR(0x1e,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "aur",    2, {{RR(0x2e,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "awr",    2, {{RR(0x3e,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "axr",    2, {{RR(0x36,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "balr",   2, {{RR(0x05,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "basr",   2, {{RR(0x0d,0,0), 0}}, {{RR_MASK, 0}}, IXA,   {RR_R1, RR_R2} },

{ "bassm",  2, {{RR(0x0c,0,0), 0}}, {{RR_MASK, 0}}, IXA,   {RR_R1, RR_R2} },

{ "bsm",    2, {{RR(0x0b,0,0), 0}}, {{RR_MASK, 0}}, IXA,   {RR_R1, RR_R2} },

{ "bcr",    2, {{RR(0x07,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "bctr",   2, {{RR(0x06,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "cdr",    2, {{RR(0x29,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "cer",    2, {{RR(0x39,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "clr",    2, {{RR(0x15,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "clcl",   2, {{RR(0x0f,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "cr",     2, {{RR(0x19,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "ddr",    2, {{RR(0x2d,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "der",    2, {{RR(0x3d,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "dr",     2, {{RR(0x1d,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "hdr",    2, {{RR(0x24,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "her",    2, {{RR(0x34,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "lcdr",   2, {{RR(0x23,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "lcer",   2, {{RR(0x33,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "lcr",    2, {{RR(0x13,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "ldr",    2, {{RR(0x28,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "ler",    2, {{RR(0x38,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "lndr",   2, {{RR(0x21,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "lner",   2, {{RR(0x31,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "lnr",    2, {{RR(0x11,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "lpdr",   2, {{RR(0x20,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "lper",   2, {{RR(0x30,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "lpr",    2, {{RR(0x10,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "lr",     2, {{RR(0x18,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "lrdr",   2, {{RR(0x25,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "lrer",   2, {{RR(0x35,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "ltdr",   2, {{RR(0x22,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },

{ "lter",   2, {{RR(0x32,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },