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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [opcodes/] [i386-opc.h] - Blame information for rev 318

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1 227 jeremybenn
/* Declarations for Intel 80386 opcode table
2
   Copyright 2007, 2008, 2009, 2010
3
   Free Software Foundation, Inc.
4
 
5
   This file is part of the GNU opcodes library.
6
 
7
   This library is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3, or (at your option)
10
   any later version.
11
 
12
   It is distributed in the hope that it will be useful, but WITHOUT
13
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
   License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with GAS; see the file COPYING.  If not, write to the Free
19
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20
   02110-1301, USA.  */
21
 
22
#include "opcode/i386.h"
23
#ifdef HAVE_LIMITS_H
24
#include <limits.h>
25
#endif
26
 
27
#ifndef CHAR_BIT
28
#define CHAR_BIT 8
29
#endif
30
 
31
/* Position of cpu flags bitfiled.  */
32
 
33
enum
34
{
35
  /* i186 or better required */
36
  Cpu186 = 0,
37
  /* i286 or better required */
38
  Cpu286,
39
  /* i386 or better required */
40
  Cpu386,
41
  /* i486 or better required */
42
  Cpu486,
43
  /* i585 or better required */
44
  Cpu586,
45
  /* i686 or better required */
46
  Cpu686,
47
  /* CLFLUSH Instuction support required */
48
  CpuClflush,
49
  /* SYSCALL Instuctions support required */
50
  CpuSYSCALL,
51
  /* Floating point support required */
52
  Cpu8087,
53
  /* i287 support required */
54
  Cpu287,
55
  /* i387 support required */
56
  Cpu387,
57
  /* i686 and floating point support required */
58
  Cpu687,
59
  /* SSE3 and floating point support required */
60
  CpuFISTTP,
61
  /* MMX support required */
62
  CpuMMX,
63
  /* SSE support required */
64
  CpuSSE,
65
  /* SSE2 support required */
66
  CpuSSE2,
67
  /* 3dnow! support required */
68
  Cpu3dnow,
69
  /* 3dnow! Extensions support required */
70
  Cpu3dnowA,
71
  /* SSE3 support required */
72
  CpuSSE3,
73
  /* VIA PadLock required */
74
  CpuPadLock,
75
  /* AMD Secure Virtual Machine Ext-s required */
76
  CpuSVME,
77
  /* VMX Instructions required */
78
  CpuVMX,
79
  /* SMX Instructions required */
80
  CpuSMX,
81
  /* SSSE3 support required */
82
  CpuSSSE3,
83
  /* SSE4a support required */
84
  CpuSSE4a,
85
  /* ABM New Instructions required */
86
  CpuABM,
87
  /* SSE4.1 support required */
88
  CpuSSE4_1,
89
  /* SSE4.2 support required */
90
  CpuSSE4_2,
91
  /* AVX support required */
92
  CpuAVX,
93
  /* Intel L1OM support required */
94
  CpuL1OM,
95
  /* Xsave/xrstor New Instuctions support required */
96
  CpuXsave,
97
  /* AES support required */
98
  CpuAES,
99
  /* PCLMUL support required */
100
  CpuPCLMUL,
101
  /* FMA support required */
102
  CpuFMA,
103
  /* FMA4 support required */
104
  CpuFMA4,
105
  /* XOP support required */
106
  CpuXOP,
107
  /* LWP support required */
108
  CpuLWP,
109
  /* MOVBE Instuction support required */
110
  CpuMovbe,
111
  /* EPT Instructions required */
112
  CpuEPT,
113
  /* RDTSCP Instuction support required */
114
  CpuRdtscp,
115
  /* 64bit support available, used by -march= in assembler.  */
116
  CpuLM,
117
  /* 64bit support required  */
118
  Cpu64,
119
  /* Not supported in the 64bit mode  */
120
  CpuNo64,
121
  /* The last bitfield in i386_cpu_flags.  */
122
  CpuMax = CpuNo64
123
};
124
 
125
#define CpuNumOfUints \
126
  (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
127
#define CpuNumOfBits \
128
  (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
129
 
130
/* If you get a compiler error for zero width of the unused field,
131
   comment it out.  */
132
#define CpuUnused       (CpuMax + 1)
133
 
134
/* We can check if an instruction is available with array instead
135
   of bitfield. */
136
typedef union i386_cpu_flags
137
{
138
  struct
139
    {
140
      unsigned int cpui186:1;
141
      unsigned int cpui286:1;
142
      unsigned int cpui386:1;
143
      unsigned int cpui486:1;
144
      unsigned int cpui586:1;
145
      unsigned int cpui686:1;
146
      unsigned int cpuclflush:1;
147
      unsigned int cpusyscall:1;
148
      unsigned int cpu8087:1;
149
      unsigned int cpu287:1;
150
      unsigned int cpu387:1;
151
      unsigned int cpu687:1;
152
      unsigned int cpufisttp:1;
153
      unsigned int cpummx:1;
154
      unsigned int cpusse:1;
155
      unsigned int cpusse2:1;
156
      unsigned int cpua3dnow:1;
157
      unsigned int cpua3dnowa:1;
158
      unsigned int cpusse3:1;
159
      unsigned int cpupadlock:1;
160
      unsigned int cpusvme:1;
161
      unsigned int cpuvmx:1;
162
      unsigned int cpusmx:1;
163
      unsigned int cpussse3:1;
164
      unsigned int cpusse4a:1;
165
      unsigned int cpuabm:1;
166
      unsigned int cpusse4_1:1;
167
      unsigned int cpusse4_2:1;
168
      unsigned int cpuavx:1;
169
      unsigned int cpul1om:1;
170
      unsigned int cpuxsave:1;
171
      unsigned int cpuaes:1;
172
      unsigned int cpupclmul:1;
173
      unsigned int cpufma:1;
174
      unsigned int cpufma4:1;
175
      unsigned int cpuxop:1;
176
      unsigned int cpulwp:1;
177
      unsigned int cpumovbe:1;
178
      unsigned int cpuept:1;
179
      unsigned int cpurdtscp:1;
180
      unsigned int cpulm:1;
181
      unsigned int cpu64:1;
182
      unsigned int cpuno64:1;
183
#ifdef CpuUnused
184
      unsigned int unused:(CpuNumOfBits - CpuUnused);
185
#endif
186
    } bitfield;
187
  unsigned int array[CpuNumOfUints];
188
} i386_cpu_flags;
189
 
190
/* Position of opcode_modifier bits.  */
191
 
192
enum
193
{
194
  /* has direction bit. */
195
  D = 0,
196
  /* set if operands can be words or dwords encoded the canonical way */
197
  W,
198
  /* Skip the current insn and use the next insn in i386-opc.tbl to swap
199
     operand in encoding.  */
200
  S,
201
  /* insn has a modrm byte. */
202
  Modrm,
203
  /* register is in low 3 bits of opcode */
204
  ShortForm,
205
  /* special case for jump insns.  */
206
  Jump,
207
  /* call and jump */
208
  JumpDword,
209
  /* loop and jecxz */
210
  JumpByte,
211
  /* special case for intersegment leaps/calls */
212
  JumpInterSegment,
213
  /* FP insn memory format bit, sized by 0x4 */
214
  FloatMF,
215
  /* src/dest swap for floats. */
216
  FloatR,
217
  /* has float insn direction bit. */
218
  FloatD,
219
  /* needs size prefix if in 32-bit mode */
220
  Size16,
221
  /* needs size prefix if in 16-bit mode */
222
  Size32,
223
  /* needs size prefix if in 64-bit mode */
224
  Size64,
225
  /* instruction ignores operand size prefix and in Intel mode ignores
226
     mnemonic size suffix check.  */
227
  IgnoreSize,
228
  /* default insn size depends on mode */
229
  DefaultSize,
230
  /* b suffix on instruction illegal */
231
  No_bSuf,
232
  /* w suffix on instruction illegal */
233
  No_wSuf,
234
  /* l suffix on instruction illegal */
235
  No_lSuf,
236
  /* s suffix on instruction illegal */
237
  No_sSuf,
238
  /* q suffix on instruction illegal */
239
  No_qSuf,
240
  /* long double suffix on instruction illegal */
241
  No_ldSuf,
242
  /* instruction needs FWAIT */
243
  FWait,
244
  /* quick test for string instructions */
245
  IsString,
246
  /* quick test for lockable instructions */
247
  IsLockable,
248
  /* fake an extra reg operand for clr, imul and special register
249
     processing for some instructions.  */
250
  RegKludge,
251
  /* The first operand must be xmm0 */
252
  FirstXmm0,
253
  /* An implicit xmm0 as the first operand */
254
  Implicit1stXmm0,
255
  /* Convert to DWORD */
256
  ToDword,
257
  /* Convert to QWORD */
258
  ToQword,
259
  /* Address prefix changes operand 0 */
260
  AddrPrefixOp0,
261
  /* opcode is a prefix */
262
  IsPrefix,
263
  /* instruction has extension in 8 bit imm */
264
  ImmExt,
265
  /* instruction don't need Rex64 prefix.  */
266
  NoRex64,
267
  /* instruction require Rex64 prefix.  */
268
  Rex64,
269
  /* deprecated fp insn, gets a warning */
270
  Ugh,
271
  /* insn has VEX prefix:
272
        1: 128bit VEX prefix.
273
        2: 256bit VEX prefix.
274
        3: Scalar VEX prefix.
275
   */
276
#define VEX128          1
277
#define VEX256          2
278
#define VEXScalar       3
279
  Vex,
280
  /* How to encode VEX.vvvv:
281
     0: VEX.vvvv must be 1111b.
282
     1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
283
        the content of source registers will be preserved.
284
        VEX.DDS.  The second register operand is encoded in VEX.vvvv
285
        where the content of first source register will be overwritten
286
        by the result.
287
        For assembler, there are no difference between VEX.NDS and
288
        VEX.DDS.
289
     2. VEX.NDD.  Register destination is encoded in VEX.vvvv.
290
     3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
291
        of the operands can access a memory location.
292
   */
293
#define VEXXDS  1
294
#define VEXNDD  2
295
#define VEXLWP  3
296
  VexVVVV,
297
  /* How the VEX.W bit is used:
298
     0: Set by the REX.W bit.
299
     1: VEX.W0.  Should always be 0.
300
     2: VEX.W1.  Should always be 1.
301
   */
302
#define VEXW0   1
303
#define VEXW1   2
304
  VexW,
305
  /* VEX opcode prefix:
306
     0: VEX 0x0F opcode prefix.
307
     1: VEX 0x0F38 opcode prefix.
308
     2: VEX 0x0F3A opcode prefix
309
     3: XOP 0x08 opcode prefix.
310
     4: XOP 0x09 opcode prefix
311
     5: XOP 0x0A opcode prefix.
312
   */
313
#define VEX0F           0
314
#define VEX0F38         1
315
#define VEX0F3A         2
316
#define XOP08           3
317
#define XOP09           4
318
#define XOP0A           5
319
  VexOpcode,
320
  /* number of VEX source operands:
321
     0: <= 2 source operands.
322
     1: 2 XOP source operands.
323
     2: 3 source operands.
324
   */
325
#define XOP2SOURCES     1
326
#define VEX3SOURCES     2
327
  VexSources,
328
  /* instruction has VEX 8 bit imm */
329
  VexImmExt,
330
  /* SSE to AVX support required */
331
  SSE2AVX,
332
  /* No AVX equivalent */
333
  NoAVX,
334
  /* Compatible with old (<= 2.8.1) versions of gcc  */
335
  OldGcc,
336
  /* AT&T mnemonic.  */
337
  ATTMnemonic,
338
  /* AT&T syntax.  */
339
  ATTSyntax,
340
  /* Intel syntax.  */
341
  IntelSyntax,
342
  /* The last bitfield in i386_opcode_modifier.  */
343
  Opcode_Modifier_Max
344
};
345
 
346
typedef struct i386_opcode_modifier
347
{
348
  unsigned int d:1;
349
  unsigned int w:1;
350
  unsigned int s:1;
351
  unsigned int modrm:1;
352
  unsigned int shortform:1;
353
  unsigned int jump:1;
354
  unsigned int jumpdword:1;
355
  unsigned int jumpbyte:1;
356
  unsigned int jumpintersegment:1;
357
  unsigned int floatmf:1;
358
  unsigned int floatr:1;
359
  unsigned int floatd:1;
360
  unsigned int size16:1;
361
  unsigned int size32:1;
362
  unsigned int size64:1;
363
  unsigned int ignoresize:1;
364
  unsigned int defaultsize:1;
365
  unsigned int no_bsuf:1;
366
  unsigned int no_wsuf:1;
367
  unsigned int no_lsuf:1;
368
  unsigned int no_ssuf:1;
369
  unsigned int no_qsuf:1;
370
  unsigned int no_ldsuf:1;
371
  unsigned int fwait:1;
372
  unsigned int isstring:1;
373
  unsigned int islockable:1;
374
  unsigned int regkludge:1;
375
  unsigned int firstxmm0:1;
376
  unsigned int implicit1stxmm0:1;
377
  unsigned int todword:1;
378
  unsigned int toqword:1;
379
  unsigned int addrprefixop0:1;
380
  unsigned int isprefix:1;
381
  unsigned int immext:1;
382
  unsigned int norex64:1;
383
  unsigned int rex64:1;
384
  unsigned int ugh:1;
385
  unsigned int vex:2;
386
  unsigned int vexvvvv:2;
387
  unsigned int vexw:2;
388
  unsigned int vexopcode:3;
389
  unsigned int vexsources:2;
390
  unsigned int veximmext:1;
391
  unsigned int sse2avx:1;
392
  unsigned int noavx:1;
393
  unsigned int oldgcc:1;
394
  unsigned int attmnemonic:1;
395
  unsigned int attsyntax:1;
396
  unsigned int intelsyntax:1;
397
} i386_opcode_modifier;
398
 
399
/* Position of operand_type bits.  */
400
 
401
enum
402
{
403
  /* 8bit register */
404
  Reg8 = 0,
405
  /* 16bit register */
406
  Reg16,
407
  /* 32bit register */
408
  Reg32,
409
  /* 64bit register */
410
  Reg64,
411
  /* Floating pointer stack register */
412
  FloatReg,
413
  /* MMX register */
414
  RegMMX,
415
  /* SSE register */
416
  RegXMM,
417
  /* AVX registers */
418
  RegYMM,
419
  /* Control register */
420
  Control,
421
  /* Debug register */
422
  Debug,
423
  /* Test register */
424
  Test,
425
  /* 2 bit segment register */
426
  SReg2,
427
  /* 3 bit segment register */
428
  SReg3,
429
  /* 1 bit immediate */
430
  Imm1,
431
  /* 8 bit immediate */
432
  Imm8,
433
  /* 8 bit immediate sign extended */
434
  Imm8S,
435
  /* 16 bit immediate */
436
  Imm16,
437
  /* 32 bit immediate */
438
  Imm32,
439
  /* 32 bit immediate sign extended */
440
  Imm32S,
441
  /* 64 bit immediate */
442
  Imm64,
443
  /* 8bit/16bit/32bit displacements are used in different ways,
444
     depending on the instruction.  For jumps, they specify the
445
     size of the PC relative displacement, for instructions with
446
     memory operand, they specify the size of the offset relative
447
     to the base register, and for instructions with memory offset
448
     such as `mov 1234,%al' they specify the size of the offset
449
     relative to the segment base.  */
450
  /* 8 bit displacement */
451
  Disp8,
452
  /* 16 bit displacement */
453
  Disp16,
454
  /* 32 bit displacement */
455
  Disp32,
456
  /* 32 bit signed displacement */
457
  Disp32S,
458
  /* 64 bit displacement */
459
  Disp64,
460
  /* Accumulator %al/%ax/%eax/%rax */
461
  Acc,
462
  /* Floating pointer top stack register %st(0) */
463
  FloatAcc,
464
  /* Register which can be used for base or index in memory operand.  */
465
  BaseIndex,
466
  /* Register to hold in/out port addr = dx */
467
  InOutPortReg,
468
  /* Register to hold shift count = cl */
469
  ShiftCount,
470
  /* Absolute address for jump.  */
471
  JumpAbsolute,
472
  /* String insn operand with fixed es segment */
473
  EsSeg,
474
  /* RegMem is for instructions with a modrm byte where the register
475
     destination operand should be encoded in the mod and regmem fields.
476
     Normally, it will be encoded in the reg field. We add a RegMem
477
     flag to the destination register operand to indicate that it should
478
     be encoded in the regmem field.  */
479
  RegMem,
480
  /* Memory.  */
481
  Mem,
482
  /* BYTE memory. */
483
  Byte,
484
  /* WORD memory. 2 byte */
485
  Word,
486
  /* DWORD memory. 4 byte */
487
  Dword,
488
  /* FWORD memory. 6 byte */
489
  Fword,
490
  /* QWORD memory. 8 byte */
491
  Qword,
492
  /* TBYTE memory. 10 byte */
493
  Tbyte,
494
  /* XMMWORD memory. */
495
  Xmmword,
496
  /* YMMWORD memory. */
497
  Ymmword,
498
  /* Unspecified memory size.  */
499
  Unspecified,
500
  /* Any memory size.  */
501
  Anysize,
502
 
503
  /* Vector 4 bit immediate.  */
504
  Vec_Imm4,
505
 
506
  /* The last bitfield in i386_operand_type.  */
507
  OTMax
508
};
509
 
510
#define OTNumOfUints \
511
  (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
512
#define OTNumOfBits \
513
  (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
514
 
515
/* If you get a compiler error for zero width of the unused field,
516
   comment it out.  */
517
#define OTUnused                (OTMax + 1)
518
 
519
typedef union i386_operand_type
520
{
521
  struct
522
    {
523
      unsigned int reg8:1;
524
      unsigned int reg16:1;
525
      unsigned int reg32:1;
526
      unsigned int reg64:1;
527
      unsigned int floatreg:1;
528
      unsigned int regmmx:1;
529
      unsigned int regxmm:1;
530
      unsigned int regymm:1;
531
      unsigned int control:1;
532
      unsigned int debug:1;
533
      unsigned int test:1;
534
      unsigned int sreg2:1;
535
      unsigned int sreg3:1;
536
      unsigned int imm1:1;
537
      unsigned int imm8:1;
538
      unsigned int imm8s:1;
539
      unsigned int imm16:1;
540
      unsigned int imm32:1;
541
      unsigned int imm32s:1;
542
      unsigned int imm64:1;
543
      unsigned int disp8:1;
544
      unsigned int disp16:1;
545
      unsigned int disp32:1;
546
      unsigned int disp32s:1;
547
      unsigned int disp64:1;
548
      unsigned int acc:1;
549
      unsigned int floatacc:1;
550
      unsigned int baseindex:1;
551
      unsigned int inoutportreg:1;
552
      unsigned int shiftcount:1;
553
      unsigned int jumpabsolute:1;
554
      unsigned int esseg:1;
555
      unsigned int regmem:1;
556
      unsigned int mem:1;
557
      unsigned int byte:1;
558
      unsigned int word:1;
559
      unsigned int dword:1;
560
      unsigned int fword:1;
561
      unsigned int qword:1;
562
      unsigned int tbyte:1;
563
      unsigned int xmmword:1;
564
      unsigned int ymmword:1;
565
      unsigned int unspecified:1;
566
      unsigned int anysize:1;
567
      unsigned int vec_imm4:1;
568
#ifdef OTUnused
569
      unsigned int unused:(OTNumOfBits - OTUnused);
570
#endif
571
    } bitfield;
572
  unsigned int array[OTNumOfUints];
573
} i386_operand_type;
574
 
575
typedef struct insn_template
576
{
577
  /* instruction name sans width suffix ("mov" for movl insns) */
578
  char *name;
579
 
580
  /* how many operands */
581
  unsigned int operands;
582
 
583
  /* base_opcode is the fundamental opcode byte without optional
584
     prefix(es).  */
585
  unsigned int base_opcode;
586
#define Opcode_D        0x2 /* Direction bit:
587
                               set if Reg --> Regmem;
588
                               unset if Regmem --> Reg. */
589
#define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
590
#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
591
 
592
  /* extension_opcode is the 3 bit extension for group <n> insns.
593
     This field is also used to store the 8-bit opcode suffix for the
594
     AMD 3DNow! instructions.
595
     If this template has no extension opcode (the usual case) use None
596
     Instructions */
597
  unsigned int extension_opcode;
598
#define None 0xffff             /* If no extension_opcode is possible.  */
599
 
600
  /* Opcode length.  */
601
  unsigned char opcode_length;
602
 
603
  /* cpu feature flags */
604
  i386_cpu_flags cpu_flags;
605
 
606
  /* the bits in opcode_modifier are used to generate the final opcode from
607
     the base_opcode.  These bits also are used to detect alternate forms of
608
     the same instruction */
609
  i386_opcode_modifier opcode_modifier;
610
 
611
  /* operand_types[i] describes the type of operand i.  This is made
612
     by OR'ing together all of the possible type masks.  (e.g.
613
     'operand_types[i] = Reg|Imm' specifies that operand i can be
614
     either a register or an immediate operand.  */
615
  i386_operand_type operand_types[MAX_OPERANDS];
616
}
617
insn_template;
618
 
619
extern const insn_template i386_optab[];
620
 
621
/* these are for register name --> number & type hash lookup */
622
typedef struct
623
{
624
  char *reg_name;
625
  i386_operand_type reg_type;
626
  unsigned char reg_flags;
627
#define RegRex      0x1  /* Extended register.  */
628
#define RegRex64    0x2  /* Extended 8 bit register.  */
629
  unsigned char reg_num;
630
#define RegRip  ((unsigned char ) ~0)
631
#define RegEip  (RegRip - 1)
632
/* EIZ and RIZ are fake index registers.  */
633
#define RegEiz  (RegEip - 1)
634
#define RegRiz  (RegEiz - 1)
635
/* FLAT is a fake segment register (Intel mode).  */
636
#define RegFlat     ((unsigned char) ~0)
637
  signed char dw2_regnum[2];
638
#define Dw2Inval (-1)
639
}
640
reg_entry;
641
 
642
/* Entries in i386_regtab.  */
643
#define REGNAM_AL 1
644
#define REGNAM_AX 25
645
#define REGNAM_EAX 41
646
 
647
extern const reg_entry i386_regtab[];
648
extern const unsigned int i386_regtab_size;
649
 
650
typedef struct
651
{
652
  char *seg_name;
653
  unsigned int seg_prefix;
654
}
655
seg_entry;
656
 
657
extern const seg_entry cs;
658
extern const seg_entry ds;
659
extern const seg_entry ss;
660
extern const seg_entry es;
661
extern const seg_entry fs;
662
extern const seg_entry gs;

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