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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [opcodes/] [m32r-opc.c] - Blame information for rev 227

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1 227 jeremybenn
/* Instruction opcode table for m32r.
2
 
3
THIS FILE IS MACHINE GENERATED WITH CGEN.
4
 
5
Copyright 1996-2010 Free Software Foundation, Inc.
6
 
7
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
 
9
   This file is free software; you can redistribute it and/or modify
10
   it under the terms of the GNU General Public License as published by
11
   the Free Software Foundation; either version 3, or (at your option)
12
   any later version.
13
 
14
   It is distributed in the hope that it will be useful, but WITHOUT
15
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17
   License for more details.
18
 
19
   You should have received a copy of the GNU General Public License along
20
   with this program; if not, write to the Free Software Foundation, Inc.,
21
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
 
23
*/
24
 
25
#include "sysdep.h"
26
#include "ansidecl.h"
27
#include "bfd.h"
28
#include "symcat.h"
29
#include "m32r-desc.h"
30
#include "m32r-opc.h"
31
#include "libiberty.h"
32
 
33
/* -- opc.c */
34
unsigned int
35
m32r_cgen_dis_hash (const char * buf ATTRIBUTE_UNUSED, CGEN_INSN_INT value)
36
{
37
  unsigned int x;
38
 
39
  if (value & 0xffff0000) /* 32bit instructions.  */
40
    value = (value >> 16) & 0xffff;
41
 
42
  x = (value >> 8) & 0xf0;
43
  if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50)
44
    return x;
45
 
46
  if (x == 0x70 || x == 0xf0)
47
    return x | ((value >> 8) & 0x0f);
48
 
49
  if (x == 0x30)
50
    return x | ((value & 0x70) >> 4);
51
  else
52
    return x | ((value & 0xf0) >> 4);
53
}
54
 
55
/* -- */
56
/* The hash functions are recorded here to help keep assembler code out of
57
   the disassembler and vice versa.  */
58
 
59
static int asm_hash_insn_p        (const CGEN_INSN *);
60
static unsigned int asm_hash_insn (const char *);
61
static int dis_hash_insn_p        (const CGEN_INSN *);
62
static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
63
 
64
/* Instruction formats.  */
65
 
66
#define F(f) & m32r_cgen_ifld_table[M32R_##f]
67
static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
68
  0, 0, 0x0, { { 0 } }
69
};
70
 
71
static const CGEN_IFMT ifmt_add ATTRIBUTE_UNUSED = {
72
  16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
73
};
74
 
75
static const CGEN_IFMT ifmt_add3 ATTRIBUTE_UNUSED = {
76
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
77
};
78
 
79
static const CGEN_IFMT ifmt_and3 ATTRIBUTE_UNUSED = {
80
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
81
};
82
 
83
static const CGEN_IFMT ifmt_or3 ATTRIBUTE_UNUSED = {
84
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
85
};
86
 
87
static const CGEN_IFMT ifmt_addi ATTRIBUTE_UNUSED = {
88
  16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } }
89
};
90
 
91
static const CGEN_IFMT ifmt_addv3 ATTRIBUTE_UNUSED = {
92
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
93
};
94
 
95
static const CGEN_IFMT ifmt_bc8 ATTRIBUTE_UNUSED = {
96
  16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
97
};
98
 
99
static const CGEN_IFMT ifmt_bc24 ATTRIBUTE_UNUSED = {
100
  32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
101
};
102
 
103
static const CGEN_IFMT ifmt_beq ATTRIBUTE_UNUSED = {
104
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } }
105
};
106
 
107
static const CGEN_IFMT ifmt_beqz ATTRIBUTE_UNUSED = {
108
  32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } }
109
};
110
 
111
static const CGEN_IFMT ifmt_cmp ATTRIBUTE_UNUSED = {
112
  16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
113
};
114
 
115
static const CGEN_IFMT ifmt_cmpi ATTRIBUTE_UNUSED = {
116
  32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
117
};
118
 
119
static const CGEN_IFMT ifmt_cmpz ATTRIBUTE_UNUSED = {
120
  16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
121
};
122
 
123
static const CGEN_IFMT ifmt_div ATTRIBUTE_UNUSED = {
124
  32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
125
};
126
 
127
static const CGEN_IFMT ifmt_jc ATTRIBUTE_UNUSED = {
128
  16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
129
};
130
 
131
static const CGEN_IFMT ifmt_ld24 ATTRIBUTE_UNUSED = {
132
  32, 32, 0xf0000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM24) }, { 0 } }
133
};
134
 
135
static const CGEN_IFMT ifmt_ldi16 ATTRIBUTE_UNUSED = {
136
  32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
137
};
138
 
139
static const CGEN_IFMT ifmt_machi_a ATTRIBUTE_UNUSED = {
140
  16, 16, 0xf070, { { F (F_OP1) }, { F (F_R1) }, { F (F_ACC) }, { F (F_OP23) }, { F (F_R2) }, { 0 } }
141
};
142
 
143
static const CGEN_IFMT ifmt_mvfachi ATTRIBUTE_UNUSED = {
144
  16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
145
};
146
 
147
static const CGEN_IFMT ifmt_mvfachi_a ATTRIBUTE_UNUSED = {
148
  16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } }
149
};
150
 
151
static const CGEN_IFMT ifmt_mvfc ATTRIBUTE_UNUSED = {
152
  16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
153
};
154
 
155
static const CGEN_IFMT ifmt_mvtachi ATTRIBUTE_UNUSED = {
156
  16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
157
};
158
 
159
static const CGEN_IFMT ifmt_mvtachi_a ATTRIBUTE_UNUSED = {
160
  16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } }
161
};
162
 
163
static const CGEN_IFMT ifmt_mvtc ATTRIBUTE_UNUSED = {
164
  16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
165
};
166
 
167
static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = {
168
  16, 16, 0xffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
169
};
170
 
171
static const CGEN_IFMT ifmt_rac_dsi ATTRIBUTE_UNUSED = {
172
  16, 16, 0xf3f2, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
173
};
174
 
175
static const CGEN_IFMT ifmt_seth ATTRIBUTE_UNUSED = {
176
  32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_HI16) }, { 0 } }
177
};
178
 
179
static const CGEN_IFMT ifmt_slli ATTRIBUTE_UNUSED = {
180
  16, 16, 0xf0e0, { { F (F_OP1) }, { F (F_R1) }, { F (F_SHIFT_OP2) }, { F (F_UIMM5) }, { 0 } }
181
};
182
 
183
static const CGEN_IFMT ifmt_st_d ATTRIBUTE_UNUSED = {
184
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
185
};
186
 
187
static const CGEN_IFMT ifmt_trap ATTRIBUTE_UNUSED = {
188
  16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_UIMM4) }, { 0 } }
189
};
190
 
191
static const CGEN_IFMT ifmt_satb ATTRIBUTE_UNUSED = {
192
  32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
193
};
194
 
195
static const CGEN_IFMT ifmt_clrpsw ATTRIBUTE_UNUSED = {
196
  16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM8) }, { 0 } }
197
};
198
 
199
static const CGEN_IFMT ifmt_bset ATTRIBUTE_UNUSED = {
200
  32, 32, 0xf8f00000, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
201
};
202
 
203
static const CGEN_IFMT ifmt_btst ATTRIBUTE_UNUSED = {
204
  16, 16, 0xf8f0, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
205
};
206
 
207
#undef F
208
 
209
#define A(a) (1 << CGEN_INSN_##a)
210
#define OPERAND(op) M32R_OPERAND_##op
211
#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
212
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
213
 
214
/* The instruction table.  */
215
 
216
static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
217
{
218
  /* Special null first entry.
219
     A `num' value of zero is thus invalid.
220
     Also, the special `invalid' insn resides here.  */
221
  { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
222
/* add $dr,$sr */
223
  {
224
    { 0, 0, 0, 0 },
225
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
226
    & ifmt_add, { 0xa0 }
227
  },
228
/* add3 $dr,$sr,$hash$slo16 */
229
  {
230
    { 0, 0, 0, 0 },
231
    { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
232
    & ifmt_add3, { 0x80a00000 }
233
  },
234
/* and $dr,$sr */
235
  {
236
    { 0, 0, 0, 0 },
237
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
238
    & ifmt_add, { 0xc0 }
239
  },
240
/* and3 $dr,$sr,$uimm16 */
241
  {
242
    { 0, 0, 0, 0 },
243
    { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
244
    & ifmt_and3, { 0x80c00000 }
245
  },
246
/* or $dr,$sr */
247
  {
248
    { 0, 0, 0, 0 },
249
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
250
    & ifmt_add, { 0xe0 }
251
  },
252
/* or3 $dr,$sr,$hash$ulo16 */
253
  {
254
    { 0, 0, 0, 0 },
255
    { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
256
    & ifmt_or3, { 0x80e00000 }
257
  },
258
/* xor $dr,$sr */
259
  {
260
    { 0, 0, 0, 0 },
261
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
262
    & ifmt_add, { 0xd0 }
263
  },
264
/* xor3 $dr,$sr,$uimm16 */
265
  {
266
    { 0, 0, 0, 0 },
267
    { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
268
    & ifmt_and3, { 0x80d00000 }
269
  },
270
/* addi $dr,$simm8 */
271
  {
272
    { 0, 0, 0, 0 },
273
    { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
274
    & ifmt_addi, { 0x4000 }
275
  },
276
/* addv $dr,$sr */
277
  {
278
    { 0, 0, 0, 0 },
279
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
280
    & ifmt_add, { 0x80 }
281
  },
282
/* addv3 $dr,$sr,$simm16 */
283
  {
284
    { 0, 0, 0, 0 },
285
    { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
286
    & ifmt_addv3, { 0x80800000 }
287
  },
288
/* addx $dr,$sr */
289
  {
290
    { 0, 0, 0, 0 },
291
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
292
    & ifmt_add, { 0x90 }
293
  },
294
/* bc.s $disp8 */
295
  {
296
    { 0, 0, 0, 0 },
297
    { { MNEM, ' ', OP (DISP8), 0 } },
298
    & ifmt_bc8, { 0x7c00 }
299
  },
300
/* bc.l $disp24 */
301
  {
302
    { 0, 0, 0, 0 },
303
    { { MNEM, ' ', OP (DISP24), 0 } },
304
    & ifmt_bc24, { 0xfc000000 }
305
  },
306
/* beq $src1,$src2,$disp16 */
307
  {
308
    { 0, 0, 0, 0 },
309
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
310
    & ifmt_beq, { 0xb0000000 }
311
  },
312
/* beqz $src2,$disp16 */
313
  {
314
    { 0, 0, 0, 0 },
315
    { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
316
    & ifmt_beqz, { 0xb0800000 }
317
  },
318
/* bgez $src2,$disp16 */
319
  {
320
    { 0, 0, 0, 0 },
321
    { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
322
    & ifmt_beqz, { 0xb0b00000 }
323
  },
324
/* bgtz $src2,$disp16 */
325
  {
326
    { 0, 0, 0, 0 },
327
    { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
328
    & ifmt_beqz, { 0xb0d00000 }
329
  },
330
/* blez $src2,$disp16 */
331
  {
332
    { 0, 0, 0, 0 },
333
    { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
334
    & ifmt_beqz, { 0xb0c00000 }
335
  },
336
/* bltz $src2,$disp16 */
337
  {
338
    { 0, 0, 0, 0 },
339
    { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
340
    & ifmt_beqz, { 0xb0a00000 }
341
  },
342
/* bnez $src2,$disp16 */
343
  {
344
    { 0, 0, 0, 0 },
345
    { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
346
    & ifmt_beqz, { 0xb0900000 }
347
  },
348
/* bl.s $disp8 */
349
  {
350
    { 0, 0, 0, 0 },
351
    { { MNEM, ' ', OP (DISP8), 0 } },
352
    & ifmt_bc8, { 0x7e00 }
353
  },
354
/* bl.l $disp24 */
355
  {
356
    { 0, 0, 0, 0 },
357
    { { MNEM, ' ', OP (DISP24), 0 } },
358
    & ifmt_bc24, { 0xfe000000 }
359
  },
360
/* bcl.s $disp8 */
361
  {
362
    { 0, 0, 0, 0 },
363
    { { MNEM, ' ', OP (DISP8), 0 } },
364
    & ifmt_bc8, { 0x7800 }
365
  },
366
/* bcl.l $disp24 */
367
  {
368
    { 0, 0, 0, 0 },
369
    { { MNEM, ' ', OP (DISP24), 0 } },
370
    & ifmt_bc24, { 0xf8000000 }
371
  },
372
/* bnc.s $disp8 */
373
  {
374
    { 0, 0, 0, 0 },
375
    { { MNEM, ' ', OP (DISP8), 0 } },
376
    & ifmt_bc8, { 0x7d00 }
377
  },
378
/* bnc.l $disp24 */
379
  {
380
    { 0, 0, 0, 0 },
381
    { { MNEM, ' ', OP (DISP24), 0 } },
382
    & ifmt_bc24, { 0xfd000000 }
383
  },
384
/* bne $src1,$src2,$disp16 */
385
  {
386
    { 0, 0, 0, 0 },
387
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
388
    & ifmt_beq, { 0xb0100000 }
389
  },
390
/* bra.s $disp8 */
391
  {
392
    { 0, 0, 0, 0 },
393
    { { MNEM, ' ', OP (DISP8), 0 } },
394
    & ifmt_bc8, { 0x7f00 }
395
  },
396
/* bra.l $disp24 */
397
  {
398
    { 0, 0, 0, 0 },
399
    { { MNEM, ' ', OP (DISP24), 0 } },
400
    & ifmt_bc24, { 0xff000000 }
401
  },
402
/* bncl.s $disp8 */
403
  {
404
    { 0, 0, 0, 0 },
405
    { { MNEM, ' ', OP (DISP8), 0 } },
406
    & ifmt_bc8, { 0x7900 }
407
  },
408
/* bncl.l $disp24 */
409
  {
410
    { 0, 0, 0, 0 },
411
    { { MNEM, ' ', OP (DISP24), 0 } },
412
    & ifmt_bc24, { 0xf9000000 }
413
  },
414
/* cmp $src1,$src2 */
415
  {
416
    { 0, 0, 0, 0 },
417
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
418
    & ifmt_cmp, { 0x40 }
419
  },
420
/* cmpi $src2,$simm16 */
421
  {
422
    { 0, 0, 0, 0 },
423
    { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
424
    & ifmt_cmpi, { 0x80400000 }
425
  },
426
/* cmpu $src1,$src2 */
427
  {
428
    { 0, 0, 0, 0 },
429
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
430
    & ifmt_cmp, { 0x50 }
431
  },
432
/* cmpui $src2,$simm16 */
433
  {
434
    { 0, 0, 0, 0 },
435
    { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
436
    & ifmt_cmpi, { 0x80500000 }
437
  },
438
/* cmpeq $src1,$src2 */
439
  {
440
    { 0, 0, 0, 0 },
441
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
442
    & ifmt_cmp, { 0x60 }
443
  },
444
/* cmpz $src2 */
445
  {
446
    { 0, 0, 0, 0 },
447
    { { MNEM, ' ', OP (SRC2), 0 } },
448
    & ifmt_cmpz, { 0x70 }
449
  },
450
/* div $dr,$sr */
451
  {
452
    { 0, 0, 0, 0 },
453
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
454
    & ifmt_div, { 0x90000000 }
455
  },
456
/* divu $dr,$sr */
457
  {
458
    { 0, 0, 0, 0 },
459
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
460
    & ifmt_div, { 0x90100000 }
461
  },
462
/* rem $dr,$sr */
463
  {
464
    { 0, 0, 0, 0 },
465
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
466
    & ifmt_div, { 0x90200000 }
467
  },
468
/* remu $dr,$sr */
469
  {
470
    { 0, 0, 0, 0 },
471
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
472
    & ifmt_div, { 0x90300000 }
473
  },
474
/* remh $dr,$sr */
475
  {
476
    { 0, 0, 0, 0 },
477
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
478
    & ifmt_div, { 0x90200010 }
479
  },
480
/* remuh $dr,$sr */
481
  {
482
    { 0, 0, 0, 0 },
483
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
484
    & ifmt_div, { 0x90300010 }
485
  },
486
/* remb $dr,$sr */
487
  {
488
    { 0, 0, 0, 0 },
489
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
490
    & ifmt_div, { 0x90200018 }
491
  },
492
/* remub $dr,$sr */
493
  {
494
    { 0, 0, 0, 0 },
495
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
496
    & ifmt_div, { 0x90300018 }
497
  },
498
/* divuh $dr,$sr */
499
  {
500
    { 0, 0, 0, 0 },
501
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
502
    & ifmt_div, { 0x90100010 }
503
  },
504
/* divb $dr,$sr */
505
  {
506
    { 0, 0, 0, 0 },
507
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
508
    & ifmt_div, { 0x90000018 }
509
  },
510
/* divub $dr,$sr */
511
  {
512
    { 0, 0, 0, 0 },
513
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
514
    & ifmt_div, { 0x90100018 }
515
  },
516
/* divh $dr,$sr */
517
  {
518
    { 0, 0, 0, 0 },
519
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
520
    & ifmt_div, { 0x90000010 }
521
  },
522
/* jc $sr */
523
  {
524
    { 0, 0, 0, 0 },
525
    { { MNEM, ' ', OP (SR), 0 } },
526
    & ifmt_jc, { 0x1cc0 }
527
  },
528
/* jnc $sr */
529
  {
530
    { 0, 0, 0, 0 },
531
    { { MNEM, ' ', OP (SR), 0 } },
532
    & ifmt_jc, { 0x1dc0 }
533
  },
534
/* jl $sr */
535
  {
536
    { 0, 0, 0, 0 },
537
    { { MNEM, ' ', OP (SR), 0 } },
538
    & ifmt_jc, { 0x1ec0 }
539
  },
540
/* jmp $sr */
541
  {
542
    { 0, 0, 0, 0 },
543
    { { MNEM, ' ', OP (SR), 0 } },
544
    & ifmt_jc, { 0x1fc0 }
545
  },
546
/* ld $dr,@$sr */
547
  {
548
    { 0, 0, 0, 0 },
549
    { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
550
    & ifmt_add, { 0x20c0 }
551
  },
552
/* ld $dr,@($slo16,$sr) */
553
  {
554
    { 0, 0, 0, 0 },
555
    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
556
    & ifmt_add3, { 0xa0c00000 }
557
  },
558
/* ldb $dr,@$sr */
559
  {
560
    { 0, 0, 0, 0 },
561
    { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
562
    & ifmt_add, { 0x2080 }
563
  },
564
/* ldb $dr,@($slo16,$sr) */
565
  {
566
    { 0, 0, 0, 0 },
567
    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
568
    & ifmt_add3, { 0xa0800000 }
569
  },
570
/* ldh $dr,@$sr */
571
  {
572
    { 0, 0, 0, 0 },
573
    { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
574
    & ifmt_add, { 0x20a0 }
575
  },
576
/* ldh $dr,@($slo16,$sr) */
577
  {
578
    { 0, 0, 0, 0 },
579
    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
580
    & ifmt_add3, { 0xa0a00000 }
581
  },
582
/* ldub $dr,@$sr */
583
  {
584
    { 0, 0, 0, 0 },
585
    { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
586
    & ifmt_add, { 0x2090 }
587
  },
588
/* ldub $dr,@($slo16,$sr) */
589
  {
590
    { 0, 0, 0, 0 },
591
    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
592
    & ifmt_add3, { 0xa0900000 }
593
  },
594
/* lduh $dr,@$sr */
595
  {
596
    { 0, 0, 0, 0 },
597
    { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
598
    & ifmt_add, { 0x20b0 }
599
  },
600
/* lduh $dr,@($slo16,$sr) */
601
  {
602
    { 0, 0, 0, 0 },
603
    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
604
    & ifmt_add3, { 0xa0b00000 }
605
  },
606
/* ld $dr,@$sr+ */
607
  {
608
    { 0, 0, 0, 0 },
609
    { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
610
    & ifmt_add, { 0x20e0 }
611
  },
612
/* ld24 $dr,$uimm24 */
613
  {
614
    { 0, 0, 0, 0 },
615
    { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
616
    & ifmt_ld24, { 0xe0000000 }
617
  },
618
/* ldi8 $dr,$simm8 */
619
  {
620
    { 0, 0, 0, 0 },
621
    { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
622
    & ifmt_addi, { 0x6000 }
623
  },
624
/* ldi16 $dr,$hash$slo16 */
625
  {
626
    { 0, 0, 0, 0 },
627
    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
628
    & ifmt_ldi16, { 0x90f00000 }
629
  },
630
/* lock $dr,@$sr */
631
  {
632
    { 0, 0, 0, 0 },
633
    { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
634
    & ifmt_add, { 0x20d0 }
635
  },
636
/* machi $src1,$src2 */
637
  {
638
    { 0, 0, 0, 0 },
639
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
640
    & ifmt_cmp, { 0x3040 }
641
  },
642
/* machi $src1,$src2,$acc */
643
  {
644
    { 0, 0, 0, 0 },
645
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
646
    & ifmt_machi_a, { 0x3040 }
647
  },
648
/* maclo $src1,$src2 */
649
  {
650
    { 0, 0, 0, 0 },
651
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
652
    & ifmt_cmp, { 0x3050 }
653
  },
654
/* maclo $src1,$src2,$acc */
655
  {
656
    { 0, 0, 0, 0 },
657
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
658
    & ifmt_machi_a, { 0x3050 }
659
  },
660
/* macwhi $src1,$src2 */
661
  {
662
    { 0, 0, 0, 0 },
663
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
664
    & ifmt_cmp, { 0x3060 }
665
  },
666
/* macwhi $src1,$src2,$acc */
667
  {
668
    { 0, 0, 0, 0 },
669
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
670
    & ifmt_machi_a, { 0x3060 }
671
  },
672
/* macwlo $src1,$src2 */
673
  {
674
    { 0, 0, 0, 0 },
675
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
676
    & ifmt_cmp, { 0x3070 }
677
  },
678
/* macwlo $src1,$src2,$acc */
679
  {
680
    { 0, 0, 0, 0 },
681
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
682
    & ifmt_machi_a, { 0x3070 }
683
  },
684
/* mul $dr,$sr */
685
  {
686
    { 0, 0, 0, 0 },
687
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
688
    & ifmt_add, { 0x1060 }
689
  },
690
/* mulhi $src1,$src2 */
691
  {
692
    { 0, 0, 0, 0 },
693
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
694
    & ifmt_cmp, { 0x3000 }
695
  },
696
/* mulhi $src1,$src2,$acc */
697
  {
698
    { 0, 0, 0, 0 },
699
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
700
    & ifmt_machi_a, { 0x3000 }
701
  },
702
/* mullo $src1,$src2 */
703
  {
704
    { 0, 0, 0, 0 },
705
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
706
    & ifmt_cmp, { 0x3010 }
707
  },
708
/* mullo $src1,$src2,$acc */
709
  {
710
    { 0, 0, 0, 0 },
711
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
712
    & ifmt_machi_a, { 0x3010 }
713
  },
714
/* mulwhi $src1,$src2 */
715
  {
716
    { 0, 0, 0, 0 },
717
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
718
    & ifmt_cmp, { 0x3020 }
719
  },
720
/* mulwhi $src1,$src2,$acc */
721
  {
722
    { 0, 0, 0, 0 },
723
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
724
    & ifmt_machi_a, { 0x3020 }
725
  },
726
/* mulwlo $src1,$src2 */
727
  {
728
    { 0, 0, 0, 0 },
729
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
730
    & ifmt_cmp, { 0x3030 }
731
  },
732
/* mulwlo $src1,$src2,$acc */
733
  {
734
    { 0, 0, 0, 0 },
735
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
736
    & ifmt_machi_a, { 0x3030 }
737
  },
738
/* mv $dr,$sr */
739
  {
740
    { 0, 0, 0, 0 },
741
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
742
    & ifmt_add, { 0x1080 }
743
  },
744
/* mvfachi $dr */
745
  {
746
    { 0, 0, 0, 0 },
747
    { { MNEM, ' ', OP (DR), 0 } },
748
    & ifmt_mvfachi, { 0x50f0 }
749
  },
750
/* mvfachi $dr,$accs */
751
  {
752
    { 0, 0, 0, 0 },
753
    { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
754
    & ifmt_mvfachi_a, { 0x50f0 }
755
  },
756
/* mvfaclo $dr */
757
  {
758
    { 0, 0, 0, 0 },
759
    { { MNEM, ' ', OP (DR), 0 } },
760
    & ifmt_mvfachi, { 0x50f1 }
761
  },
762
/* mvfaclo $dr,$accs */
763
  {
764
    { 0, 0, 0, 0 },
765
    { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
766
    & ifmt_mvfachi_a, { 0x50f1 }
767
  },
768
/* mvfacmi $dr */
769
  {
770
    { 0, 0, 0, 0 },
771
    { { MNEM, ' ', OP (DR), 0 } },
772
    & ifmt_mvfachi, { 0x50f2 }
773
  },
774
/* mvfacmi $dr,$accs */
775
  {
776
    { 0, 0, 0, 0 },
777
    { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
778
    & ifmt_mvfachi_a, { 0x50f2 }
779
  },
780
/* mvfc $dr,$scr */
781
  {
782
    { 0, 0, 0, 0 },
783
    { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
784
    & ifmt_mvfc, { 0x1090 }
785
  },
786
/* mvtachi $src1 */
787
  {
788
    { 0, 0, 0, 0 },
789
    { { MNEM, ' ', OP (SRC1), 0 } },
790
    & ifmt_mvtachi, { 0x5070 }
791
  },
792
/* mvtachi $src1,$accs */
793
  {
794
    { 0, 0, 0, 0 },
795
    { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
796
    & ifmt_mvtachi_a, { 0x5070 }
797
  },
798
/* mvtaclo $src1 */
799
  {
800
    { 0, 0, 0, 0 },
801
    { { MNEM, ' ', OP (SRC1), 0 } },
802
    & ifmt_mvtachi, { 0x5071 }
803
  },
804
/* mvtaclo $src1,$accs */
805
  {
806
    { 0, 0, 0, 0 },
807
    { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
808
    & ifmt_mvtachi_a, { 0x5071 }
809
  },
810
/* mvtc $sr,$dcr */
811
  {
812
    { 0, 0, 0, 0 },
813
    { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
814
    & ifmt_mvtc, { 0x10a0 }
815
  },
816
/* neg $dr,$sr */
817
  {
818
    { 0, 0, 0, 0 },
819
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
820
    & ifmt_add, { 0x30 }
821
  },
822
/* nop */
823
  {
824
    { 0, 0, 0, 0 },
825
    { { MNEM, 0 } },
826
    & ifmt_nop, { 0x7000 }
827
  },
828
/* not $dr,$sr */
829
  {
830
    { 0, 0, 0, 0 },
831
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
832
    & ifmt_add, { 0xb0 }
833
  },
834
/* rac */
835
  {
836
    { 0, 0, 0, 0 },
837
    { { MNEM, 0 } },
838
    & ifmt_nop, { 0x5090 }
839
  },
840
/* rac $accd,$accs,$imm1 */
841
  {
842
    { 0, 0, 0, 0 },
843
    { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
844
    & ifmt_rac_dsi, { 0x5090 }
845
  },
846
/* rach */
847
  {
848
    { 0, 0, 0, 0 },
849
    { { MNEM, 0 } },
850
    & ifmt_nop, { 0x5080 }
851
  },
852
/* rach $accd,$accs,$imm1 */
853
  {
854
    { 0, 0, 0, 0 },
855
    { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
856
    & ifmt_rac_dsi, { 0x5080 }
857
  },
858
/* rte */
859
  {
860
    { 0, 0, 0, 0 },
861
    { { MNEM, 0 } },
862
    & ifmt_nop, { 0x10d6 }
863
  },
864
/* seth $dr,$hash$hi16 */
865
  {
866
    { 0, 0, 0, 0 },
867
    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
868
    & ifmt_seth, { 0xd0c00000 }
869
  },
870
/* sll $dr,$sr */
871
  {
872
    { 0, 0, 0, 0 },
873
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
874
    & ifmt_add, { 0x1040 }
875
  },
876
/* sll3 $dr,$sr,$simm16 */
877
  {
878
    { 0, 0, 0, 0 },
879
    { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
880
    & ifmt_addv3, { 0x90c00000 }
881
  },
882
/* slli $dr,$uimm5 */
883
  {
884
    { 0, 0, 0, 0 },
885
    { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
886
    & ifmt_slli, { 0x5040 }
887
  },
888
/* sra $dr,$sr */
889
  {
890
    { 0, 0, 0, 0 },
891
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
892
    & ifmt_add, { 0x1020 }
893
  },
894
/* sra3 $dr,$sr,$simm16 */
895
  {
896
    { 0, 0, 0, 0 },
897
    { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
898
    & ifmt_addv3, { 0x90a00000 }
899
  },
900
/* srai $dr,$uimm5 */
901
  {
902
    { 0, 0, 0, 0 },
903
    { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
904
    & ifmt_slli, { 0x5020 }
905
  },
906
/* srl $dr,$sr */
907
  {
908
    { 0, 0, 0, 0 },
909
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
910
    & ifmt_add, { 0x1000 }
911
  },
912
/* srl3 $dr,$sr,$simm16 */
913
  {
914
    { 0, 0, 0, 0 },
915
    { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
916
    & ifmt_addv3, { 0x90800000 }
917
  },
918
/* srli $dr,$uimm5 */
919
  {
920
    { 0, 0, 0, 0 },
921
    { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
922
    & ifmt_slli, { 0x5000 }
923
  },
924
/* st $src1,@$src2 */
925
  {
926
    { 0, 0, 0, 0 },
927
    { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
928
    & ifmt_cmp, { 0x2040 }
929
  },
930
/* st $src1,@($slo16,$src2) */
931
  {
932
    { 0, 0, 0, 0 },
933
    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
934
    & ifmt_st_d, { 0xa0400000 }
935
  },
936
/* stb $src1,@$src2 */
937
  {
938
    { 0, 0, 0, 0 },
939
    { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
940
    & ifmt_cmp, { 0x2000 }
941
  },
942
/* stb $src1,@($slo16,$src2) */
943
  {
944
    { 0, 0, 0, 0 },
945
    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
946
    & ifmt_st_d, { 0xa0000000 }
947
  },
948
/* sth $src1,@$src2 */
949
  {
950
    { 0, 0, 0, 0 },
951
    { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
952
    & ifmt_cmp, { 0x2020 }
953
  },
954
/* sth $src1,@($slo16,$src2) */
955
  {
956
    { 0, 0, 0, 0 },
957
    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
958
    & ifmt_st_d, { 0xa0200000 }
959
  },
960
/* st $src1,@+$src2 */
961
  {
962
    { 0, 0, 0, 0 },
963
    { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
964
    & ifmt_cmp, { 0x2060 }
965
  },
966
/* sth $src1,@$src2+ */
967
  {
968
    { 0, 0, 0, 0 },
969
    { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } },
970
    & ifmt_cmp, { 0x2030 }
971
  },
972
/* stb $src1,@$src2+ */
973
  {
974
    { 0, 0, 0, 0 },
975
    { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } },
976
    & ifmt_cmp, { 0x2010 }
977
  },
978
/* st $src1,@-$src2 */
979
  {
980
    { 0, 0, 0, 0 },
981
    { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
982
    & ifmt_cmp, { 0x2070 }
983
  },
984
/* sub $dr,$sr */
985
  {
986
    { 0, 0, 0, 0 },
987
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
988
    & ifmt_add, { 0x20 }
989
  },
990
/* subv $dr,$sr */
991
  {
992
    { 0, 0, 0, 0 },
993
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
994
    & ifmt_add, { 0x0 }
995
  },
996
/* subx $dr,$sr */
997
  {
998
    { 0, 0, 0, 0 },
999
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1000
    & ifmt_add, { 0x10 }
1001
  },
1002
/* trap $uimm4 */
1003
  {
1004
    { 0, 0, 0, 0 },
1005
    { { MNEM, ' ', OP (UIMM4), 0 } },
1006
    & ifmt_trap, { 0x10f0 }
1007
  },
1008
/* unlock $src1,@$src2 */
1009
  {
1010
    { 0, 0, 0, 0 },
1011
    { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
1012
    & ifmt_cmp, { 0x2050 }
1013
  },
1014
/* satb $dr,$sr */
1015
  {
1016
    { 0, 0, 0, 0 },
1017
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1018
    & ifmt_satb, { 0x80600300 }
1019
  },
1020
/* sath $dr,$sr */
1021
  {
1022
    { 0, 0, 0, 0 },
1023
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1024
    & ifmt_satb, { 0x80600200 }
1025
  },
1026
/* sat $dr,$sr */
1027
  {
1028
    { 0, 0, 0, 0 },
1029
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1030
    & ifmt_satb, { 0x80600000 }
1031
  },
1032
/* pcmpbz $src2 */
1033
  {
1034
    { 0, 0, 0, 0 },
1035
    { { MNEM, ' ', OP (SRC2), 0 } },
1036
    & ifmt_cmpz, { 0x370 }
1037
  },
1038
/* sadd */
1039
  {
1040
    { 0, 0, 0, 0 },
1041
    { { MNEM, 0 } },
1042
    & ifmt_nop, { 0x50e4 }
1043
  },
1044
/* macwu1 $src1,$src2 */
1045
  {
1046
    { 0, 0, 0, 0 },
1047
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1048
    & ifmt_cmp, { 0x50b0 }
1049
  },
1050
/* msblo $src1,$src2 */
1051
  {
1052
    { 0, 0, 0, 0 },
1053
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1054
    & ifmt_cmp, { 0x50d0 }
1055
  },
1056
/* mulwu1 $src1,$src2 */
1057
  {
1058
    { 0, 0, 0, 0 },
1059
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1060
    & ifmt_cmp, { 0x50a0 }
1061
  },
1062
/* maclh1 $src1,$src2 */
1063
  {
1064
    { 0, 0, 0, 0 },
1065
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1066
    & ifmt_cmp, { 0x50c0 }
1067
  },
1068
/* sc */
1069
  {
1070
    { 0, 0, 0, 0 },
1071
    { { MNEM, 0 } },
1072
    & ifmt_nop, { 0x7401 }
1073
  },
1074
/* snc */
1075
  {
1076
    { 0, 0, 0, 0 },
1077
    { { MNEM, 0 } },
1078
    & ifmt_nop, { 0x7501 }
1079
  },
1080
/* clrpsw $uimm8 */
1081
  {
1082
    { 0, 0, 0, 0 },
1083
    { { MNEM, ' ', OP (UIMM8), 0 } },
1084
    & ifmt_clrpsw, { 0x7200 }
1085
  },
1086
/* setpsw $uimm8 */
1087
  {
1088
    { 0, 0, 0, 0 },
1089
    { { MNEM, ' ', OP (UIMM8), 0 } },
1090
    & ifmt_clrpsw, { 0x7100 }
1091
  },
1092
/* bset $uimm3,@($slo16,$sr) */
1093
  {
1094
    { 0, 0, 0, 0 },
1095
    { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1096
    & ifmt_bset, { 0xa0600000 }
1097
  },
1098
/* bclr $uimm3,@($slo16,$sr) */
1099
  {
1100
    { 0, 0, 0, 0 },
1101
    { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1102
    & ifmt_bset, { 0xa0700000 }
1103
  },
1104
/* btst $uimm3,$sr */
1105
  {
1106
    { 0, 0, 0, 0 },
1107
    { { MNEM, ' ', OP (UIMM3), ',', OP (SR), 0 } },
1108
    & ifmt_btst, { 0xf0 }
1109
  },
1110
};
1111
 
1112
#undef A
1113
#undef OPERAND
1114
#undef MNEM
1115
#undef OP
1116
 
1117
/* Formats for ALIAS macro-insns.  */
1118
 
1119
#define F(f) & m32r_cgen_ifld_table[M32R_##f]
1120
static const CGEN_IFMT ifmt_bc8r ATTRIBUTE_UNUSED = {
1121
  16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1122
};
1123
 
1124
static const CGEN_IFMT ifmt_bc24r ATTRIBUTE_UNUSED = {
1125
  32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1126
};
1127
 
1128
static const CGEN_IFMT ifmt_bl8r ATTRIBUTE_UNUSED = {
1129
  16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1130
};
1131
 
1132
static const CGEN_IFMT ifmt_bl24r ATTRIBUTE_UNUSED = {
1133
  32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1134
};
1135
 
1136
static const CGEN_IFMT ifmt_bcl8r ATTRIBUTE_UNUSED = {
1137
  16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1138
};
1139
 
1140
static const CGEN_IFMT ifmt_bcl24r ATTRIBUTE_UNUSED = {
1141
  32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1142
};
1143
 
1144
static const CGEN_IFMT ifmt_bnc8r ATTRIBUTE_UNUSED = {
1145
  16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1146
};
1147
 
1148
static const CGEN_IFMT ifmt_bnc24r ATTRIBUTE_UNUSED = {
1149
  32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1150
};
1151
 
1152
static const CGEN_IFMT ifmt_bra8r ATTRIBUTE_UNUSED = {
1153
  16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1154
};
1155
 
1156
static const CGEN_IFMT ifmt_bra24r ATTRIBUTE_UNUSED = {
1157
  32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1158
};
1159
 
1160
static const CGEN_IFMT ifmt_bncl8r ATTRIBUTE_UNUSED = {
1161
  16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1162
};
1163
 
1164
static const CGEN_IFMT ifmt_bncl24r ATTRIBUTE_UNUSED = {
1165
  32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1166
};
1167
 
1168
static const CGEN_IFMT ifmt_ld_2 ATTRIBUTE_UNUSED = {
1169
  16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1170
};
1171
 
1172
static const CGEN_IFMT ifmt_ld_d2 ATTRIBUTE_UNUSED = {
1173
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1174
};
1175
 
1176
static const CGEN_IFMT ifmt_ldb_2 ATTRIBUTE_UNUSED = {
1177
  16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1178
};
1179
 
1180
static const CGEN_IFMT ifmt_ldb_d2 ATTRIBUTE_UNUSED = {
1181
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1182
};
1183
 
1184
static const CGEN_IFMT ifmt_ldh_2 ATTRIBUTE_UNUSED = {
1185
  16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1186
};
1187
 
1188
static const CGEN_IFMT ifmt_ldh_d2 ATTRIBUTE_UNUSED = {
1189
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1190
};
1191
 
1192
static const CGEN_IFMT ifmt_ldub_2 ATTRIBUTE_UNUSED = {
1193
  16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1194
};
1195
 
1196
static const CGEN_IFMT ifmt_ldub_d2 ATTRIBUTE_UNUSED = {
1197
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1198
};
1199
 
1200
static const CGEN_IFMT ifmt_lduh_2 ATTRIBUTE_UNUSED = {
1201
  16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1202
};
1203
 
1204
static const CGEN_IFMT ifmt_lduh_d2 ATTRIBUTE_UNUSED = {
1205
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1206
};
1207
 
1208
static const CGEN_IFMT ifmt_pop ATTRIBUTE_UNUSED = {
1209
  16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
1210
};
1211
 
1212
static const CGEN_IFMT ifmt_ldi8a ATTRIBUTE_UNUSED = {
1213
  16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } }
1214
};
1215
 
1216
static const CGEN_IFMT ifmt_ldi16a ATTRIBUTE_UNUSED = {
1217
  32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_R1) }, { F (F_SIMM16) }, { 0 } }
1218
};
1219
 
1220
static const CGEN_IFMT ifmt_rac_d ATTRIBUTE_UNUSED = {
1221
  16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
1222
};
1223
 
1224
static const CGEN_IFMT ifmt_rac_ds ATTRIBUTE_UNUSED = {
1225
  16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
1226
};
1227
 
1228
static const CGEN_IFMT ifmt_rach_d ATTRIBUTE_UNUSED = {
1229
  16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
1230
};
1231
 
1232
static const CGEN_IFMT ifmt_rach_ds ATTRIBUTE_UNUSED = {
1233
  16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
1234
};
1235
 
1236
static const CGEN_IFMT ifmt_st_2 ATTRIBUTE_UNUSED = {
1237
  16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1238
};
1239
 
1240
static const CGEN_IFMT ifmt_st_d2 ATTRIBUTE_UNUSED = {
1241
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1242
};
1243
 
1244
static const CGEN_IFMT ifmt_stb_2 ATTRIBUTE_UNUSED = {
1245
  16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1246
};
1247
 
1248
static const CGEN_IFMT ifmt_stb_d2 ATTRIBUTE_UNUSED = {
1249
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1250
};
1251
 
1252
static const CGEN_IFMT ifmt_sth_2 ATTRIBUTE_UNUSED = {
1253
  16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1254
};
1255
 
1256
static const CGEN_IFMT ifmt_sth_d2 ATTRIBUTE_UNUSED = {
1257
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1258
};
1259
 
1260
static const CGEN_IFMT ifmt_push ATTRIBUTE_UNUSED = {
1261
  16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1262
};
1263
 
1264
#undef F
1265
 
1266
/* Each non-simple macro entry points to an array of expansion possibilities.  */
1267
 
1268
#define A(a) (1 << CGEN_INSN_##a)
1269
#define OPERAND(op) M32R_OPERAND_##op
1270
#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1271
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1272
 
1273
/* The macro instruction table.  */
1274
 
1275
static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
1276
{
1277
/* bc $disp8 */
1278
  {
1279
    -1, "bc8r", "bc", 16,
1280
    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1281
  },
1282
/* bc $disp24 */
1283
  {
1284
    -1, "bc24r", "bc", 32,
1285
    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1286
  },
1287
/* bl $disp8 */
1288
  {
1289
    -1, "bl8r", "bl", 16,
1290
    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1291
  },
1292
/* bl $disp24 */
1293
  {
1294
    -1, "bl24r", "bl", 32,
1295
    { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1296
  },
1297
/* bcl $disp8 */
1298
  {
1299
    -1, "bcl8r", "bcl", 16,
1300
    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
1301
  },
1302
/* bcl $disp24 */
1303
  {
1304
    -1, "bcl24r", "bcl", 32,
1305
    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
1306
  },
1307
/* bnc $disp8 */
1308
  {
1309
    -1, "bnc8r", "bnc", 16,
1310
    { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1311
  },
1312
/* bnc $disp24 */
1313
  {
1314
    -1, "bnc24r", "bnc", 32,
1315
    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1316
  },
1317
/* bra $disp8 */
1318
  {
1319
    -1, "bra8r", "bra", 16,
1320
    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1321
  },
1322
/* bra $disp24 */
1323
  {
1324
    -1, "bra24r", "bra", 32,
1325
    { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1326
  },
1327
/* bncl $disp8 */
1328
  {
1329
    -1, "bncl8r", "bncl", 16,
1330
    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
1331
  },
1332
/* bncl $disp24 */
1333
  {
1334
    -1, "bncl24r", "bncl", 32,
1335
    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
1336
  },
1337
/* ld $dr,@($sr) */
1338
  {
1339
    -1, "ld-2", "ld", 16,
1340
    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1341
  },
1342
/* ld $dr,@($sr,$slo16) */
1343
  {
1344
    -1, "ld-d2", "ld", 32,
1345
    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1346
  },
1347
/* ldb $dr,@($sr) */
1348
  {
1349
    -1, "ldb-2", "ldb", 16,
1350
    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1351
  },
1352
/* ldb $dr,@($sr,$slo16) */
1353
  {
1354
    -1, "ldb-d2", "ldb", 32,
1355
    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1356
  },
1357
/* ldh $dr,@($sr) */
1358
  {
1359
    -1, "ldh-2", "ldh", 16,
1360
    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1361
  },
1362
/* ldh $dr,@($sr,$slo16) */
1363
  {
1364
    -1, "ldh-d2", "ldh", 32,
1365
    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1366
  },
1367
/* ldub $dr,@($sr) */
1368
  {
1369
    -1, "ldub-2", "ldub", 16,
1370
    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1371
  },
1372
/* ldub $dr,@($sr,$slo16) */
1373
  {
1374
    -1, "ldub-d2", "ldub", 32,
1375
    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1376
  },
1377
/* lduh $dr,@($sr) */
1378
  {
1379
    -1, "lduh-2", "lduh", 16,
1380
    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1381
  },
1382
/* lduh $dr,@($sr,$slo16) */
1383
  {
1384
    -1, "lduh-d2", "lduh", 32,
1385
    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1386
  },
1387
/* pop $dr */
1388
  {
1389
    -1, "pop", "pop", 16,
1390
    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1391
  },
1392
/* ldi $dr,$simm8 */
1393
  {
1394
    -1, "ldi8a", "ldi", 16,
1395
    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1396
  },
1397
/* ldi $dr,$hash$slo16 */
1398
  {
1399
    -1, "ldi16a", "ldi", 32,
1400
    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1401
  },
1402
/* rac $accd */
1403
  {
1404
    -1, "rac-d", "rac", 16,
1405
    { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1406
  },
1407
/* rac $accd,$accs */
1408
  {
1409
    -1, "rac-ds", "rac", 16,
1410
    { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1411
  },
1412
/* rach $accd */
1413
  {
1414
    -1, "rach-d", "rach", 16,
1415
    { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1416
  },
1417
/* rach $accd,$accs */
1418
  {
1419
    -1, "rach-ds", "rach", 16,
1420
    { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1421
  },
1422
/* st $src1,@($src2) */
1423
  {
1424
    -1, "st-2", "st", 16,
1425
    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1426
  },
1427
/* st $src1,@($src2,$slo16) */
1428
  {
1429
    -1, "st-d2", "st", 32,
1430
    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1431
  },
1432
/* stb $src1,@($src2) */
1433
  {
1434
    -1, "stb-2", "stb", 16,
1435
    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1436
  },
1437
/* stb $src1,@($src2,$slo16) */
1438
  {
1439
    -1, "stb-d2", "stb", 32,
1440
    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1441
  },
1442
/* sth $src1,@($src2) */
1443
  {
1444
    -1, "sth-2", "sth", 16,
1445
    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1446
  },
1447
/* sth $src1,@($src2,$slo16) */
1448
  {
1449
    -1, "sth-d2", "sth", 32,
1450
    { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1451
  },
1452
/* push $src1 */
1453
  {
1454
    -1, "push", "push", 16,
1455
    { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1456
  },
1457
};
1458
 
1459
/* The macro instruction opcode table.  */
1460
 
1461
static const CGEN_OPCODE m32r_cgen_macro_insn_opcode_table[] =
1462
{
1463
/* bc $disp8 */
1464
  {
1465
    { 0, 0, 0, 0 },
1466
    { { MNEM, ' ', OP (DISP8), 0 } },
1467
    & ifmt_bc8r, { 0x7c00 }
1468
  },
1469
/* bc $disp24 */
1470
  {
1471
    { 0, 0, 0, 0 },
1472
    { { MNEM, ' ', OP (DISP24), 0 } },
1473
    & ifmt_bc24r, { 0xfc000000 }
1474
  },
1475
/* bl $disp8 */
1476
  {
1477
    { 0, 0, 0, 0 },
1478
    { { MNEM, ' ', OP (DISP8), 0 } },
1479
    & ifmt_bl8r, { 0x7e00 }
1480
  },
1481
/* bl $disp24 */
1482
  {
1483
    { 0, 0, 0, 0 },
1484
    { { MNEM, ' ', OP (DISP24), 0 } },
1485
    & ifmt_bl24r, { 0xfe000000 }
1486
  },
1487
/* bcl $disp8 */
1488
  {
1489
    { 0, 0, 0, 0 },
1490
    { { MNEM, ' ', OP (DISP8), 0 } },
1491
    & ifmt_bcl8r, { 0x7800 }
1492
  },
1493
/* bcl $disp24 */
1494
  {
1495
    { 0, 0, 0, 0 },
1496
    { { MNEM, ' ', OP (DISP24), 0 } },
1497
    & ifmt_bcl24r, { 0xf8000000 }
1498
  },
1499
/* bnc $disp8 */
1500
  {
1501
    { 0, 0, 0, 0 },
1502
    { { MNEM, ' ', OP (DISP8), 0 } },
1503
    & ifmt_bnc8r, { 0x7d00 }
1504
  },
1505
/* bnc $disp24 */
1506
  {
1507
    { 0, 0, 0, 0 },
1508
    { { MNEM, ' ', OP (DISP24), 0 } },
1509
    & ifmt_bnc24r, { 0xfd000000 }
1510
  },
1511
/* bra $disp8 */
1512
  {
1513
    { 0, 0, 0, 0 },
1514
    { { MNEM, ' ', OP (DISP8), 0 } },
1515
    & ifmt_bra8r, { 0x7f00 }
1516
  },
1517
/* bra $disp24 */
1518
  {
1519
    { 0, 0, 0, 0 },
1520
    { { MNEM, ' ', OP (DISP24), 0 } },
1521
    & ifmt_bra24r, { 0xff000000 }
1522
  },
1523
/* bncl $disp8 */
1524
  {
1525
    { 0, 0, 0, 0 },
1526
    { { MNEM, ' ', OP (DISP8), 0 } },
1527
    & ifmt_bncl8r, { 0x7900 }
1528
  },
1529
/* bncl $disp24 */
1530
  {
1531
    { 0, 0, 0, 0 },
1532
    { { MNEM, ' ', OP (DISP24), 0 } },
1533
    & ifmt_bncl24r, { 0xf9000000 }
1534
  },
1535
/* ld $dr,@($sr) */
1536
  {
1537
    { 0, 0, 0, 0 },
1538
    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1539
    & ifmt_ld_2, { 0x20c0 }
1540
  },
1541
/* ld $dr,@($sr,$slo16) */
1542
  {
1543
    { 0, 0, 0, 0 },
1544
    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1545
    & ifmt_ld_d2, { 0xa0c00000 }
1546
  },
1547
/* ldb $dr,@($sr) */
1548
  {
1549
    { 0, 0, 0, 0 },
1550
    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1551
    & ifmt_ldb_2, { 0x2080 }
1552
  },
1553
/* ldb $dr,@($sr,$slo16) */
1554
  {
1555
    { 0, 0, 0, 0 },
1556
    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1557
    & ifmt_ldb_d2, { 0xa0800000 }
1558
  },
1559
/* ldh $dr,@($sr) */
1560
  {
1561
    { 0, 0, 0, 0 },
1562
    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1563
    & ifmt_ldh_2, { 0x20a0 }
1564
  },
1565
/* ldh $dr,@($sr,$slo16) */
1566
  {
1567
    { 0, 0, 0, 0 },
1568
    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1569
    & ifmt_ldh_d2, { 0xa0a00000 }
1570
  },
1571
/* ldub $dr,@($sr) */
1572
  {
1573
    { 0, 0, 0, 0 },
1574
    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1575
    & ifmt_ldub_2, { 0x2090 }
1576
  },
1577
/* ldub $dr,@($sr,$slo16) */
1578
  {
1579
    { 0, 0, 0, 0 },
1580
    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1581
    & ifmt_ldub_d2, { 0xa0900000 }
1582
  },
1583
/* lduh $dr,@($sr) */
1584
  {
1585
    { 0, 0, 0, 0 },
1586
    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1587
    & ifmt_lduh_2, { 0x20b0 }
1588
  },
1589
/* lduh $dr,@($sr,$slo16) */
1590
  {
1591
    { 0, 0, 0, 0 },
1592
    { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1593
    & ifmt_lduh_d2, { 0xa0b00000 }
1594
  },
1595
/* pop $dr */
1596
  {
1597
    { 0, 0, 0, 0 },
1598
    { { MNEM, ' ', OP (DR), 0 } },
1599
    & ifmt_pop, { 0x20ef }
1600
  },
1601
/* ldi $dr,$simm8 */
1602
  {
1603
    { 0, 0, 0, 0 },
1604
    { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
1605
    & ifmt_ldi8a, { 0x6000 }
1606
  },
1607
/* ldi $dr,$hash$slo16 */
1608
  {
1609
    { 0, 0, 0, 0 },
1610
    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
1611
    & ifmt_ldi16a, { 0x90f00000 }
1612
  },
1613
/* rac $accd */
1614
  {
1615
    { 0, 0, 0, 0 },
1616
    { { MNEM, ' ', OP (ACCD), 0 } },
1617
    & ifmt_rac_d, { 0x5090 }
1618
  },
1619
/* rac $accd,$accs */
1620
  {
1621
    { 0, 0, 0, 0 },
1622
    { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
1623
    & ifmt_rac_ds, { 0x5090 }
1624
  },
1625
/* rach $accd */
1626
  {
1627
    { 0, 0, 0, 0 },
1628
    { { MNEM, ' ', OP (ACCD), 0 } },
1629
    & ifmt_rach_d, { 0x5080 }
1630
  },
1631
/* rach $accd,$accs */
1632
  {
1633
    { 0, 0, 0, 0 },
1634
    { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
1635
    & ifmt_rach_ds, { 0x5080 }
1636
  },
1637
/* st $src1,@($src2) */
1638
  {
1639
    { 0, 0, 0, 0 },
1640
    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1641
    & ifmt_st_2, { 0x2040 }
1642
  },
1643
/* st $src1,@($src2,$slo16) */
1644
  {
1645
    { 0, 0, 0, 0 },
1646
    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1647
    & ifmt_st_d2, { 0xa0400000 }
1648
  },
1649
/* stb $src1,@($src2) */
1650
  {
1651
    { 0, 0, 0, 0 },
1652
    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1653
    & ifmt_stb_2, { 0x2000 }
1654
  },
1655
/* stb $src1,@($src2,$slo16) */
1656
  {
1657
    { 0, 0, 0, 0 },
1658
    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1659
    & ifmt_stb_d2, { 0xa0000000 }
1660
  },
1661
/* sth $src1,@($src2) */
1662
  {
1663
    { 0, 0, 0, 0 },
1664
    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1665
    & ifmt_sth_2, { 0x2020 }
1666
  },
1667
/* sth $src1,@($src2,$slo16) */
1668
  {
1669
    { 0, 0, 0, 0 },
1670
    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1671
    & ifmt_sth_d2, { 0xa0200000 }
1672
  },
1673
/* push $src1 */
1674
  {
1675
    { 0, 0, 0, 0 },
1676
    { { MNEM, ' ', OP (SRC1), 0 } },
1677
    & ifmt_push, { 0x207f }
1678
  },
1679
};
1680
 
1681
#undef A
1682
#undef OPERAND
1683
#undef MNEM
1684
#undef OP
1685
 
1686
#ifndef CGEN_ASM_HASH_P
1687
#define CGEN_ASM_HASH_P(insn) 1
1688
#endif
1689
 
1690
#ifndef CGEN_DIS_HASH_P
1691
#define CGEN_DIS_HASH_P(insn) 1
1692
#endif
1693
 
1694
/* Return non-zero if INSN is to be added to the hash table.
1695
   Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
1696
 
1697
static int
1698
asm_hash_insn_p (insn)
1699
     const CGEN_INSN *insn ATTRIBUTE_UNUSED;
1700
{
1701
  return CGEN_ASM_HASH_P (insn);
1702
}
1703
 
1704
static int
1705
dis_hash_insn_p (insn)
1706
     const CGEN_INSN *insn;
1707
{
1708
  /* If building the hash table and the NO-DIS attribute is present,
1709
     ignore.  */
1710
  if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
1711
    return 0;
1712
  return CGEN_DIS_HASH_P (insn);
1713
}
1714
 
1715
#ifndef CGEN_ASM_HASH
1716
#define CGEN_ASM_HASH_SIZE 127
1717
#ifdef CGEN_MNEMONIC_OPERANDS
1718
#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
1719
#else
1720
#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
1721
#endif
1722
#endif
1723
 
1724
/* It doesn't make much sense to provide a default here,
1725
   but while this is under development we do.
1726
   BUFFER is a pointer to the bytes of the insn, target order.
1727
   VALUE is the first base_insn_bitsize bits as an int in host order.  */
1728
 
1729
#ifndef CGEN_DIS_HASH
1730
#define CGEN_DIS_HASH_SIZE 256
1731
#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
1732
#endif
1733
 
1734
/* The result is the hash value of the insn.
1735
   Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
1736
 
1737
static unsigned int
1738
asm_hash_insn (mnem)
1739
     const char * mnem;
1740
{
1741
  return CGEN_ASM_HASH (mnem);
1742
}
1743
 
1744
/* BUF is a pointer to the bytes of the insn, target order.
1745
   VALUE is the first base_insn_bitsize bits as an int in host order.  */
1746
 
1747
static unsigned int
1748
dis_hash_insn (buf, value)
1749
     const char * buf ATTRIBUTE_UNUSED;
1750
     CGEN_INSN_INT value ATTRIBUTE_UNUSED;
1751
{
1752
  return CGEN_DIS_HASH (buf, value);
1753
}
1754
 
1755
/* Set the recorded length of the insn in the CGEN_FIELDS struct.  */
1756
 
1757
static void
1758
set_fields_bitsize (CGEN_FIELDS *fields, int size)
1759
{
1760
  CGEN_FIELDS_BITSIZE (fields) = size;
1761
}
1762
 
1763
/* Function to call before using the operand instance table.
1764
   This plugs the opcode entries and macro instructions into the cpu table.  */
1765
 
1766
void
1767
m32r_cgen_init_opcode_table (CGEN_CPU_DESC cd)
1768
{
1769
  int i;
1770
  int num_macros = (sizeof (m32r_cgen_macro_insn_table) /
1771
                    sizeof (m32r_cgen_macro_insn_table[0]));
1772
  const CGEN_IBASE *ib = & m32r_cgen_macro_insn_table[0];
1773
  const CGEN_OPCODE *oc = & m32r_cgen_macro_insn_opcode_table[0];
1774
  CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
1775
 
1776
  /* This test has been added to avoid a warning generated
1777
     if memset is called with a third argument of value zero.  */
1778
  if (num_macros >= 1)
1779
    memset (insns, 0, num_macros * sizeof (CGEN_INSN));
1780
  for (i = 0; i < num_macros; ++i)
1781
    {
1782
      insns[i].base = &ib[i];
1783
      insns[i].opcode = &oc[i];
1784
      m32r_cgen_build_insn_regex (& insns[i]);
1785
    }
1786
  cd->macro_insn_table.init_entries = insns;
1787
  cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
1788
  cd->macro_insn_table.num_init_entries = num_macros;
1789
 
1790
  oc = & m32r_cgen_insn_opcode_table[0];
1791
  insns = (CGEN_INSN *) cd->insn_table.init_entries;
1792
  for (i = 0; i < MAX_INSNS; ++i)
1793
    {
1794
      insns[i].opcode = &oc[i];
1795
      m32r_cgen_build_insn_regex (& insns[i]);
1796
    }
1797
 
1798
  cd->sizeof_fields = sizeof (CGEN_FIELDS);
1799
  cd->set_fields_bitsize = set_fields_bitsize;
1800
 
1801
  cd->asm_hash_p = asm_hash_insn_p;
1802
  cd->asm_hash = asm_hash_insn;
1803
  cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
1804
 
1805
  cd->dis_hash_p = dis_hash_insn_p;
1806
  cd->dis_hash = dis_hash_insn;
1807
  cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
1808
}

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