URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [common/] [gdbinit.in] - Blame information for rev 300

Go to most recent revision | Details | Compare with Previous | View Log


break sim_io_error
break sim_core_signal
@cgen_breaks@
 
define dump
set sim_debug_dump ()
end
 
document dump
Dump cpu and simulator registers for debugging the simulator.
Requires the simulator to provide function sim_debug_dump.
end

Line No.	Rev	Author	Line
1	227	jeremybenn	`break sim_io_error`
2			`break sim_core_signal`
3			`@cgen_breaks@`
4
5			`define dump`
6			`set sim_debug_dump ()`
7			`end`
8
9			`document dump`
10			`Dump cpu and simulator registers for debugging the simulator.`
11			`Requires the simulator to provide function sim_debug_dump.`
12			`end`

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [common/] [gdbinit.in] - Blame information for rev 300