OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [common/] [sim-base.h] - Blame information for rev 280

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
/* Simulator pseudo baseclass.
2
 
3
   Copyright 1997, 1998, 2003, 2007, 2008, 2009, 2010
4
   Free Software Foundation, Inc.
5
 
6
   Contributed by Cygnus Support.
7
 
8
This file is part of GDB, the GNU debugger.
9
 
10
This program is free software; you can redistribute it and/or modify
11
it under the terms of the GNU General Public License as published by
12
the Free Software Foundation; either version 3 of the License, or
13
(at your option) any later version.
14
 
15
This program is distributed in the hope that it will be useful,
16
but WITHOUT ANY WARRANTY; without even the implied warranty of
17
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18
GNU General Public License for more details.
19
 
20
You should have received a copy of the GNU General Public License
21
along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
22
 
23
 
24
/* Simulator state pseudo baseclass.
25
 
26
   Each simulator is required to have the file ``sim-main.h''.  That
27
   file includes ``sim-basics.h'', defines the base type ``sim_cia''
28
   (the data type that contains complete current instruction address
29
   information), include ``sim-base.h'':
30
 
31
     #include "sim-basics.h"
32
     typedef address_word sim_cia;
33
     /-* If `sim_cia' is not an integral value (e.g. a struct), define
34
         CIA_ADDR to return the integral value.  *-/
35
     /-* #define CIA_ADDR(cia) (...) *-/
36
     #include "sim-base.h"
37
 
38
   finally, two data types `struct _sim_cpu' and `struct sim_state'
39
   are defined:
40
 
41
     struct _sim_cpu {
42
        ... simulator specific members ...
43
        sim_cpu_base base;
44
     };
45
 
46
     struct sim_state {
47
       sim_cpu *cpu[MAX_NR_PROCESSORS];
48
     #if (WITH_SMP)
49
     #define STATE_CPU(sd,n) ((sd)->cpu[n])
50
     #else
51
     #define STATE_CPU(sd,n) ((sd)->cpu[0])
52
     #endif
53
       ... simulator specific members ...
54
       sim_state_base base;
55
     };
56
 
57
   Note that `base' appears last.  This makes `base.magic' appear last
58
   in the entire struct and helps catch miscompilation errors. */
59
 
60
 
61
#ifndef SIM_BASE_H
62
#define SIM_BASE_H
63
 
64
/* Pre-declare certain types. */
65
 
66
/* typedef <target-dependant> sim_cia; */
67
#ifndef NULL_CIA
68
#define NULL_CIA ((sim_cia) 0)
69
#endif
70
/* Return the current instruction address as a number.
71
   Some targets treat the current instruction address as a struct
72
   (e.g. for delay slot handling).  */
73
#ifndef CIA_ADDR
74
#define CIA_ADDR(cia) (cia)
75
#endif
76
#ifndef INVALID_INSTRUCTION_ADDRESS
77
#define INVALID_INSTRUCTION_ADDRESS ((address_word)0 - 1)
78
#endif
79
 
80
typedef struct _sim_cpu sim_cpu;
81
 
82
#include "sim-module.h"
83
 
84
#include "sim-trace.h"
85
#include "sim-core.h"
86
#include "sim-events.h"
87
#include "sim-profile.h"
88
#ifdef SIM_HAVE_MODEL
89
#include "sim-model.h"
90
#endif
91
#include "sim-io.h"
92
#include "sim-engine.h"
93
#include "sim-watch.h"
94
#include "sim-memopt.h"
95
#include "sim-cpu.h"
96
 
97
/* Global pointer to current state while sim_resume is running.
98
   On a machine with lots of registers, it might be possible to reserve
99
   one of them for current_state.  However on a machine with few registers
100
   current_state can't permanently live in one and indirecting through it
101
   will be slower [in which case one can have sim_resume set globals from
102
   current_state for faster access].
103
   If CURRENT_STATE_REG is defined, it means current_state is living in
104
   a global register.  */
105
 
106
 
107
#ifdef CURRENT_STATE_REG
108
/* FIXME: wip */
109
#else
110
extern struct sim_state *current_state;
111
#endif
112
 
113
 
114
/* The simulator may provide different (and faster) definition.  */
115
#ifndef CURRENT_STATE
116
#define CURRENT_STATE current_state
117
#endif
118
 
119
 
120
typedef struct {
121
 
122
  /* Simulator's argv[0].  */
123
  const char *my_name;
124
#define STATE_MY_NAME(sd) ((sd)->base.my_name)
125
 
126
  /* Who opened the simulator.  */
127
  SIM_OPEN_KIND open_kind;
128
#define STATE_OPEN_KIND(sd) ((sd)->base.open_kind)
129
 
130
  /* The host callbacks.  */
131
  struct host_callback_struct *callback;
132
#define STATE_CALLBACK(sd) ((sd)->base.callback)
133
 
134
  /* The type of simulation environment (user/operating).  */
135
  enum sim_environment environment;
136
#define STATE_ENVIRONMENT(sd) ((sd)->base.environment)
137
 
138
#if 0 /* FIXME: Not ready yet.  */
139
  /* Stuff defined in sim-config.h.  */
140
  struct sim_config config;
141
#define STATE_CONFIG(sd) ((sd)->base.config)
142
#endif
143
 
144
  /* List of installed module `init' handlers.  */
145
  struct module_list *modules;
146
#define STATE_MODULES(sd) ((sd)->base.modules)
147
 
148
  /* Supported options.  */
149
  struct option_list *options;
150
#define STATE_OPTIONS(sd) ((sd)->base.options)
151
 
152
  /* Non-zero if -v specified.  */
153
  int verbose_p;
154
#define STATE_VERBOSE_P(sd) ((sd)->base.verbose_p)
155
 
156
  /* Non cpu-specific trace data.  See sim-trace.h.  */
157
  TRACE_DATA trace_data;
158
#define STATE_TRACE_DATA(sd) (& (sd)->base.trace_data)
159
 
160
  /* If non NULL, the BFD architecture specified on the command line */
161
  const struct bfd_arch_info *architecture;
162
#define STATE_ARCHITECTURE(sd) ((sd)->base.architecture)
163
 
164
  /* If non NULL, the bfd target specified on the command line */
165
  const char *target;
166
#define STATE_TARGET(sd) ((sd)->base.target)
167
 
168
  /* In standalone simulator, this is the program's arguments passed
169
     on the command line.  */
170
  char **prog_argv;
171
#define STATE_PROG_ARGV(sd) ((sd)->base.prog_argv)
172
 
173
  /* The program's bfd.  */
174
  struct bfd *prog_bfd;
175
#define STATE_PROG_BFD(sd) ((sd)->base.prog_bfd)
176
 
177
  /* Symbol table for prog_bfd */
178
  struct bfd_symbol **prog_syms;
179
#define STATE_PROG_SYMS(sd) ((sd)->base.prog_syms)
180
 
181
  /* The program's text section.  */
182
  struct bfd_section *text_section;
183
  /* Starting and ending text section addresses from the bfd.  */
184
  bfd_vma text_start, text_end;
185
#define STATE_TEXT_SECTION(sd) ((sd)->base.text_section)
186
#define STATE_TEXT_START(sd) ((sd)->base.text_start)
187
#define STATE_TEXT_END(sd) ((sd)->base.text_end)
188
 
189
  /* Start address, set when the program is loaded from the bfd.  */
190
  bfd_vma start_addr;
191
#define STATE_START_ADDR(sd) ((sd)->base.start_addr)
192
 
193
  /* Size of the simulator's cache, if any.
194
     This is not the target's cache.  It is the cache the simulator uses
195
     to process instructions.  */
196
  unsigned int scache_size;
197
#define STATE_SCACHE_SIZE(sd) ((sd)->base.scache_size)
198
 
199
  /* FIXME: Move to top level sim_state struct (as some struct)?  */
200
#ifdef SIM_HAVE_FLATMEM
201
  unsigned int mem_size;
202
#define STATE_MEM_SIZE(sd) ((sd)->base.mem_size)
203
  unsigned int mem_base;
204
#define STATE_MEM_BASE(sd) ((sd)->base.mem_base)
205
  unsigned char *memory;
206
#define STATE_MEMORY(sd) ((sd)->base.memory)
207
#endif
208
 
209
  /* core memory bus */
210
#define STATE_CORE(sd) (&(sd)->base.core)
211
  sim_core core;
212
 
213
  /* Record of memory sections added via the memory-options interface.  */
214
#define STATE_MEMOPT(sd) ((sd)->base.memopt)
215
  sim_memopt *memopt;
216
 
217
  /* event handler */
218
#define STATE_EVENTS(sd) (&(sd)->base.events)
219
  sim_events events;
220
 
221
  /* generic halt/resume engine */
222
  sim_engine engine;
223
#define STATE_ENGINE(sd) (&(sd)->base.engine)
224
 
225
  /* generic watchpoint support */
226
  sim_watchpoints watchpoints;
227
#define STATE_WATCHPOINTS(sd) (&(sd)->base.watchpoints)
228
 
229
#if WITH_HW
230
  struct sim_hw *hw;
231
#define STATE_HW(sd) ((sd)->base.hw)
232
#endif
233
 
234
  /* Should image loads be performed using the LMA or VMA?  Older
235
     simulators use the VMA while newer simulators prefer the LMA. */
236
  int load_at_lma_p;
237
#define STATE_LOAD_AT_LMA_P(SD) ((SD)->base.load_at_lma_p)
238
 
239
  /* Marker for those wanting to do sanity checks.
240
     This should remain the last member of this struct to help catch
241
     miscompilation errors.  */
242
  int magic;
243
#define SIM_MAGIC_NUMBER 0x4242
244
#define STATE_MAGIC(sd) ((sd)->base.magic)
245
} sim_state_base;
246
 
247
/* Functions for allocating/freeing a sim_state.  */
248
SIM_DESC sim_state_alloc PARAMS ((SIM_OPEN_KIND kind, host_callback *callback));
249
void sim_state_free PARAMS ((SIM_DESC));
250
 
251
#endif /* SIM_BASE_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.