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/* Simulator instruction semantics for crisv32f.

THIS FILE IS MACHINE GENERATED WITH CGEN.

Copyright 1996-2010 Free Software Foundation, Inc.

This file is part of the GNU simulators.

   This file is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 3, or (at your option)

   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT

   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public

   License for more details.

   You should have received a copy of the GNU General Public License along

   with this program; if not, write to the Free Software Foundation, Inc.,

   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.

*/

#ifdef DEFINE_LABELS

  /* The labels have the case they have because the enum of insn types

     is all uppercase and in the non-stdc case the insn symbol is built

     into the enum name.  */

  static struct {

    int index;

    void *label;

  } labels[] = {

    { CRISV32F_INSN_X_INVALID, && case_sem_INSN_X_INVALID },

    { CRISV32F_INSN_X_AFTER, && case_sem_INSN_X_AFTER },

    { CRISV32F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },

    { CRISV32F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },

    { CRISV32F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },

    { CRISV32F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },

    { CRISV32F_INSN_MOVE_B_R, && case_sem_INSN_MOVE_B_R },

    { CRISV32F_INSN_MOVE_W_R, && case_sem_INSN_MOVE_W_R },

    { CRISV32F_INSN_MOVE_D_R, && case_sem_INSN_MOVE_D_R },

    { CRISV32F_INSN_MOVEQ, && case_sem_INSN_MOVEQ },

    { CRISV32F_INSN_MOVS_B_R, && case_sem_INSN_MOVS_B_R },

    { CRISV32F_INSN_MOVS_W_R, && case_sem_INSN_MOVS_W_R },

    { CRISV32F_INSN_MOVU_B_R, && case_sem_INSN_MOVU_B_R },

    { CRISV32F_INSN_MOVU_W_R, && case_sem_INSN_MOVU_W_R },

    { CRISV32F_INSN_MOVECBR, && case_sem_INSN_MOVECBR },

    { CRISV32F_INSN_MOVECWR, && case_sem_INSN_MOVECWR },

    { CRISV32F_INSN_MOVECDR, && case_sem_INSN_MOVECDR },

    { CRISV32F_INSN_MOVSCBR, && case_sem_INSN_MOVSCBR },

    { CRISV32F_INSN_MOVSCWR, && case_sem_INSN_MOVSCWR },

    { CRISV32F_INSN_MOVUCBR, && case_sem_INSN_MOVUCBR },

    { CRISV32F_INSN_MOVUCWR, && case_sem_INSN_MOVUCWR },

    { CRISV32F_INSN_ADDQ, && case_sem_INSN_ADDQ },

    { CRISV32F_INSN_SUBQ, && case_sem_INSN_SUBQ },

    { CRISV32F_INSN_CMP_R_B_R, && case_sem_INSN_CMP_R_B_R },

    { CRISV32F_INSN_CMP_R_W_R, && case_sem_INSN_CMP_R_W_R },

    { CRISV32F_INSN_CMP_R_D_R, && case_sem_INSN_CMP_R_D_R },

    { CRISV32F_INSN_CMP_M_B_M, && case_sem_INSN_CMP_M_B_M },

    { CRISV32F_INSN_CMP_M_W_M, && case_sem_INSN_CMP_M_W_M },

    { CRISV32F_INSN_CMP_M_D_M, && case_sem_INSN_CMP_M_D_M },

    { CRISV32F_INSN_CMPCBR, && case_sem_INSN_CMPCBR },

    { CRISV32F_INSN_CMPCWR, && case_sem_INSN_CMPCWR },

    { CRISV32F_INSN_CMPCDR, && case_sem_INSN_CMPCDR },

    { CRISV32F_INSN_CMPQ, && case_sem_INSN_CMPQ },

    { CRISV32F_INSN_CMPS_M_B_M, && case_sem_INSN_CMPS_M_B_M },

    { CRISV32F_INSN_CMPS_M_W_M, && case_sem_INSN_CMPS_M_W_M },

    { CRISV32F_INSN_CMPSCBR, && case_sem_INSN_CMPSCBR },

    { CRISV32F_INSN_CMPSCWR, && case_sem_INSN_CMPSCWR },

    { CRISV32F_INSN_CMPU_M_B_M, && case_sem_INSN_CMPU_M_B_M },

    { CRISV32F_INSN_CMPU_M_W_M, && case_sem_INSN_CMPU_M_W_M },

    { CRISV32F_INSN_CMPUCBR, && case_sem_INSN_CMPUCBR },

    { CRISV32F_INSN_CMPUCWR, && case_sem_INSN_CMPUCWR },

    { CRISV32F_INSN_MOVE_M_B_M, && case_sem_INSN_MOVE_M_B_M },

    { CRISV32F_INSN_MOVE_M_W_M, && case_sem_INSN_MOVE_M_W_M },

    { CRISV32F_INSN_MOVE_M_D_M, && case_sem_INSN_MOVE_M_D_M },

    { CRISV32F_INSN_MOVS_M_B_M, && case_sem_INSN_MOVS_M_B_M },

    { CRISV32F_INSN_MOVS_M_W_M, && case_sem_INSN_MOVS_M_W_M },

    { CRISV32F_INSN_MOVU_M_B_M, && case_sem_INSN_MOVU_M_B_M },

    { CRISV32F_INSN_MOVU_M_W_M, && case_sem_INSN_MOVU_M_W_M },

    { CRISV32F_INSN_MOVE_R_SPRV32, && case_sem_INSN_MOVE_R_SPRV32 },

    { CRISV32F_INSN_MOVE_SPR_RV32, && case_sem_INSN_MOVE_SPR_RV32 },

    { CRISV32F_INSN_MOVE_M_SPRV32, && case_sem_INSN_MOVE_M_SPRV32 },

    { CRISV32F_INSN_MOVE_C_SPRV32_P2, && case_sem_INSN_MOVE_C_SPRV32_P2 },

    { CRISV32F_INSN_MOVE_C_SPRV32_P3, && case_sem_INSN_MOVE_C_SPRV32_P3 },

    { CRISV32F_INSN_MOVE_C_SPRV32_P5, && case_sem_INSN_MOVE_C_SPRV32_P5 },

    { CRISV32F_INSN_MOVE_C_SPRV32_P6, && case_sem_INSN_MOVE_C_SPRV32_P6 },

    { CRISV32F_INSN_MOVE_C_SPRV32_P7, && case_sem_INSN_MOVE_C_SPRV32_P7 },

    { CRISV32F_INSN_MOVE_C_SPRV32_P9, && case_sem_INSN_MOVE_C_SPRV32_P9 },

    { CRISV32F_INSN_MOVE_C_SPRV32_P10, && case_sem_INSN_MOVE_C_SPRV32_P10 },

    { CRISV32F_INSN_MOVE_C_SPRV32_P11, && case_sem_INSN_MOVE_C_SPRV32_P11 },

    { CRISV32F_INSN_MOVE_C_SPRV32_P12, && case_sem_INSN_MOVE_C_SPRV32_P12 },

    { CRISV32F_INSN_MOVE_C_SPRV32_P13, && case_sem_INSN_MOVE_C_SPRV32_P13 },

    { CRISV32F_INSN_MOVE_C_SPRV32_P14, && case_sem_INSN_MOVE_C_SPRV32_P14 },

    { CRISV32F_INSN_MOVE_C_SPRV32_P15, && case_sem_INSN_MOVE_C_SPRV32_P15 },

    { CRISV32F_INSN_MOVE_SPR_MV32, && case_sem_INSN_MOVE_SPR_MV32 },

    { CRISV32F_INSN_MOVE_SS_R, && case_sem_INSN_MOVE_SS_R },

    { CRISV32F_INSN_MOVE_R_SS, && case_sem_INSN_MOVE_R_SS },

    { CRISV32F_INSN_MOVEM_R_M_V32, && case_sem_INSN_MOVEM_R_M_V32 },

    { CRISV32F_INSN_MOVEM_M_R_V32, && case_sem_INSN_MOVEM_M_R_V32 },

    { CRISV32F_INSN_ADD_B_R, && case_sem_INSN_ADD_B_R },

    { CRISV32F_INSN_ADD_W_R, && case_sem_INSN_ADD_W_R },

    { CRISV32F_INSN_ADD_D_R, && case_sem_INSN_ADD_D_R },

    { CRISV32F_INSN_ADD_M_B_M, && case_sem_INSN_ADD_M_B_M },

    { CRISV32F_INSN_ADD_M_W_M, && case_sem_INSN_ADD_M_W_M },

    { CRISV32F_INSN_ADD_M_D_M, && case_sem_INSN_ADD_M_D_M },

    { CRISV32F_INSN_ADDCBR, && case_sem_INSN_ADDCBR },

    { CRISV32F_INSN_ADDCWR, && case_sem_INSN_ADDCWR },

    { CRISV32F_INSN_ADDCDR, && case_sem_INSN_ADDCDR },

    { CRISV32F_INSN_ADDS_B_R, && case_sem_INSN_ADDS_B_R },

    { CRISV32F_INSN_ADDS_W_R, && case_sem_INSN_ADDS_W_R },

    { CRISV32F_INSN_ADDS_M_B_M, && case_sem_INSN_ADDS_M_B_M },

    { CRISV32F_INSN_ADDS_M_W_M, && case_sem_INSN_ADDS_M_W_M },

    { CRISV32F_INSN_ADDSCBR, && case_sem_INSN_ADDSCBR },

    { CRISV32F_INSN_ADDSCWR, && case_sem_INSN_ADDSCWR },

    { CRISV32F_INSN_ADDU_B_R, && case_sem_INSN_ADDU_B_R },

    { CRISV32F_INSN_ADDU_W_R, && case_sem_INSN_ADDU_W_R },

    { CRISV32F_INSN_ADDU_M_B_M, && case_sem_INSN_ADDU_M_B_M },

    { CRISV32F_INSN_ADDU_M_W_M, && case_sem_INSN_ADDU_M_W_M },

    { CRISV32F_INSN_ADDUCBR, && case_sem_INSN_ADDUCBR },

    { CRISV32F_INSN_ADDUCWR, && case_sem_INSN_ADDUCWR },

    { CRISV32F_INSN_SUB_B_R, && case_sem_INSN_SUB_B_R },

    { CRISV32F_INSN_SUB_W_R, && case_sem_INSN_SUB_W_R },

    { CRISV32F_INSN_SUB_D_R, && case_sem_INSN_SUB_D_R },

    { CRISV32F_INSN_SUB_M_B_M, && case_sem_INSN_SUB_M_B_M },

    { CRISV32F_INSN_SUB_M_W_M, && case_sem_INSN_SUB_M_W_M },

    { CRISV32F_INSN_SUB_M_D_M, && case_sem_INSN_SUB_M_D_M },

    { CRISV32F_INSN_SUBCBR, && case_sem_INSN_SUBCBR },

    { CRISV32F_INSN_SUBCWR, && case_sem_INSN_SUBCWR },

    { CRISV32F_INSN_SUBCDR, && case_sem_INSN_SUBCDR },

    { CRISV32F_INSN_SUBS_B_R, && case_sem_INSN_SUBS_B_R },

    { CRISV32F_INSN_SUBS_W_R, && case_sem_INSN_SUBS_W_R },

    { CRISV32F_INSN_SUBS_M_B_M, && case_sem_INSN_SUBS_M_B_M },

    { CRISV32F_INSN_SUBS_M_W_M, && case_sem_INSN_SUBS_M_W_M },

    { CRISV32F_INSN_SUBSCBR, && case_sem_INSN_SUBSCBR },

    { CRISV32F_INSN_SUBSCWR, && case_sem_INSN_SUBSCWR },

    { CRISV32F_INSN_SUBU_B_R, && case_sem_INSN_SUBU_B_R },

    { CRISV32F_INSN_SUBU_W_R, && case_sem_INSN_SUBU_W_R },

    { CRISV32F_INSN_SUBU_M_B_M, && case_sem_INSN_SUBU_M_B_M },

    { CRISV32F_INSN_SUBU_M_W_M, && case_sem_INSN_SUBU_M_W_M },

    { CRISV32F_INSN_SUBUCBR, && case_sem_INSN_SUBUCBR },

    { CRISV32F_INSN_SUBUCWR, && case_sem_INSN_SUBUCWR },

    { CRISV32F_INSN_ADDC_R, && case_sem_INSN_ADDC_R },

    { CRISV32F_INSN_ADDC_M, && case_sem_INSN_ADDC_M },

    { CRISV32F_INSN_ADDC_C, && case_sem_INSN_ADDC_C },

    { CRISV32F_INSN_LAPC_D, && case_sem_INSN_LAPC_D },

    { CRISV32F_INSN_LAPCQ, && case_sem_INSN_LAPCQ },

    { CRISV32F_INSN_ADDI_B_R, && case_sem_INSN_ADDI_B_R },

    { CRISV32F_INSN_ADDI_W_R, && case_sem_INSN_ADDI_W_R },

    { CRISV32F_INSN_ADDI_D_R, && case_sem_INSN_ADDI_D_R },

    { CRISV32F_INSN_NEG_B_R, && case_sem_INSN_NEG_B_R },

    { CRISV32F_INSN_NEG_W_R, && case_sem_INSN_NEG_W_R },

    { CRISV32F_INSN_NEG_D_R, && case_sem_INSN_NEG_D_R },

    { CRISV32F_INSN_TEST_M_B_M, && case_sem_INSN_TEST_M_B_M },

    { CRISV32F_INSN_TEST_M_W_M, && case_sem_INSN_TEST_M_W_M },

    { CRISV32F_INSN_TEST_M_D_M, && case_sem_INSN_TEST_M_D_M },

    { CRISV32F_INSN_MOVE_R_M_B_M, && case_sem_INSN_MOVE_R_M_B_M },

    { CRISV32F_INSN_MOVE_R_M_W_M, && case_sem_INSN_MOVE_R_M_W_M },

    { CRISV32F_INSN_MOVE_R_M_D_M, && case_sem_INSN_MOVE_R_M_D_M },

    { CRISV32F_INSN_MULS_B, && case_sem_INSN_MULS_B },

    { CRISV32F_INSN_MULS_W, && case_sem_INSN_MULS_W },

    { CRISV32F_INSN_MULS_D, && case_sem_INSN_MULS_D },

    { CRISV32F_INSN_MULU_B, && case_sem_INSN_MULU_B },

    { CRISV32F_INSN_MULU_W, && case_sem_INSN_MULU_W },

    { CRISV32F_INSN_MULU_D, && case_sem_INSN_MULU_D },

    { CRISV32F_INSN_MCP, && case_sem_INSN_MCP },

    { CRISV32F_INSN_DSTEP, && case_sem_INSN_DSTEP },

    { CRISV32F_INSN_ABS, && case_sem_INSN_ABS },

    { CRISV32F_INSN_AND_B_R, && case_sem_INSN_AND_B_R },

    { CRISV32F_INSN_AND_W_R, && case_sem_INSN_AND_W_R },

    { CRISV32F_INSN_AND_D_R, && case_sem_INSN_AND_D_R },

    { CRISV32F_INSN_AND_M_B_M, && case_sem_INSN_AND_M_B_M },

    { CRISV32F_INSN_AND_M_W_M, && case_sem_INSN_AND_M_W_M },

    { CRISV32F_INSN_AND_M_D_M, && case_sem_INSN_AND_M_D_M },

    { CRISV32F_INSN_ANDCBR, && case_sem_INSN_ANDCBR },

    { CRISV32F_INSN_ANDCWR, && case_sem_INSN_ANDCWR },

    { CRISV32F_INSN_ANDCDR, && case_sem_INSN_ANDCDR },

    { CRISV32F_INSN_ANDQ, && case_sem_INSN_ANDQ },

    { CRISV32F_INSN_ORR_B_R, && case_sem_INSN_ORR_B_R },

    { CRISV32F_INSN_ORR_W_R, && case_sem_INSN_ORR_W_R },

    { CRISV32F_INSN_ORR_D_R, && case_sem_INSN_ORR_D_R },

    { CRISV32F_INSN_OR_M_B_M, && case_sem_INSN_OR_M_B_M },

    { CRISV32F_INSN_OR_M_W_M, && case_sem_INSN_OR_M_W_M },

    { CRISV32F_INSN_OR_M_D_M, && case_sem_INSN_OR_M_D_M },

    { CRISV32F_INSN_ORCBR, && case_sem_INSN_ORCBR },

    { CRISV32F_INSN_ORCWR, && case_sem_INSN_ORCWR },

    { CRISV32F_INSN_ORCDR, && case_sem_INSN_ORCDR },

    { CRISV32F_INSN_ORQ, && case_sem_INSN_ORQ },

    { CRISV32F_INSN_XOR, && case_sem_INSN_XOR },

    { CRISV32F_INSN_SWAP, && case_sem_INSN_SWAP },

    { CRISV32F_INSN_ASRR_B_R, && case_sem_INSN_ASRR_B_R },

    { CRISV32F_INSN_ASRR_W_R, && case_sem_INSN_ASRR_W_R },

    { CRISV32F_INSN_ASRR_D_R, && case_sem_INSN_ASRR_D_R },

    { CRISV32F_INSN_ASRQ, && case_sem_INSN_ASRQ },

    { CRISV32F_INSN_LSRR_B_R, && case_sem_INSN_LSRR_B_R },

    { CRISV32F_INSN_LSRR_W_R, && case_sem_INSN_LSRR_W_R },

    { CRISV32F_INSN_LSRR_D_R, && case_sem_INSN_LSRR_D_R },

    { CRISV32F_INSN_LSRQ, && case_sem_INSN_LSRQ },

    { CRISV32F_INSN_LSLR_B_R, && case_sem_INSN_LSLR_B_R },

    { CRISV32F_INSN_LSLR_W_R, && case_sem_INSN_LSLR_W_R },

    { CRISV32F_INSN_LSLR_D_R, && case_sem_INSN_LSLR_D_R },

    { CRISV32F_INSN_LSLQ, && case_sem_INSN_LSLQ },

    { CRISV32F_INSN_BTST, && case_sem_INSN_BTST },

    { CRISV32F_INSN_BTSTQ, && case_sem_INSN_BTSTQ },

    { CRISV32F_INSN_SETF, && case_sem_INSN_SETF },

    { CRISV32F_INSN_CLEARF, && case_sem_INSN_CLEARF },

    { CRISV32F_INSN_RFE, && case_sem_INSN_RFE },

    { CRISV32F_INSN_SFE, && case_sem_INSN_SFE },

    { CRISV32F_INSN_RFG, && case_sem_INSN_RFG },

    { CRISV32F_INSN_RFN, && case_sem_INSN_RFN },

    { CRISV32F_INSN_HALT, && case_sem_INSN_HALT },

    { CRISV32F_INSN_BCC_B, && case_sem_INSN_BCC_B },

    { CRISV32F_INSN_BA_B, && case_sem_INSN_BA_B },

    { CRISV32F_INSN_BCC_W, && case_sem_INSN_BCC_W },

    { CRISV32F_INSN_BA_W, && case_sem_INSN_BA_W },

    { CRISV32F_INSN_JAS_R, && case_sem_INSN_JAS_R },

    { CRISV32F_INSN_JAS_C, && case_sem_INSN_JAS_C },

    { CRISV32F_INSN_JUMP_P, && case_sem_INSN_JUMP_P },

    { CRISV32F_INSN_BAS_C, && case_sem_INSN_BAS_C },

    { CRISV32F_INSN_JASC_R, && case_sem_INSN_JASC_R },

    { CRISV32F_INSN_JASC_C, && case_sem_INSN_JASC_C },

    { CRISV32F_INSN_BASC_C, && case_sem_INSN_BASC_C },

    { CRISV32F_INSN_BREAK, && case_sem_INSN_BREAK },

    { CRISV32F_INSN_BOUND_R_B_R, && case_sem_INSN_BOUND_R_B_R },

    { CRISV32F_INSN_BOUND_R_W_R, && case_sem_INSN_BOUND_R_W_R },

    { CRISV32F_INSN_BOUND_R_D_R, && case_sem_INSN_BOUND_R_D_R },

    { CRISV32F_INSN_BOUND_CB, && case_sem_INSN_BOUND_CB },

    { CRISV32F_INSN_BOUND_CW, && case_sem_INSN_BOUND_CW },

    { CRISV32F_INSN_BOUND_CD, && case_sem_INSN_BOUND_CD },

    { CRISV32F_INSN_SCC, && case_sem_INSN_SCC },

    { CRISV32F_INSN_LZ, && case_sem_INSN_LZ },

    { CRISV32F_INSN_ADDOQ, && case_sem_INSN_ADDOQ },

    { CRISV32F_INSN_ADDO_M_B_M, && case_sem_INSN_ADDO_M_B_M },

    { CRISV32F_INSN_ADDO_M_W_M, && case_sem_INSN_ADDO_M_W_M },

    { CRISV32F_INSN_ADDO_M_D_M, && case_sem_INSN_ADDO_M_D_M },

    { CRISV32F_INSN_ADDO_CB, && case_sem_INSN_ADDO_CB },

    { CRISV32F_INSN_ADDO_CW, && case_sem_INSN_ADDO_CW },

    { CRISV32F_INSN_ADDO_CD, && case_sem_INSN_ADDO_CD },

    { CRISV32F_INSN_ADDI_ACR_B_R, && case_sem_INSN_ADDI_ACR_B_R },

    { CRISV32F_INSN_ADDI_ACR_W_R, && case_sem_INSN_ADDI_ACR_W_R },

    { CRISV32F_INSN_ADDI_ACR_D_R, && case_sem_INSN_ADDI_ACR_D_R },

    { CRISV32F_INSN_FIDXI, && case_sem_INSN_FIDXI },

    { CRISV32F_INSN_FTAGI, && case_sem_INSN_FTAGI },

    { CRISV32F_INSN_FIDXD, && case_sem_INSN_FIDXD },

    { CRISV32F_INSN_FTAGD, && case_sem_INSN_FTAGD },

    { 0, 0 }

  };

  int i;

  for (i = 0; labels[i].label != 0; ++i)

    {

#if FAST_P

      CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;

#else

      CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;

#endif

    }

#undef DEFINE_LABELS

#endif /* DEFINE_LABELS */

#ifdef DEFINE_SWITCH

/* If hyper-fast [well not unnecessarily slow] execution is selected, turn

   off frills like tracing and profiling.  */

/* FIXME: A better way would be to have TRACE_RESULT check for something

   that can cause it to be optimized out.  Another way would be to emit

   special handlers into the instruction "stream".  */

#if FAST_P

#undef TRACE_RESULT

#define TRACE_RESULT(cpu, abuf, name, type, val)

#endif

#undef GET_ATTR

#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)

{

#if WITH_SCACHE_PBB

/* Branch to next handler without going around main loop.  */

#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case

SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)

#else /* ! WITH_SCACHE_PBB */

#define NEXT(vpc) BREAK (sem)

#ifdef __GNUC__

#if FAST_P

  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)

#else

  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)

#endif

#else

  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)

#endif

#endif /* ! WITH_SCACHE_PBB */

    {

  CASE (sem, INSN_X_INVALID) : /* --invalid-- */

{

  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

#define FLD(f) abuf->fields.sfmt_empty.f

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {

    /* Update the recorded pc in the cpu state struct.

       Only necessary for WITH_SCACHE case, but to avoid the

       conditional compilation ....  */

    SET_H_PC (pc);

    /* Virtual insns have zero size.  Overwrite vpc with address of next insn

       using the default-insn-bitsize spec.  When executing insns in parallel

       we may want to queue the fault and continue execution.  */

    vpc = SEM_NEXT_VPC (sem_arg, pc, 2);

    vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);

  }

#undef FLD

}

  NEXT (vpc);

  CASE (sem, INSN_X_AFTER) : /* --after-- */

{

  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

#define FLD(f) abuf->fields.sfmt_empty.f

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {

#if WITH_SCACHE_PBB_CRISV32F

    crisv32f_pbb_after (current_cpu, sem_arg);

#endif

  }

#undef FLD

}

  NEXT (vpc);

  CASE (sem, INSN_X_BEFORE) : /* --before-- */

{

  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

#define FLD(f) abuf->fields.sfmt_empty.f

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {

#if WITH_SCACHE_PBB_CRISV32F

    crisv32f_pbb_before (current_cpu, sem_arg);

#endif

  }

#undef FLD

}

  NEXT (vpc);

  CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */

{

  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

#define FLD(f) abuf->fields.sfmt_empty.f

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {

#if WITH_SCACHE_PBB_CRISV32F

#ifdef DEFINE_SWITCH

    vpc = crisv32f_pbb_cti_chain (current_cpu, sem_arg,

                               pbb_br_type, pbb_br_npc);

    BREAK (sem);

#else

    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */

    vpc = crisv32f_pbb_cti_chain (current_cpu, sem_arg,

                               CPU_PBB_BR_TYPE (current_cpu),

                               CPU_PBB_BR_NPC (current_cpu));

#endif

#endif

  }

#undef FLD

}

  NEXT (vpc);

  CASE (sem, INSN_X_CHAIN) : /* --chain-- */

{

  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

#define FLD(f) abuf->fields.sfmt_empty.f

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {

#if WITH_SCACHE_PBB_CRISV32F

    vpc = crisv32f_pbb_chain (current_cpu, sem_arg);

#ifdef DEFINE_SWITCH

    BREAK (sem);

#endif

#endif

  }

#undef FLD

}

  NEXT (vpc);

  CASE (sem, INSN_X_BEGIN) : /* --begin-- */

{

  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

#define FLD(f) abuf->fields.sfmt_empty.f

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);

  {

#if WITH_SCACHE_PBB_CRISV32F

#if defined DEFINE_SWITCH || defined FAST_P

    /* In the switch case FAST_P is a constant, allowing several optimizations

       in any called inline functions.  */

    vpc = crisv32f_pbb_begin (current_cpu, FAST_P);

#else

#if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */

    vpc = crisv32f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));

#else

    vpc = crisv32f_pbb_begin (current_cpu, 0);

#endif

#endif

#endif

  }

#undef FLD

}

  NEXT (vpc);

  CASE (sem, INSN_MOVE_B_R) : /* move.b move.m ${Rs},${Rd} */

{

  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

#define FLD(f) abuf->fields.sfmt_addc_m.f

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);

{

  QI tmp_newval;

  tmp_newval = GET_H_GR (FLD (f_operand1));

{

  SI tmp_oldregval;

  tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));

  {

    SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));

    SET_H_GR (FLD (f_operand2), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

}

{

  {

    BI opval = LTQI (tmp_newval, 0);

    CPU (h_nbit) = opval;

    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);

  }

  {

    BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));

    CPU (h_zbit) = opval;

    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);

  }

SET_H_CBIT_MOVE (0);

SET_H_VBIT_MOVE (0);

{

  {

    BI opval = 0;

    CPU (h_xbit) = opval;

    TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);

  }

  {

    BI opval = 0;

    SET_H_INSN_PREFIXED_P (opval);

    TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);

  }

}

}

}

#undef FLD

}

  NEXT (vpc);

  CASE (sem, INSN_MOVE_W_R) : /* move.w move.m ${Rs},${Rd} */

{

  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

#define FLD(f) abuf->fields.sfmt_addc_m.f

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);

{

  HI tmp_newval;

  tmp_newval = GET_H_GR (FLD (f_operand1));

{

  SI tmp_oldregval;

  tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));

  {

    SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));

    SET_H_GR (FLD (f_operand2), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

}

{

  {

    BI opval = LTHI (tmp_newval, 0);

    CPU (h_nbit) = opval;

    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);

  }

  {

    BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));

    CPU (h_zbit) = opval;

    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);

  }

SET_H_CBIT_MOVE (0);

SET_H_VBIT_MOVE (0);

{

  {

    BI opval = 0;

    CPU (h_xbit) = opval;

    TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);

  }

  {

    BI opval = 0;

    SET_H_INSN_PREFIXED_P (opval);

    TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);

  }

}

}

}

#undef FLD

}

  NEXT (vpc);

  CASE (sem, INSN_MOVE_D_R) : /* move.d move.m ${Rs},${Rd} */

{

  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

#define FLD(f) abuf->fields.sfmt_addc_m.f

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);

{

  SI tmp_newval;

  tmp_newval = GET_H_GR (FLD (f_operand1));

  {

    SI opval = tmp_newval;

    SET_H_GR (FLD (f_operand2), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

{

  {

    BI opval = LTSI (tmp_newval, 0);

    CPU (h_nbit) = opval;

    TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);

  }

  {

    BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));

    CPU (h_zbit) = opval;

    TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);

  }

SET_H_CBIT_MOVE (0);

SET_H_VBIT_MOVE (0);

{

  {

    BI opval = 0;

    CPU (h_xbit) = opval;

    TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);

  }

  {

    BI opval = 0;

    SET_H_INSN_PREFIXED_P (opval);

    TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);

  }

}

}

}

#undef FLD

}

  NEXT (vpc);

  CASE (sem, INSN_MOVEQ) : /* moveq $i,$Rd */

{

  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);

  ARGBUF *abuf = SEM_ARGBUF (sem_arg);

#define FLD(f) abuf->fields.sfmt_moveq.f

  int UNUSED written = 0;

  IADDR UNUSED pc = abuf->addr;

  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);

{

  SI tmp_newval;

  tmp_newval = FLD (f_s6);

  {

    SI opval = tmp_newval;

    SET_H_GR (FLD (f_operand2), opval);

    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);

  }

{

SET_H_NBIT_MOVE (LTSI (tmp_newval, 0));

SET_H_ZBIT_MOVE (ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))));

SET_H_CBIT_MOVE (0);

SET_H_VBIT_MOVE (0);

{

  {

    BI opval = 0;

    CPU (h_xbit) = opval;