OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [iq2000/] [cpu.c] - Blame information for rev 252

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
/* Misc. support for CPU family iq2000bf.
2
 
3
THIS FILE IS MACHINE GENERATED WITH CGEN.
4
 
5
Copyright 1996-2010 Free Software Foundation, Inc.
6
 
7
This file is part of the GNU simulators.
8
 
9
   This file is free software; you can redistribute it and/or modify
10
   it under the terms of the GNU General Public License as published by
11
   the Free Software Foundation; either version 3, or (at your option)
12
   any later version.
13
 
14
   It is distributed in the hope that it will be useful, but WITHOUT
15
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17
   License for more details.
18
 
19
   You should have received a copy of the GNU General Public License along
20
   with this program; if not, write to the Free Software Foundation, Inc.,
21
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
 
23
*/
24
 
25
#define WANT_CPU iq2000bf
26
#define WANT_CPU_IQ2000BF
27
 
28
#include "sim-main.h"
29
#include "cgen-ops.h"
30
 
31
/* Get the value of h-pc.  */
32
 
33
USI
34
iq2000bf_h_pc_get (SIM_CPU *current_cpu)
35
{
36
  return GET_H_PC ();
37
}
38
 
39
/* Set a value for h-pc.  */
40
 
41
void
42
iq2000bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
43
{
44
  SET_H_PC (newval);
45
}
46
 
47
/* Get the value of h-gr.  */
48
 
49
SI
50
iq2000bf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
51
{
52
  return GET_H_GR (regno);
53
}
54
 
55
/* Set a value for h-gr.  */
56
 
57
void
58
iq2000bf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
59
{
60
  SET_H_GR (regno, newval);
61
}
62
 
63
/* Record trace results for INSN.  */
64
 
65
void
66
iq2000bf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
67
                            int *indices, TRACE_RECORD *tr)
68
{
69
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.