OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [iq2000/] [sim-main.h] - Blame information for rev 227

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
 
2
/* Main header for the Vitesse IQ2000.  */
3
 
4
#ifndef SIM_MAIN_H
5
#define SIM_MAIN_H
6
 
7
#define USING_SIM_BASE_H /* FIXME: quick hack */
8
 
9
struct _sim_cpu; /* FIXME: should be in sim-basics.h */
10
typedef struct _sim_cpu SIM_CPU;
11
 
12
/* sim-basics.h includes config.h but cgen-types.h must be included before
13
   sim-basics.h and cgen-types.h needs config.h.  */
14
#include "config.h"
15
 
16
#include "symcat.h"
17
#include "sim-basics.h"
18
#include "cgen-types.h"
19
#include "iq2000-desc.h"
20
#include "iq2000-opc.h"
21
#include "arch.h"
22
 
23
/* Pull in IQ2000_{DATA,INSN}_{MASK,VALUE}.  */
24
#include "elf/iq2000.h"
25
 
26
/* These must be defined before sim-base.h.  */
27
typedef USI sim_cia;
28
 
29
#define CIA_GET(cpu)     CPU_PC_GET (cpu)
30
#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
31
 
32
#include "sim-base.h"
33
#include "cgen-sim.h"
34
#include "iq2000-sim.h"
35
 
36
/* The _sim_cpu struct.  */
37
 
38
struct _sim_cpu {
39
  /* sim/common cpu base.  */
40
  sim_cpu_base base;
41
 
42
  /* Static parts of cgen.  */
43
  CGEN_CPU cgen_cpu;
44
 
45
  /* CPU specific parts go here.
46
     Note that in files that don't need to access these pieces WANT_CPU_FOO
47
     won't be defined and thus these parts won't appear.  This is ok in the
48
     sense that things work.  It is a source of bugs though.
49
     One has to of course be careful to not take the size of this
50
     struct and no structure members accessed in non-cpu specific files can
51
     go after here.  Oh for a better language.  */
52
#if defined (WANT_CPU_IQ2000BF)
53
  IQ2000BF_CPU_DATA cpu_data;
54
#endif
55
};
56
 
57
/* The sim_state struct.  */
58
 
59
struct sim_state {
60
  sim_cpu *cpu;
61
#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
62
 
63
  CGEN_STATE cgen_state;
64
 
65
  sim_state_base base;
66
};
67
 
68
/* Misc.  */
69
 
70
/* Catch address exceptions.  */
71
extern SIM_CORE_SIGNAL_FN iq2000_core_signal;
72
#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
73
iq2000_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
74
                  (TRANSFER), (ERROR))
75
 
76
/* Convert between CPU-internal addresses and sim_core addresses.  */
77
#define CPU2DATA(addr) (IQ2000_DATA_VALUE + (addr))
78
#define DATA2CPU(addr) ((addr) - IQ2000_DATA_VALUE)
79
#define CPU2INSN(addr) (IQ2000_INSN_VALUE + ((addr) & ~IQ2000_INSN_MASK))
80
#define INSN2CPU(addr) ((addr) - IQ2000_INSN_VALUE)
81
#define IQ2000_INSN_MEM_SIZE (CPU2INSN(0x800000) - CPU2INSN(0x0000))
82
#define IQ2000_DATA_MEM_SIZE (CPU2DATA(0x800000) - CPU2DATA(0x0000))
83
 
84
#endif /* SIM_MAIN_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.