OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [lm32/] [lm32-sim.h] - Blame information for rev 297

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
/* Contributed by Jon Beniston <jon@beniston.com>
2
 
3
   Copyright (C) 2009, 2010 Free Software Foundation, Inc.
4
 
5
   This file is part of GDB.
6
 
7
   This program is free software; you can redistribute it and/or modify
8
   it under the terms of the GNU General Public License as published by
9
   the Free Software Foundation; either version 3 of the License, or
10
   (at your option) any later version.
11
 
12
   This program is distributed in the hope that it will be useful,
13
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
   GNU General Public License for more details.
16
 
17
   You should have received a copy of the GNU General Public License
18
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
19
 
20
#ifndef LM32_SIM_H
21
#define LM32_SIM_H
22
 
23
#include "gdb/sim-lm32.h"
24
 
25
/* CSRs.  */
26
#define LM32_CSR_IE             0
27
#define LM32_CSR_IM             1
28
#define LM32_CSR_IP             2
29
#define LM32_CSR_ICC            3
30
#define LM32_CSR_DCC            4
31
#define LM32_CSR_CC             5
32
#define LM32_CSR_CFG            6
33
#define LM32_CSR_EBA            7
34
#define LM32_CSR_DC             8
35
#define LM32_CSR_DEBA           9
36
#define LM32_CSR_JTX            0xe
37
#define LM32_CSR_JRX            0xf
38
#define LM32_CSR_BP0            0x10
39
#define LM32_CSR_BP1            0x11
40
#define LM32_CSR_BP2            0x12
41
#define LM32_CSR_BP3            0x13
42
#define LM32_CSR_WP0            0x18
43
#define LM32_CSR_WP1            0x19
44
#define LM32_CSR_WP2            0x1a
45
#define LM32_CSR_WP3            0x1b
46
 
47
/* Exception IDs.  */
48
#define LM32_EID_RESET                  0
49
#define LM32_EID_BREAKPOINT             1
50
#define LM32_EID_INSTRUCTION_BUS_ERROR  2
51
#define LM32_EID_WATCHPOINT             3
52
#define LM32_EID_DATA_BUS_ERROR         4
53
#define LM32_EID_DIVIDE_BY_ZERO         5
54
#define LM32_EID_INTERRUPT              6
55
#define LM32_EID_SYSTEM_CALL            7
56
 
57
#endif /* LM32_SIM_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.