OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [lm32/] [lm32.c] - Blame information for rev 252

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
/* Lattice Mico32 simulator support code.
2
   Contributed by Jon Beniston <jon@beniston.com>
3
 
4
   Copyright (C) 2009, 2010 Free Software Foundation, Inc.
5
 
6
   This file is part of GDB.
7
 
8
   This program is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3 of the License, or
11
   (at your option) any later version.
12
 
13
   This program is distributed in the hope that it will be useful,
14
   but WITHOUT ANY WARRANTY; without even the implied warranty of
15
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
   GNU General Public License for more details.
17
 
18
   You should have received a copy of the GNU General Public License
19
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
20
 
21
#define WANT_CPU lm32bf
22
#define WANT_CPU_LM32BF
23
 
24
#include "sim-main.h"
25
#include "cgen-mem.h"
26
#include "cgen-ops.h"
27
 
28
/* The contents of BUF are in target byte order.  */
29
 
30
int
31
lm32bf_fetch_register (SIM_CPU * current_cpu, int rn, unsigned char *buf,
32
                       int len)
33
{
34
  if (rn < 32)
35
    SETTSI (buf, lm32bf_h_gr_get (current_cpu, rn));
36
  else
37
    switch (rn)
38
      {
39
      case SIM_LM32_PC_REGNUM:
40
        SETTSI (buf, lm32bf_h_pc_get (current_cpu));
41
        break;
42
      default:
43
        return 0;
44
      }
45
 
46
  return -1;
47
}
48
 
49
/* The contents of BUF are in target byte order.  */
50
 
51
int
52
lm32bf_store_register (SIM_CPU * current_cpu, int rn, unsigned char *buf,
53
                       int len)
54
{
55
  if (rn < 32)
56
    lm32bf_h_gr_set (current_cpu, rn, GETTSI (buf));
57
  else
58
    switch (rn)
59
      {
60
      case SIM_LM32_PC_REGNUM:
61
        lm32bf_h_pc_set (current_cpu, GETTSI (buf));
62
        break;
63
      default:
64
        return 0;
65
      }
66
 
67
  return -1;
68
}
69
 
70
 
71
 
72
#if WITH_PROFILE_MODEL_P
73
 
74
/* Initialize cycle counting for an insn.
75
   FIRST_P is non-zero if this is the first insn in a set of parallel
76
   insns.  */
77
 
78
void
79
lm32bf_model_insn_before (SIM_CPU * cpu, int first_p)
80
{
81
}
82
 
83
/* Record the cycles computed for an insn.
84
   LAST_P is non-zero if this is the last insn in a set of parallel insns,
85
   and we update the total cycle count.
86
   CYCLES is the cycle count of the insn.  */
87
 
88
void
89
lm32bf_model_insn_after (SIM_CPU * cpu, int last_p, int cycles)
90
{
91
}
92
 
93
int
94
lm32bf_model_lm32_u_exec (SIM_CPU * cpu, const IDESC * idesc,
95
                          int unit_num, int referenced)
96
{
97
  return idesc->timing->units[unit_num].done;
98
}
99
 
100
#endif /* WITH_PROFILE_MODEL_P */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.