OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [lm32/] [sim-main.h] - Blame information for rev 309

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
/* Lattice Mico32 simulator support code
2
   Contributed by Jon Beniston <jon@beniston.com>
3
 
4
   Copyright (C) 2009, 2010 Free Software Foundation, Inc.
5
 
6
   This file is part of GDB.
7
 
8
   This program is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3 of the License, or
11
   (at your option) any later version.
12
 
13
   This program is distributed in the hope that it will be useful,
14
   but WITHOUT ANY WARRANTY; without even the implied warranty of
15
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
   GNU General Public License for more details.
17
 
18
   You should have received a copy of the GNU General Public License
19
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
20
 
21
/* Main header for the LM32 simulator.  */
22
 
23
#ifndef SIM_MAIN_H
24
#define SIM_MAIN_H
25
 
26
#define USING_SIM_BASE_H        /* FIXME: quick hack */
27
 
28
struct _sim_cpu;                /* FIXME: should be in sim-basics.h */
29
typedef struct _sim_cpu SIM_CPU;
30
 
31
#include "symcat.h"
32
#include "sim-basics.h"
33
#include "cgen-types.h"
34
#include "lm32-desc.h"
35
#include "lm32-opc.h"
36
#include "arch.h"
37
 
38
/* These must be defined before sim-base.h.  */
39
typedef USI sim_cia;
40
 
41
#define CIA_GET(cpu)     CPU_PC_GET (cpu)
42
#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
43
 
44
#define SIM_ENGINE_HALT_HOOK(sd, cpu, cia) \
45
do { \
46
  if (cpu) /* null if ctrl-c */ \
47
    sim_pc_set ((cpu), (cia)); \
48
} while (0)
49
#define SIM_ENGINE_RESTART_HOOK(sd, cpu, cia) \
50
do { \
51
  sim_pc_set ((cpu), (cia)); \
52
} while (0)
53
 
54
#include "sim-base.h"
55
#include "cgen-sim.h"
56
#include "lm32-sim.h"
57
#include "opcode/cgen.h"
58
 
59
/* The _sim_cpu struct.  */
60
 
61
struct _sim_cpu
62
{
63
  /* sim/common cpu base.  */
64
  sim_cpu_base base;
65
 
66
  /* Static parts of cgen.  */
67
  CGEN_CPU cgen_cpu;
68
 
69
  /* CPU specific parts go here.
70
     Note that in files that don't need to access these pieces WANT_CPU_FOO
71
     won't be defined and thus these parts won't appear.  This is ok in the
72
     sense that things work.  It is a source of bugs though.
73
     One has to of course be careful to not take the size of this
74
     struct and no structure members accessed in non-cpu specific files can
75
     go after here.  Oh for a better language.  */
76
#if defined (WANT_CPU_LM32BF)
77
  LM32BF_CPU_DATA cpu_data;
78
#endif
79
 
80
};
81
 
82
/* The sim_state struct.  */
83
 
84
struct sim_state
85
{
86
  sim_cpu *cpu;
87
#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
88
 
89
  CGEN_STATE cgen_state;
90
 
91
  sim_state_base base;
92
};
93
 
94
/* Misc.  */
95
 
96
/* Catch address exceptions.  */
97
extern SIM_CORE_SIGNAL_FN lm32_core_signal;
98
#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
99
lm32_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
100
                  (TRANSFER), (ERROR))
101
 
102
#endif /* SIM_MAIN_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.