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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [lm32/] [traps.c] - Blame information for rev 227

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1 227 jeremybenn
/* Lattice Mico32 exception and system call support.
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   Contributed by Jon Beniston <jon@beniston.com>
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   Copyright (C) 2009, 2010 Free Software Foundation, Inc.
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   This file is part of GDB.
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   This program is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License as published by
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   the Free Software Foundation; either version 3 of the License, or
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   (at your option) any later version.
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   This program is distributed in the hope that it will be useful,
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   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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   GNU General Public License for more details.
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   You should have received a copy of the GNU General Public License
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   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
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#define WANT_CPU lm32bf
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#define WANT_CPU_LM32BF
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#include "sim-main.h"
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#include "lm32-sim.h"
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#include "targ-vals.h"
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/* Read memory function for system call interface.  */
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static int
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syscall_read_mem (host_callback * cb, struct cb_syscall *sc,
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                  unsigned long taddr, char *buf, int bytes)
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{
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  SIM_DESC sd = (SIM_DESC) sc->p1;
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  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
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  return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
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}
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/* Write memory function for system call interface.  */
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static int
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syscall_write_mem (host_callback * cb, struct cb_syscall *sc,
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                   unsigned long taddr, const char *buf, int bytes)
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{
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  SIM_DESC sd = (SIM_DESC) sc->p1;
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  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
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  return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
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}
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/* Handle invalid instructions.  */
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SEM_PC
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sim_engine_invalid_insn (SIM_CPU * current_cpu, IADDR cia, SEM_PC pc)
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{
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  SIM_DESC sd = CPU_STATE (current_cpu);
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  sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
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61
  return pc;
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}
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/* Handle divide instructions. */
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USI
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lm32bf_divu_insn (SIM_CPU * current_cpu, IADDR pc, USI r0, USI r1, USI r2)
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{
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  SIM_DESC sd = CPU_STATE (current_cpu);
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  host_callback *cb = STATE_CALLBACK (sd);
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  /* Check for divide by zero */
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  if (GET_H_GR (r1) == 0)
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    {
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      if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
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        sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGFPE);
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      else
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        {
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          /* Save PC in exception address register.  */
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          SET_H_GR (30, pc);
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          /* Save and clear interrupt enable.  */
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          SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
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          /* Branch to divide by zero exception handler.  */
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          return GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DIVIDE_BY_ZERO * 32;
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        }
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    }
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  else
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    {
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      SET_H_GR (r2, (USI) GET_H_GR (r0) / (USI) GET_H_GR (r1));
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      return pc + 4;
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    }
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}
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USI
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lm32bf_modu_insn (SIM_CPU * current_cpu, IADDR pc, USI r0, USI r1, USI r2)
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{
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  SIM_DESC sd = CPU_STATE (current_cpu);
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  host_callback *cb = STATE_CALLBACK (sd);
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  /* Check for divide by zero.  */
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  if (GET_H_GR (r1) == 0)
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    {
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      if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
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        sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGFPE);
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      else
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        {
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          /* Save PC in exception address register.  */
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          SET_H_GR (30, pc);
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          /* Save and clear interrupt enable.  */
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          SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
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          /* Branch to divide by zero exception handler.  */
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          return GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DIVIDE_BY_ZERO * 32;
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        }
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    }
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  else
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    {
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      SET_H_GR (r2, (USI) GET_H_GR (r0) % (USI) GET_H_GR (r1));
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      return pc + 4;
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    }
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}
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/* Handle break instructions.  */
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USI
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lm32bf_break_insn (SIM_CPU * current_cpu, IADDR pc)
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{
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  SIM_DESC sd = CPU_STATE (current_cpu);
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  host_callback *cb = STATE_CALLBACK (sd);
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  /* Breakpoint.  */
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  if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
131
    {
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      sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
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      return pc;
134
    }
135
  else
136
    {
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      /* Save PC in breakpoint address register.  */
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      SET_H_GR (31, pc);
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      /* Save and clear interrupt enable.  */
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      SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 2);
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      /* Branch to breakpoint exception handler.  */
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      return GET_H_CSR (LM32_CSR_DEBA) + LM32_EID_BREAKPOINT * 32;
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    }
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}
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/* Handle scall instructions.  */
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148
USI
149
lm32bf_scall_insn (SIM_CPU * current_cpu, IADDR pc)
150
{
151
  SIM_DESC sd = CPU_STATE (current_cpu);
152
  host_callback *cb = STATE_CALLBACK (sd);
153
 
154
  if ((STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
155
      || (GET_H_GR (8) == TARGET_SYS_exit))
156
    {
157
      /* Delegate system call to host O/S.  */
158
      CB_SYSCALL s;
159
      CB_SYSCALL_INIT (&s);
160
      s.p1 = (PTR) sd;
161
      s.p2 = (PTR) current_cpu;
162
      s.read_mem = syscall_read_mem;
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      s.write_mem = syscall_write_mem;
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      /* Extract parameters.  */
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      s.func = GET_H_GR (8);
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      s.arg1 = GET_H_GR (1);
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      s.arg2 = GET_H_GR (2);
168
      s.arg3 = GET_H_GR (3);
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      /* Halt the simulator if the requested system call is _exit.  */
170
      if (s.func == TARGET_SYS_exit)
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        sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
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      /* Perform the system call.  */
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      cb_syscall (cb, &s);
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      /* Store the return value in the CPU's registers.  */
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      SET_H_GR (1, s.result);
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      SET_H_GR (2, s.result2);
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      SET_H_GR (3, s.errcode);
178
      /* Skip over scall instruction.  */
179
      return pc + 4;
180
    }
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  else
182
    {
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      /* Save PC in exception address register.  */
184
      SET_H_GR (30, pc);
185
      /* Save and clear interrupt enable */
186
      SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
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      /* Branch to system call exception handler.  */
188
      return GET_H_CSR (LM32_CSR_EBA) + LM32_EID_SYSTEM_CALL * 32;
189
    }
190
}
191
 
192
/* Handle b instructions.  */
193
 
194
USI
195
lm32bf_b_insn (SIM_CPU * current_cpu, USI r0, USI f_r0)
196
{
197
  SIM_DESC sd = CPU_STATE (current_cpu);
198
  host_callback *cb = STATE_CALLBACK (sd);
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200
  /* Restore interrupt enable.  */
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  if (f_r0 == 30)
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    SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 2) >> 1);
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  else if (f_r0 == 31)
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    SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 4) >> 2);
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  return r0;
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}
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/* Handle wcsr instructions.  */
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void
211
lm32bf_wcsr_insn (SIM_CPU * current_cpu, USI f_csr, USI r1)
212
{
213
  SIM_DESC sd = CPU_STATE (current_cpu);
214
  host_callback *cb = STATE_CALLBACK (sd);
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  /* Writing a 1 to IP CSR clears a bit, writing 0 has no effect.  */
217
  if (f_csr == LM32_CSR_IP)
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    SET_H_CSR (f_csr, GET_H_CSR (f_csr) & ~r1);
219
  else
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    SET_H_CSR (f_csr, r1);
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}
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223
/* Handle signals.  */
224
 
225
void
226
lm32_core_signal (SIM_DESC sd,
227
                  sim_cpu * cpu,
228
                  sim_cia cia,
229
                  unsigned map,
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                  int nr_bytes,
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                  address_word addr,
232
                  transfer_type transfer, sim_core_signals sig)
233
{
234
  const char *copy = (transfer == read_transfer ? "read" : "write");
235
  address_word ip = CIA_ADDR (cia);
236
  SIM_CPU *current_cpu = cpu;
237
 
238
  switch (sig)
239
    {
240
    case sim_core_unmapped_signal:
241
      sim_io_eprintf (sd,
242
                      "core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
243
                      nr_bytes, copy, (unsigned long) addr,
244
                      (unsigned long) ip);
245
      SET_H_GR (30, ip);
246
      /* Save and clear interrupt enable.  */
247
      SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
248
      CIA_SET (cpu, GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DATA_BUS_ERROR * 32);
249
      sim_engine_halt (sd, cpu, NULL, LM32_EID_DATA_BUS_ERROR * 32,
250
                       sim_stopped, SIM_SIGSEGV);
251
      break;
252
    case sim_core_unaligned_signal:
253
      sim_io_eprintf (sd,
254
                      "core: %d byte misaligned %s to address 0x%lx at 0x%lx\n",
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                      nr_bytes, copy, (unsigned long) addr,
256
                      (unsigned long) ip);
257
      SET_H_GR (30, ip);
258
      /* Save and clear interrupt enable.  */
259
      SET_H_CSR (LM32_CSR_IE, (GET_H_CSR (LM32_CSR_IE) & 1) << 1);
260
      CIA_SET (cpu, GET_H_CSR (LM32_CSR_EBA) + LM32_EID_DATA_BUS_ERROR * 32);
261
      sim_engine_halt (sd, cpu, NULL, LM32_EID_DATA_BUS_ERROR * 32,
262
                       sim_stopped, SIM_SIGBUS);
263
      break;
264
    default:
265
      sim_engine_abort (sd, cpu, cia,
266
                        "sim_core_signal - internal error - bad switch");
267
    }
268
}

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