OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [mips/] [smartmips.igen] - Blame information for rev 258

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
// -*- C -*-
2
//
3
// Simulator definition for the SmartMIPS extensions.
4
// Copyright (C) 2005, 2010 Free Software Foundation, Inc.
5
// Contributed by Nigel Stephens (nigel@mips.com) and
6
//                David Ung (davidu@mips.com) of MIPS Technologies.
7
//
8
// This file is part of GDB, the GNU debugger.
9
//
10
// This program is free software; you can redistribute it and/or modify
11
// it under the terms of the GNU General Public License as published by
12
// the Free Software Foundation; either version 3 of the License, or
13
// (at your option) any later version.
14
//
15
// This program is distributed in the hope that it will be useful,
16
// but WITHOUT ANY WARRANTY; without even the implied warranty of
17
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18
// GNU General Public License for more details.
19
//
20
// You should have received a copy of the GNU General Public License
21
// along with this program.  If not, see .
22
 
23
011100,5.BASE,5.INDEX,5.RD,00010,001000:SPECIAL:32::LWXS
24
"lwxs r, (r)"
25
*smartmips:
26
{
27
  GPR[RD] = EXTEND32 (do_load(SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]<<2));
28
}
29
 
30
011100,5.RS,5.RT,00000,10001,000001:SPECIAL:32::MADDP
31
"maddp r, r"
32
*smartmips:
33
{
34
  unsigned64 res;
35
  unsigned64 rs, rt;
36
  int i;
37
 
38
  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
39
  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
40
 
41
  res = 0;
42
  rs = GPR[RS];
43
  rt = GPR[RT];
44
  for (i = 0; i < 32; i++)
45
  {
46
      if (rs & 1)
47
          res ^= rt;
48
      rs >>= 1;
49
      rt <<= 1;
50
  }
51
  LO ^= EXTEND32 (VL4_8 (res));
52
  HI ^= EXTEND32 (VH4_8 (res));
53
  TRACE_ALU_RESULT2 (HI, LO);
54
}
55
 
56
 
57
000000,0000000000,5.RD,00001,010010:SPECIAL:32::MFLHXU
58
"mflhxu r"
59
*smartmips:
60
{
61
  check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
62
  TRACE_ALU_INPUT3 (ACX,HI,LO);
63
  GPR[RD] = LO;
64
  LO = HI;
65
  HI = ACX;
66
  ACX = 0;
67
  TRACE_ALU_RESULT4 (ACX,HI,LO,GPR[RD]);
68
}
69
 
70
000000,5.RS,000000000000001,010011:SPECIAL:32::MTLHX
71
"mtlhx r"
72
*smartmips:
73
{
74
  check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
75
  TRACE_ALU_INPUT3 (HI,LO,GPR[RS]);
76
  ACX = HI;
77
  HI = LO;
78
  LO = GPR[RS];
79
  TRACE_ALU_RESULT4 (ACX,HI,LO,GPR[RS]);
80
}
81
 
82
000000,5.RS,5.RT,00000,10001,011001:SPECIAL:32::MULTP
83
"multp r, r"
84
*smartmips:
85
{
86
  unsigned64 res;
87
  unsigned64 rs, rt;
88
  int i;
89
  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
90
  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
91
 
92
  res = 0;
93
  rs = GPR[RS];
94
  rt = GPR[RT];
95
  for (i = 0; i < 32; i++)
96
  {
97
      if (rs & 1)
98
          res ^= rt;
99
      rs >>= 1;
100
      rt <<= 1;
101
  }
102
  LO = EXTEND32 (VL4_8 (res));
103
  HI = EXTEND32 (VH4_8 (res));
104
  ACX = 0;
105
  TRACE_ALU_RESULT2 (HI, LO);
106
}
107
 
108
011100,5.RS,5.RT,00000,10010,000001:SPECIAL:32::PPERM
109
"pperm r, r"
110
*smartmips:
111
{
112
  int i;
113
  ACX = (ACX << 6) | MSEXTRACTED(HI,26,31);
114
  HI = EXTEND32 ((HI << 6) | MSEXTRACTED(LO,26,31));
115
  LO = EXTEND32 (LO << 6);
116
  for (i = 0; i < 6; i++) {
117
    int sbit = 5*i;
118
    int ebit = sbit + 4;
119
    int tbit = EXTRACTED(GPR[RT],sbit,ebit);
120
    LO |= MSEXTRACTED(GPR[RS],tbit,tbit) << i;
121
  }
122
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.