OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [or32/] [ChangeLog] - Blame information for rev 612

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 244 jeremybenn
2010-08-19  Jeremy Bennett  
2
 
3
        * wrapper.c: OR32_SIM_DEBUG added to control debug messages.
4
        (sim_close, sim_load, sim_create_inferior, sim_fetch_register)
5
        (sim_stop): Debug statement added.
6
        (sim_read, sim_write): Debug statements now controlled by
7
        OR32_SIM_DEBUG.
8
        (sim_store_register, sim_resume): Debug statement added and
9
        existing debug statements now controlled by OR32_SIM_DEBUG.
10
 
11
2010-08-15  Jeremy Bennett  
12
 
13
        * wrapper.c (sim_open): Assign result of or1ksim_init correctly.
14
        (sim_fetch_register): Return correct length on success.
15
 
16 237 jeremybenn
2010-08-04  Jeremy Bennett  
17
 
18
        * wrapper.c (sim_resume): Only set the NPC back on a true
19
        breakpoint, not a single step. Clear the single step flag if NOT
20
        stepping before unstalling.
21
 
22 227 jeremybenn
2010-07-20  Jeremy Bennett  
23
 
24
        * configure: Regenerated.
25
        * Makefile.in: Added LIBS.
26
 
27
2010-06-30  Jeremy Bennett  
28
 
29
        * config.in: Generated.
30
        * configure: Generated.
31
        * configure.ac: Created.
32
        * Makefile.in: Created.
33
        * or32sim.h: Created.
34
        * README: Created.
35
        * tconfig.in: Created.
36
        * wrapper.c: Created.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.