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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [ppc/] [igen.h] - Blame information for rev 227

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1 227 jeremybenn
/*  This file is part of the program psim.
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    Copyright (C) 1994,1995,1996, Andrew Cagney <cagney@highland.com.au>
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    This program is free software; you can redistribute it and/or modify
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    it under the terms of the GNU General Public License as published by
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    the Free Software Foundation; either version 2 of the License, or
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    (at your option) any later version.
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    This program is distributed in the hope that it will be useful,
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    but WITHOUT ANY WARRANTY; without even the implied warranty of
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    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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    GNU General Public License for more details.
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    You should have received a copy of the GNU General Public License
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    along with this program; if not, write to the Free Software
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    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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    */
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/* What does the instruction look like - bit ordering and size */
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extern int hi_bit_nr;
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extern int insn_bit_size;
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/* generation options: */
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enum {
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  generate_with_direct_access = 0x1,
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  generate_with_icache = 0x2,
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  generate_with_semantic_icache = 0x4,
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  generate_with_insn_in_icache = 0x8,
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};
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typedef enum {
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  /* Transfer control to an instructions semantic code using the the
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     standard call/return mechanism */
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  generate_calls = 0x100,
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  /* In addition, when refering to fields access them directly instead
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     of via variables */
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  generate_calls_with_direct_access
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    = generate_calls | generate_with_direct_access,
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  /* In addition, pre-decode an instructions opcode fields (entering
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     them into an icache) so that semantic code can avoid the need to
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     re-decode fields each time it is executed */
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  generate_calls_with_icache
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    = generate_calls | generate_with_icache,
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  /* In addition, the instruction decode code includes a duplicated
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     copy of the instructions semantic code.  This avoids the need to
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     perform two calls (one to decode an instructions opcode fields
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     and one to execute the instruction) when there is a miss of the
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     icache */
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  generate_calls_with_semantic_icache
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    = generate_calls_with_icache | generate_with_semantic_icache,
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  /* In addition, the semantic function refers to icache entries
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     directly instead of first moving them into local variables */
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  generate_calls_with_direct_access_icache
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    = generate_calls_with_icache | generate_with_direct_access,
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  generate_calls_with_direct_access_semantic_icache
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    = generate_calls_with_direct_access_icache | generate_with_semantic_icache,
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  /* Transfer control to an instructions semantic code using
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     (computed) goto's instead of the more conventional call/return
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     mechanism */
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  generate_jumps = 0x200,
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  /* As for generate jumps but with instruction fields accessed
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     directly */
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  generate_jumps_with_direct_access
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    = generate_jumps | generate_with_direct_access,
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  /* As for generate_calls_with_icache but applies to jumping code */
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  generate_jumps_with_icache
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    = generate_jumps | generate_with_icache,
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  /* As for generate_calls_with_semantic_icache but applies to jumping
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     code */
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  generate_jumps_with_semantic_icache
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    = generate_jumps_with_icache | generate_with_semantic_icache,
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  /* As for generate_calls_with_direct_access */
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  generate_jumps_with_direct_access_icache
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    = generate_jumps_with_icache | generate_with_direct_access,
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  generate_jumps_with_direct_access_semantic_icache
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    = generate_jumps_with_direct_access_icache | generate_with_semantic_icache,
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} igen_code;
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extern igen_code code;
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extern int icache_size;
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/* Instruction expansion?
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   Should the semantic code for each instruction, when the oportunity
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   arrises, be expanded according to the variable opcode files that
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   the instruction decode process renders constant */
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extern int generate_expanded_instructions;
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/* SMP?
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   Should the generated code include SMP support (>0) and if so, for
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   how many processors? */
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extern int generate_smp;
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/* Misc junk */
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/* Function header definitions */
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/* Cache functions: */
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#define ICACHE_FUNCTION_FORMAL \
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"cpu *processor,\n\
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 instruction_word instruction,\n\
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 unsigned_word cia,\n\
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 idecode_cache *cache_entry"
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#define ICACHE_FUNCTION_ACTUAL "processor, instruction, cia, cache_entry"
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#define ICACHE_FUNCTION_TYPE \
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((code & generate_with_semantic_icache) \
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 ? SEMANTIC_FUNCTION_TYPE \
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 : "idecode_semantic *")
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/* Semantic functions: */
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#define SEMANTIC_FUNCTION_FORMAL \
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((code & generate_with_icache) \
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 ? "cpu *processor,\n idecode_cache *cache_entry,\n unsigned_word cia" \
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 : "cpu *processor,\n instruction_word instruction,\n unsigned_word cia")
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#define SEMANTIC_FUNCTION_ACTUAL \
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((code & generate_with_icache) \
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 ? "processor, instruction, cia, cache_entry" \
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 : "processor, instruction, cia")
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#define SEMANTIC_FUNCTION_TYPE "unsigned_word"
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extern void print_my_defines
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(lf *file,
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 insn_bits *expanded_bits,
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 table_entry *file_entry);
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extern void print_itrace
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(lf *file,
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 table_entry *file_entry,
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 int idecode);
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typedef enum {
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  function_name_prefix_semantics,
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  function_name_prefix_idecode,
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  function_name_prefix_itable,
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  function_name_prefix_icache,
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  function_name_prefix_none
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} lf_function_name_prefixes;
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extern int print_function_name
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(lf *file,
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 const char *basename,
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 insn_bits *expanded_bits,
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 lf_function_name_prefixes prefix);

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