OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [sh64/] [cpu.h] - Blame information for rev 300

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn 
/* CPU family header for sh64.
2 
 
3 
THIS FILE IS MACHINE GENERATED WITH CGEN.
4 
 
5 
Copyright 1996-2010 Free Software Foundation, Inc.
6 
 
7 
This file is part of the GNU simulators.
8 
 
9 
   This file is free software; you can redistribute it and/or modify
10 
   it under the terms of the GNU General Public License as published by
11 
   the Free Software Foundation; either version 3, or (at your option)
12 
   any later version.
13 
 
14 
   It is distributed in the hope that it will be useful, but WITHOUT
15 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17 
   License for more details.
18 
 
19 
   You should have received a copy of the GNU General Public License along
20 
   with this program; if not, write to the Free Software Foundation, Inc.,
21 
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22 
 
23 
*/
24 
 
25 
#ifndef CPU_SH64_H
26 
#define CPU_SH64_H
27 
 
28 
/* Maximum number of instructions that are fetched at a time.
29 
   This is for LIW type instructions sets (e.g. m32r).  */
30 
#define MAX_LIW_INSNS 1
31 
 
32 
/* Maximum number of instructions that can be executed in parallel.  */
33 
#define MAX_PARALLEL_INSNS 1
34 
 
35 
/* The size of an "int" needed to hold an instruction word.
36 
   This is usually 32 bits, but some architectures needs 64 bits.  */
37 
typedef CGEN_INSN_INT CGEN_INSN_WORD;
38 
 
39 
#include "cgen-engine.h"
40 
 
41 
/* CPU state information.  */
42 
typedef struct {
43 
  /* Hardware elements.  */
44 
  struct {
45 
  /* Program counter */
46 
  UDI h_pc;
47 
#define GET_H_PC() CPU (h_pc)
48 
#define SET_H_PC(x) \
49 
do { \
50 
{\
51 
CPU (h_ism) = ANDDI ((x), 1);\
52 
CPU (h_pc) = ANDDI ((x), INVDI (1));\
53 
}\
54 
;} while (0)
55 
  /* General purpose integer registers */
56 
  DI h_gr[64];
57 
#define GET_H_GR(index) ((((index) == (63))) ? (MAKEDI (0, 0)) : (CPU (h_gr[index])))
58 
#define SET_H_GR(index, x) \
59 
do { \
60 
if ((((index)) != (63))) {\
61 
CPU (h_gr[(index)]) = (x);\
62 
} else {\
63 
((void) 0); /*nop*/\
64 
}\
65 
;} while (0)
66 
  /* Control registers */
67 
  DI h_cr[64];
68 
#define GET_H_CR(index) ((((index) == (0))) ? (ZEXTSIDI (CPU (h_sr))) : (CPU (h_cr[index])))
69 
#define SET_H_CR(index, x) \
70 
do { \
71 
if ((((index)) == (0))) {\
72 
CPU (h_sr) = (x);\
73 
} else {\
74 
CPU (h_cr[(index)]) = (x);\
75 
}\
76 
;} while (0)
77 
  /* Status register */
78 
  SI h_sr;
79 
#define GET_H_SR() CPU (h_sr)
80 
#define SET_H_SR(x) (CPU (h_sr) = (x))
81 
  /* Floating point status and control register */
82 
  SI h_fpscr;
83 
#define GET_H_FPSCR() CPU (h_fpscr)
84 
#define SET_H_FPSCR(x) (CPU (h_fpscr) = (x))
85 
  /* Single precision floating point registers */
86 
  SF h_fr[64];
87 
#define GET_H_FR(a1) CPU (h_fr)[a1]
88 
#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x))
89 
  /* Single/Double precision floating point registers */
90 
  DF h_fsd[16];
91 
#define GET_H_FSD(index) ((GET_H_PRBIT ()) ? (GET_H_DRC (index)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, CPU (h_fr[index]))))
92 
#define SET_H_FSD(index, x) \
93 
do { \
94 
if (GET_H_PRBIT ()) {\
95 
SET_H_DRC ((index), (x));\
96 
} else {\
97 
SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, (x)));\
98 
}\
99 
;} while (0)
100 
  /* floating point registers for fmov */
101 
  DF h_fmov[16];
102 
#define GET_H_FMOV(index) ((NOTBI (GET_H_SZBIT ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, GET_H_FRC (index))) : (((((((index) & (1))) == (1))) ? (GET_H_XD (((index) & ((~ (1)))))) : (GET_H_DR (index)))))
103 
#define SET_H_FMOV(index, x) \
104 
do { \
105 
if (NOTBI (GET_H_SZBIT ())) {\
106 
SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, (x)));\
107 
} else {\
108 
if ((((((index)) & (1))) == (1))) {\
109 
SET_H_XD ((((index)) & ((~ (1)))), (x));\
110 
} else {\
111 
SET_H_DR ((index), (x));\
112 
}\
113 
}\
114 
;} while (0)
115 
  /* Branch target registers */
116 
  DI h_tr[8];
117 
#define GET_H_TR(a1) CPU (h_tr)[a1]
118 
#define SET_H_TR(a1, x) (CPU (h_tr)[a1] = (x))
119 
  /* Current instruction set mode */
120 
  BI h_ism;
121 
#define GET_H_ISM() CPU (h_ism)
122 
#define SET_H_ISM(x) \
123 
do { \
124 
cgen_rtx_error (current_cpu, "cannot set ism directly");\
125 
;} while (0)
126 
  } hardware;
127 
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
128 
} SH64_CPU_DATA;
129 
 
130 
/* Virtual regs.  */
131 
 
132 
#define GET_H_GRC(index) ANDDI (CPU (h_gr[index]), ZEXTSIDI (0xffffffff))
133 
#define SET_H_GRC(index, x) \
134 
do { \
135 
CPU (h_gr[(index)]) = EXTSIDI ((x));\
136 
;} while (0)
137 
#define GET_H_FRBIT() ANDSI (SRLSI (CPU (h_fpscr), 21), 1)
138 
#define SET_H_FRBIT(x) \
139 
do { \
140 
CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (21))))), SLLSI ((x), 21));\
141 
;} while (0)
142 
#define GET_H_SZBIT() ANDSI (SRLSI (CPU (h_fpscr), 20), 1)
143 
#define SET_H_SZBIT(x) \
144 
do { \
145 
CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (20))))), SLLSI ((x), 20));\
146 
;} while (0)
147 
#define GET_H_PRBIT() ANDSI (SRLSI (CPU (h_fpscr), 19), 1)
148 
#define SET_H_PRBIT(x) \
149 
do { \
150 
CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (19))))), SLLSI ((x), 19));\
151 
;} while (0)
152 
#define GET_H_SBIT() ANDSI (SRLSI (CPU (h_sr), 1), 1)
153 
#define SET_H_SBIT(x) \
154 
do { \
155 
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (2))), SLLSI ((x), 1));\
156 
;} while (0)
157 
#define GET_H_MBIT() ANDSI (SRLSI (CPU (h_sr), 9), 1)
158 
#define SET_H_MBIT(x) \
159 
do { \
160 
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (9))))), SLLSI ((x), 9));\
161 
;} while (0)
162 
#define GET_H_QBIT() ANDSI (SRLSI (CPU (h_sr), 8), 1)
163 
#define SET_H_QBIT(x) \
164 
do { \
165 
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (8))))), SLLSI ((x), 8));\
166 
;} while (0)
167 
#define GET_H_FP(index) CPU (h_fr[index])
168 
#define SET_H_FP(index, x) \
169 
do { \
170 
CPU (h_fr[(index)]) = (x);\
171 
;} while (0)
172 
#define GET_H_FV(index) CPU (h_fr[index])
173 
#define SET_H_FV(index, x) \
174 
do { \
175 
CPU (h_fr[(index)]) = (x);\
176 
;} while (0)
177 
#define GET_H_FMTX(index) CPU (h_fr[index])
178 
#define SET_H_FMTX(index, x) \
179 
do { \
180 
CPU (h_fr[(index)]) = (x);\
181 
;} while (0)
182 
#define GET_H_DR(index) SUBWORDDIDF (ORDI (SLLDI (ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[index]))), 32), ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[((index) + (1))])))))
183 
#define SET_H_DR(index, x) \
184 
do { \
185 
{\
186 
CPU (h_fr[(index)]) = SUBWORDSISF (SUBWORDDFSI ((x), 0));\
187 
CPU (h_fr[(((index)) + (1))]) = SUBWORDSISF (SUBWORDDFSI ((x), 1));\
188 
}\
189 
;} while (0)
190 
#define GET_H_ENDIAN() sh64_endian (current_cpu)
191 
#define SET_H_ENDIAN(x) \
192 
do { \
193 
cgen_rtx_error (current_cpu, "cannot alter target byte order mid-program");\
194 
;} while (0)
195 
#define GET_H_FRC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
196 
#define SET_H_FRC(index, x) \
197 
do { \
198 
CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
199 
;} while (0)
200 
#define GET_H_DRC(index) GET_H_DR (((((16) * (GET_H_FRBIT ()))) + (index)))
201 
#define SET_H_DRC(index, x) \
202 
do { \
203 
SET_H_DR (((((16) * (GET_H_FRBIT ()))) + ((index))), (x));\
204 
;} while (0)
205 
#define GET_H_XF(index) CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + (index))])
206 
#define SET_H_XF(index, x) \
207 
do { \
208 
CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index)))]) = (x);\
209 
;} while (0)
210 
#define GET_H_XD(index) GET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + (index)))
211 
#define SET_H_XD(index, x) \
212 
do { \
213 
SET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index))), (x));\
214 
;} while (0)
215 
#define GET_H_FVC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
216 
#define SET_H_FVC(index, x) \
217 
do { \
218 
CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
219 
;} while (0)
220 
#define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1)
221 
#define SET_H_GBR(x) \
222 
do { \
223 
CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\
224 
;} while (0)
225 
#define GET_H_VBR() SUBWORDDISI (CPU (h_gr[((UINT) 20)]), 1)
226 
#define SET_H_VBR(x) \
227 
do { \
228 
CPU (h_gr[((UINT) 20)]) = EXTSIDI ((x));\
229 
;} while (0)
230 
#define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UINT) 18)]), 1)
231 
#define SET_H_PR(x) \
232 
do { \
233 
CPU (h_gr[((UINT) 18)]) = EXTSIDI ((x));\
234 
;} while (0)
235 
#define GET_H_MACL() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)
236 
#define SET_H_MACL(x) \
237 
do { \
238 
CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)), 32), ZEXTSIDI ((x)));\
239 
;} while (0)
240 
#define GET_H_MACH() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)
241 
#define SET_H_MACH(x) \
242 
do { \
243 
CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI ((x)), 32), ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)));\
244 
;} while (0)
245 
#define GET_H_TBIT() ANDBI (CPU (h_gr[((UINT) 19)]), 1)
246 
#define SET_H_TBIT(x) \
247 
do { \
248 
CPU (h_gr[((UINT) 19)]) = ORDI (ANDDI (CPU (h_gr[((UINT) 19)]), INVDI (1)), ZEXTBIDI ((x)));\
249 
;} while (0)
250 
 
251 
/* Cover fns for register access.  */
252 
UDI sh64_h_pc_get (SIM_CPU *);
253 
void sh64_h_pc_set (SIM_CPU *, UDI);
254 
DI sh64_h_gr_get (SIM_CPU *, UINT);
255 
void sh64_h_gr_set (SIM_CPU *, UINT, DI);
256 
SI sh64_h_grc_get (SIM_CPU *, UINT);
257 
void sh64_h_grc_set (SIM_CPU *, UINT, SI);
258 
DI sh64_h_cr_get (SIM_CPU *, UINT);
259 
void sh64_h_cr_set (SIM_CPU *, UINT, DI);
260 
SI sh64_h_sr_get (SIM_CPU *);
261 
void sh64_h_sr_set (SIM_CPU *, SI);
262 
SI sh64_h_fpscr_get (SIM_CPU *);
263 
void sh64_h_fpscr_set (SIM_CPU *, SI);
264 
BI sh64_h_frbit_get (SIM_CPU *);
265 
void sh64_h_frbit_set (SIM_CPU *, BI);
266 
BI sh64_h_szbit_get (SIM_CPU *);
267 
void sh64_h_szbit_set (SIM_CPU *, BI);
268 
BI sh64_h_prbit_get (SIM_CPU *);
269 
void sh64_h_prbit_set (SIM_CPU *, BI);
270 
BI sh64_h_sbit_get (SIM_CPU *);
271 
void sh64_h_sbit_set (SIM_CPU *, BI);
272 
BI sh64_h_mbit_get (SIM_CPU *);
273 
void sh64_h_mbit_set (SIM_CPU *, BI);
274 
BI sh64_h_qbit_get (SIM_CPU *);
275 
void sh64_h_qbit_set (SIM_CPU *, BI);
276 
SF sh64_h_fr_get (SIM_CPU *, UINT);
277 
void sh64_h_fr_set (SIM_CPU *, UINT, SF);
278 
SF sh64_h_fp_get (SIM_CPU *, UINT);
279 
void sh64_h_fp_set (SIM_CPU *, UINT, SF);
280 
SF sh64_h_fv_get (SIM_CPU *, UINT);
281 
void sh64_h_fv_set (SIM_CPU *, UINT, SF);
282 
SF sh64_h_fmtx_get (SIM_CPU *, UINT);
283 
void sh64_h_fmtx_set (SIM_CPU *, UINT, SF);
284 
DF sh64_h_dr_get (SIM_CPU *, UINT);
285 
void sh64_h_dr_set (SIM_CPU *, UINT, DF);
286 
DF sh64_h_fsd_get (SIM_CPU *, UINT);
287 
void sh64_h_fsd_set (SIM_CPU *, UINT, DF);
288 
DF sh64_h_fmov_get (SIM_CPU *, UINT);
289 
void sh64_h_fmov_set (SIM_CPU *, UINT, DF);
290 
DI sh64_h_tr_get (SIM_CPU *, UINT);
291 
void sh64_h_tr_set (SIM_CPU *, UINT, DI);
292 
BI sh64_h_endian_get (SIM_CPU *);
293 
void sh64_h_endian_set (SIM_CPU *, BI);
294 
BI sh64_h_ism_get (SIM_CPU *);
295 
void sh64_h_ism_set (SIM_CPU *, BI);
296 
SF sh64_h_frc_get (SIM_CPU *, UINT);
297 
void sh64_h_frc_set (SIM_CPU *, UINT, SF);
298 
DF sh64_h_drc_get (SIM_CPU *, UINT);
299 
void sh64_h_drc_set (SIM_CPU *, UINT, DF);
300 
SF sh64_h_xf_get (SIM_CPU *, UINT);
301 
void sh64_h_xf_set (SIM_CPU *, UINT, SF);
302 
DF sh64_h_xd_get (SIM_CPU *, UINT);
303 
void sh64_h_xd_set (SIM_CPU *, UINT, DF);
304 
SF sh64_h_fvc_get (SIM_CPU *, UINT);
305 
void sh64_h_fvc_set (SIM_CPU *, UINT, SF);
306 
SI sh64_h_gbr_get (SIM_CPU *);
307 
void sh64_h_gbr_set (SIM_CPU *, SI);
308 
SI sh64_h_vbr_get (SIM_CPU *);
309 
void sh64_h_vbr_set (SIM_CPU *, SI);
310 
SI sh64_h_pr_get (SIM_CPU *);
311 
void sh64_h_pr_set (SIM_CPU *, SI);
312 
SI sh64_h_macl_get (SIM_CPU *);
313 
void sh64_h_macl_set (SIM_CPU *, SI);
314 
SI sh64_h_mach_get (SIM_CPU *);
315 
void sh64_h_mach_set (SIM_CPU *, SI);
316 
BI sh64_h_tbit_get (SIM_CPU *);
317 
void sh64_h_tbit_set (SIM_CPU *, BI);
318 
 
319 
/* These must be hand-written.  */
320 
extern CPUREG_FETCH_FN sh64_fetch_register;
321 
extern CPUREG_STORE_FN sh64_store_register;
322 
 
323 
typedef struct {
324 
  int empty;
325 
} MODEL_SH4_DATA;
326 
 
327 
typedef struct {
328 
  int empty;
329 
} MODEL_SH5_DATA;
330 
 
331 
typedef struct {
332 
  int empty;
333 
} MODEL_SH5_MEDIA_DATA;
334 
 
335 
/* Collection of various things for the trace handler to use.  */
336 
 
337 
typedef struct trace_record {
338 
  IADDR pc;
339 
  /* FIXME:wip */
340 
} TRACE_RECORD;
341 
 
342 
#endif /* CPU_SH64_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.