OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [raw3.ms] - Blame information for rev 227

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
; Checking read-after-write: read-then-write unaffected.
2
#mach: crisv32
3
#output: Basic clock cycles, total @: 4\n
4
#output: Memory source stall cycles: 0\n
5
#output: Memory read-after-write stall cycles: 0\n
6
#output: Movem source stall cycles: 0\n
7
#output: Movem destination stall cycles: 0\n
8
#output: Movem address stall cycles: 0\n
9
#output: Multiplication source stall cycles: 0\n
10
#output: Jump source stall cycles: 0\n
11
#output: Branch misprediction stall cycles: 0\n
12
#output: Jump target stall cycles: 0\n
13
#sim: --cris-cycles=basic
14
 .include "testutils.inc"
15
 startnostack
16
 .lcomm x,4
17
 .lcomm y,4
18
 move.d x,$r0
19
 move.d y,$r1
20
 move.d [$r0],$r2
21
 move.d $r0,[$r1]
22
 break 15

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.