OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [frv/] [ftue.cgs] - Blame information for rev 227

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
# frv testcase for ftue $FCCi_2,$GRi,$GRj
2
# mach: all
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global ftue
9
ftue:
10
        and_spr_immed   -4081,tbr               ; clear tbr.tt
11
        set_gr_spr      tbr,gr7
12
        inc_gr_immed    2112,gr7                ; address of exception handler
13
        set_bctrlr_0_0  gr7     ; bctrlr 0,0
14
 
15
        set_spr_immed   128,lcr
16
        set_gr_immed    0,gr7
17
        set_gr_immed    4,gr8
18
 
19
        set_spr_addr    bad,lr
20
        set_fcc         0x0 0
21
        ftue            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
22
 
23
        set_psr_et      1
24
        set_spr_addr    ok1,lr
25
        set_fcc         0x1 0
26
        ftue            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
27
        fail
28
ok1:
29
        set_spr_addr    bad,lr
30
        set_fcc         0x2 0
31
        ftue            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
32
 
33
        set_psr_et      1
34
        set_spr_addr    ok3,lr
35
        set_fcc         0x3 0
36
        ftue            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
37
        fail
38
ok3:
39
        set_spr_addr    bad,lr
40
        set_fcc         0x4 0
41
        ftue            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
42
 
43
        set_psr_et      1
44
        set_spr_addr    ok5,lr
45
        set_fcc         0x5 0
46
        ftue            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
47
        fail
48
ok5:
49
        set_spr_addr    bad,lr
50
        set_fcc         0x6 0
51
        ftue            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
52
 
53
        set_psr_et      1
54
        set_spr_addr    ok7,lr
55
        set_fcc         0x7 0
56
        ftue            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
57
        fail
58
ok7:
59
        set_psr_et      1
60
        set_spr_addr    ok8,lr
61
        set_fcc         0x8 0
62
        ftue            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
63
        fail
64
ok8:
65
        set_psr_et      1
66
        set_spr_addr    ok9,lr
67
        set_fcc         0x9 0
68
        ftue            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
69
        fail
70
ok9:
71
        set_psr_et      1
72
        set_spr_addr    oka,lr
73
        set_fcc         0xa 0
74
        ftue            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
75
        fail
76
oka:
77
        set_psr_et      1
78
        set_spr_addr    okb,lr
79
        set_fcc         0xb 0
80
        ftue            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
81
        fail
82
okb:
83
        set_psr_et      1
84
        set_spr_addr    okc,lr
85
        set_fcc         0xc 0
86
        ftue            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
87
        fail
88
okc:
89
        set_psr_et      1
90
        set_spr_addr    okd,lr
91
        set_fcc         0xd 0
92
        ftue            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
93
        fail
94
okd:
95
        set_psr_et      1
96
        set_spr_addr    oke,lr
97
        set_fcc         0xe 0
98
        ftue            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
99
        fail
100
oke:
101
        set_psr_et      1
102
        set_spr_addr    okf,lr
103
        set_fcc         0xf 0
104
        ftue            fcc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
105
        fail
106
okf:
107
        pass
108
bad:
109
        fail

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.