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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [frv/] [mcmpuh.cgs] - Blame information for rev 227

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Line No. Rev Author Line
1 227 jeremybenn
# frv testcase for mcmpuh $FRi,$FRj,$FCCk
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# mach: all
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        .include "testutils.inc"
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        start
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        .global mcmpuh
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mcmpuh:
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        set_fr_iimmed   0x7fff,0x7fff,fr10
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        set_fr_iimmed   0x7fff,0x7fff,fr11
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        set_fcc         0x7,0           ; Set mask opposite of expected
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        set_fcc         0x7,1           ; Set mask opposite of expected
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        mcmpuh          fr10,fr11,fcc0
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        test_fcc        0x8,0
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        test_fcc        0x8,1
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        set_fr_iimmed   0x7fff,0x7fff,fr10
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        set_fr_iimmed   0x7fff,0x8000,fr11
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        set_fcc         0x7,0           ; Set mask opposite of expected
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        set_fcc         0xb,1           ; Set mask opposite of expected
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        mcmpuh          fr10,fr11,fcc0
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        test_fcc        0x8,0
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        test_fcc        0x4,1
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        set_fr_iimmed   0x7fff,0x7fff,fr10
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        set_fr_iimmed   0x8000,0x7fff,fr11
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        set_fcc         0xb,0           ; Set mask opposite of expected
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        set_fcc         0x7,1           ; Set mask opposite of expected
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        mcmpuh          fr10,fr11,fcc0
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        test_fcc        0x4,0
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        test_fcc        0x8,1
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        set_fr_iimmed   0x7fff,0x7fff,fr10
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        set_fr_iimmed   0x8000,0x8000,fr11
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        set_fcc         0xb,0           ; Set mask opposite of expected
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        set_fcc         0xb,1           ; Set mask opposite of expected
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        mcmpuh          fr10,fr11,fcc0
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        test_fcc        0x4,0
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        test_fcc        0x4,1
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        set_fr_iimmed   0x7fff,0x8000,fr10
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        set_fr_iimmed   0x7fff,0x7fff,fr11
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        set_fcc         0x7,0           ; Set mask opposite of expected
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        set_fcc         0xd,1           ; Set mask opposite of expected
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        mcmpuh          fr10,fr11,fcc0
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        test_fcc        0x8,0
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        test_fcc        0x2,1
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        set_fr_iimmed   0x7fff,0x8000,fr10
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        set_fr_iimmed   0x7fff,0x8000,fr11
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        set_fcc         0x7,0           ; Set mask opposite of expected
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        set_fcc         0x7,1           ; Set mask opposite of expected
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        mcmpuh          fr10,fr11,fcc0
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        test_fcc        0x8,0
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        test_fcc        0x8,1
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        set_fr_iimmed   0x7fff,0x8000,fr10
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        set_fr_iimmed   0x8000,0x7fff,fr11
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        set_fcc         0xb,0           ; Set mask opposite of expected
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        set_fcc         0xd,1           ; Set mask opposite of expected
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        mcmpuh          fr10,fr11,fcc0
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        test_fcc        0x4,0
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        test_fcc        0x2,1
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        set_fr_iimmed   0x7fff,0x8000,fr10
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        set_fr_iimmed   0x8000,0x8000,fr11
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        set_fcc         0xb,0           ; Set mask opposite of expected
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        set_fcc         0x7,1           ; Set mask opposite of expected
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        mcmpuh          fr10,fr11,fcc0
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        test_fcc        0x4,0
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        test_fcc        0x8,1
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        set_fr_iimmed   0x8000,0x7fff,fr10
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        set_fr_iimmed   0x7fff,0x7fff,fr11
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        set_fcc         0xd,0           ; Set mask opposite of expected
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        set_fcc         0x7,1           ; Set mask opposite of expected
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        mcmpuh          fr10,fr11,fcc0
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        test_fcc        0x2,0
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        test_fcc        0x8,1
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        set_fr_iimmed   0x8000,0x7fff,fr10
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        set_fr_iimmed   0x7fff,0x8000,fr11
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        set_fcc         0xd,0           ; Set mask opposite of expected
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        set_fcc         0xb,1           ; Set mask opposite of expected
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        mcmpuh          fr10,fr11,fcc0
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        test_fcc        0x2,0
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        test_fcc        0x4,1
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        set_fr_iimmed   0x8000,0x7fff,fr10
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        set_fr_iimmed   0x8000,0x7fff,fr11
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        set_fcc         0x7,0           ; Set mask opposite of expected
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        set_fcc         0x7,1           ; Set mask opposite of expected
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        mcmpuh          fr10,fr11,fcc0
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        test_fcc        0x8,0
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        test_fcc        0x8,1
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        set_fr_iimmed   0x8000,0x7fff,fr10
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        set_fr_iimmed   0x8000,0x8000,fr11
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        set_fcc         0x7,0           ; Set mask opposite of expected
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        set_fcc         0xb,1           ; Set mask opposite of expected
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        mcmpuh          fr10,fr11,fcc0
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        test_fcc        0x8,0
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        test_fcc        0x4,1
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        set_fr_iimmed   0x8000,0x8000,fr10
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        set_fr_iimmed   0x7fff,0x7fff,fr11
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        set_fcc         0xd,0           ; Set mask opposite of expected
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        set_fcc         0xd,1           ; Set mask opposite of expected
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        mcmpuh          fr10,fr11,fcc0
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        test_fcc        0x2,0
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        test_fcc        0x2,1
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        set_fr_iimmed   0x8000,0x8000,fr10
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        set_fr_iimmed   0x7fff,0x8000,fr11
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        set_fcc         0xd,0           ; Set mask opposite of expected
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        set_fcc         0x7,1           ; Set mask opposite of expected
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        mcmpuh          fr10,fr11,fcc0
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        test_fcc        0x2,0
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        test_fcc        0x8,1
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        set_fr_iimmed   0x8000,0x8000,fr10
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        set_fr_iimmed   0x8000,0x7fff,fr11
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        set_fcc         0x7,0           ; Set mask opposite of expected
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        set_fcc         0xd,1           ; Set mask opposite of expected
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        mcmpuh          fr10,fr11,fcc0
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        test_fcc        0x8,0
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        test_fcc        0x2,1
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        set_fr_iimmed   0x8000,0x8000,fr10
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        set_fr_iimmed   0x8000,0x8000,fr11
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        set_fcc         0x7,0           ; Set mask opposite of expected
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        set_fcc         0x7,1           ; Set mask opposite of expected
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        mcmpuh          fr10,fr11,fcc0
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        test_fcc        0x8,0
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        test_fcc        0x8,1
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        pass

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