URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [m32r/] [and3.cgs] - Blame information for rev 227

Details | Compare with Previous | View Log


# m32r testcase for and3 $dr,$sr,#$uimm16
# mach(): m32r m32rx
 
        .include "testutils.inc"
 
        start
 
        .global and3
and3:
        mvi_h_gr r4, 0
        mvi_h_gr r5, 6
 
        and3 r4, r5, #3
 
        test_h_gr r4, 2
 
        pass

Line No.	Rev	Author	Line
1	227	jeremybenn	`# m32r testcase for and3 $dr,$sr,#$uimm16`
2			`# mach(): m32r m32rx`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global and3`
9			`and3:`
10			`mvi_h_gr r4, 0`
11			`mvi_h_gr r5, 6`
12
13			`and3 r4, r5, #3`
14
15			`test_h_gr r4, 2`
16
17			`pass`

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [m32r/] [and3.cgs] - Blame information for rev 227