URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [m32r/] [rach.cgs] - Blame information for rev 227

Details | Compare with Previous | View Log


# m32r testcase for rach
# mach(): m32r m32rx
 
        .include "testutils.inc"
 
        start
 
        .global rach
rach:
        mvi_h_accum0 1, 0x40004001
        rach
        test_h_accum0 3, 0
 
        mvi_h_accum0 0x3fff, 0xc0000000
        rach
        test_h_accum0 0x7fff, 0
 
        mvi_h_accum0 0xffff8000, 0
        rach
        test_h_accum0 0xffff8000, 0
 
        pass

Line No.	Rev	Author	Line
1	227	jeremybenn	`# m32r testcase for rach`
2			`# mach(): m32r m32rx`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global rach`
9			`rach:`
10			`mvi_h_accum0 1, 0x40004001`
11			`rach`
12			`test_h_accum0 3, 0`
13
14			`mvi_h_accum0 0x3fff, 0xc0000000`
15			`rach`
16			`test_h_accum0 0x7fff, 0`
17
18			`mvi_h_accum0 0xffff8000, 0`
19			`rach`
20			`test_h_accum0 0xffff8000, 0`
21
22			`pass`

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [m32r/] [rach.cgs] - Blame information for rev 227