OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [mips/] [testutils.inc] - Blame information for rev 355

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn
# MIPS simulator testsuite utility functions.
2
# Copyright (C) 2004, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
3
# Contributed by Chris Demetriou of Broadcom Corporation.
4
#
5
# This file is part of the GNU simulators.
6
#
7
# This program is free software; you can redistribute it and/or modify
8
# it under the terms of the GNU General Public License as published by
9
# the Free Software Foundation; either version 3 of the License, or
10
# (at your option) any later version.
11
#
12
# This program is distributed in the hope that it will be useful,
13
# but WITHOUT ANY WARRANTY; without even the implied warranty of
14
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
# GNU General Public License for more details.
16
#
17
# You should have received a copy of the GNU General Public License
18
# along with this program.  If not, see .  */
19
 
20
 
21
# $1, $4, $5, %6, are used as temps by the macros defined here.
22
 
23
        .macro writemsg msg
24
        .data
25
901:    .ascii  "\msg\n"
26
902:
27
        .previous
28
        la      $5, 901b
29
        li      $6, 902b - 901b
30
        .set push
31
        .set noreorder
32
        jal     _dowrite
33
        li      $4, 0
34
        .set pop
35
        .endm
36
 
37
 
38
        # The MIPS simulator uses "break 0x3ff" as the code to exit,
39
        # with the return value in $4 (a0).
40
        .macro exit rc
41
        li      $4, \rc
42
        break   0x3ff
43
        .endm
44
 
45
 
46
        .macro setup
47
 
48
        .global _start
49
        .global __start
50
        .ent _start
51
_start:
52
__start:
53
        .set push
54
        .set noreorder
55
        j       DIAG
56
        nop
57
        .set pop
58
        .end _start
59
 
60
        .global _fail
61
        .ent _fail
62
_fail:
63
        writemsg "fail"
64
        exit 1
65
        .end _fail
66
 
67
        .global _pass
68
        .ent _pass
69
_pass:
70
        writemsg "pass"
71
        exit 0
72
        .end _pass
73
 
74
        # The MIPS simulator can use multiple different monitor types,
75
        # so we hard-code the simulator "write" reserved instruction opcode,
76
        # rather than jumping to a vector that invokes it.  The operation
77
        # expects RA to point to the location at which to continue
78
        # after writing.
79
        .global _dowrite
80
        .ent _dowrite
81
_dowrite:
82
        # Write opcode (reserved instruction).  See sim_monitor and its
83
        # callers in sim/mips/interp.c.
84
        .word   0x00000005 | ((8 << 1) << 6)
85
        .end _dowrite
86
 
87
        .endm   # setup
88
 
89
 
90
        .macro pass
91
        .set push
92
        .set noreorder
93
        j       _pass
94
        nop
95
        .set pop
96
        .endm
97
 
98
 
99
        .macro fail
100
        .set push
101
        .set noreorder
102
        j       _fail
103
        nop
104
        .set pop
105
        .endm
106
 
107
 
108
        .macro load32 reg, val
109
        li      \reg, \val
110
        .endm
111
 
112
 
113
        .macro load64 reg, val
114
        dli     \reg, \val
115
        .endm
116
 
117
 
118
        .macro loadaddr reg, addr
119
        la      \reg, \addr
120
        .endm
121
 
122
 
123
        .macro checkreg reg, expreg
124
        .set push
125
        .set noat
126
        .set noreorder
127
        beq     \expreg, \reg, 901f
128
        nop
129
        fail
130
901:
131
        .set pop
132
        .endm
133
 
134
 
135
        .macro check32 reg, val
136
        .set push
137
        .set noat
138
        load32  $1, \val
139
        checkreg \reg, $1
140
        .set pop
141
        .endm
142
 
143
 
144
        .macro check64 reg, val
145
        .set push
146
        .set noat
147
        load64  $1, \val
148
        checkreg \reg, $1
149
        .set pop
150
        .endm

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.