OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] [testsuite/] [sim/] [sh64/] [compact/] [div1.cgs] - Blame information for rev 227

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 227 jeremybenn 
# sh testcase for div1 $rm, $rn -*- Asm -*-
2 
# mach: all
3 
# as: -isa=shcompact
4 
# ld: -m shelf32
5 
 
6 
        .include "compact/testutils.inc"
7 
 
8 
        start
9 
        mov #10, r0
10 
        mov #2, r1
11 
        div0s r0,r1
12 
 
13 
        div1 r0, r1
14 
        div1 r0, r1
15 
        div1 r0, r1
16 
        div1 r0, r1
17 
        div1 r0, r1
18 
        div1 r0, r1
19 
        div1 r0, r1
20 
        div1 r0, r1
21 
        div1 r0, r1
22 
        div1 r0, r1
23 
        div1 r0, r1
24 
        div1 r0, r1
25 
        div1 r0, r1
26 
        div1 r0, r1
27 
        div1 r0, r1
28 
        div1 r0, r1
29 
        div1 r0, r1
30 
        div1 r0, r1
31 
        div1 r0, r1
32 
        div1 r0, r1
33 
        div1 r0, r1
34 
        div1 r0, r1
35 
        div1 r0, r1
36 
        div1 r0, r1
37 
        div1 r0, r1
38 
        div1 r0, r1
39 
        div1 r0, r1
40 
        div1 r0, r1
41 
        div1 r0, r1
42 
        div1 r0, r1
43 
        div1 r0, r1
44 
        div1 r0, r1
45 
        div1 r0, r1
46 
        div1 r0, r1
47 
        div1 r0, r1
48 
        div1 r0, r1
49 
        div1 r0, r1
50 
        div1 r0, r1
51 
 
52 
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.