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1 330 jeremybenn
@section Relocations
2
BFD maintains relocations in much the same way it maintains
3
symbols: they are left alone until required, then read in
4
en-masse and translated into an internal form.  A common
5
routine @code{bfd_perform_relocation} acts upon the
6
canonical form to do the fixup.
7
 
8
Relocations are maintained on a per section basis,
9
while symbols are maintained on a per BFD basis.
10
 
11
All that a back end has to do to fit the BFD interface is to create
12
a @code{struct reloc_cache_entry} for each relocation
13
in a particular section, and fill in the right bits of the structures.
14
 
15
@menu
16
* typedef arelent::
17
* howto manager::
18
@end menu
19
 
20
 
21
@node typedef arelent, howto manager, Relocations, Relocations
22
@subsection typedef arelent
23
This is the structure of a relocation entry:
24
 
25
 
26
@example
27
 
28
typedef enum bfd_reloc_status
29
@{
30
  /* No errors detected.  */
31
  bfd_reloc_ok,
32
 
33
  /* The relocation was performed, but there was an overflow.  */
34
  bfd_reloc_overflow,
35
 
36
  /* The address to relocate was not within the section supplied.  */
37
  bfd_reloc_outofrange,
38
 
39
  /* Used by special functions.  */
40
  bfd_reloc_continue,
41
 
42
  /* Unsupported relocation size requested.  */
43
  bfd_reloc_notsupported,
44
 
45
  /* Unused.  */
46
  bfd_reloc_other,
47
 
48
  /* The symbol to relocate against was undefined.  */
49
  bfd_reloc_undefined,
50
 
51
  /* The relocation was performed, but may not be ok - presently
52
     generated only when linking i960 coff files with i960 b.out
53
     symbols.  If this type is returned, the error_message argument
54
     to bfd_perform_relocation will be set.  */
55
  bfd_reloc_dangerous
56
 @}
57
 bfd_reloc_status_type;
58
 
59
 
60
typedef struct reloc_cache_entry
61
@{
62
  /* A pointer into the canonical table of pointers.  */
63
  struct bfd_symbol **sym_ptr_ptr;
64
 
65
  /* offset in section.  */
66
  bfd_size_type address;
67
 
68
  /* addend for relocation value.  */
69
  bfd_vma addend;
70
 
71
  /* Pointer to how to perform the required relocation.  */
72
  reloc_howto_type *howto;
73
 
74
@}
75
arelent;
76
 
77
@end example
78
@strong{Description}@*
79
Here is a description of each of the fields within an @code{arelent}:
80
 
81
@itemize @bullet
82
 
83
@item
84
@code{sym_ptr_ptr}
85
@end itemize
86
The symbol table pointer points to a pointer to the symbol
87
associated with the relocation request.  It is the pointer
88
into the table returned by the back end's
89
@code{canonicalize_symtab} action. @xref{Symbols}. The symbol is
90
referenced through a pointer to a pointer so that tools like
91
the linker can fix up all the symbols of the same name by
92
modifying only one pointer. The relocation routine looks in
93
the symbol and uses the base of the section the symbol is
94
attached to and the value of the symbol as the initial
95
relocation offset. If the symbol pointer is zero, then the
96
section provided is looked up.
97
 
98
@itemize @bullet
99
 
100
@item
101
@code{address}
102
@end itemize
103
The @code{address} field gives the offset in bytes from the base of
104
the section data which owns the relocation record to the first
105
byte of relocatable information. The actual data relocated
106
will be relative to this point; for example, a relocation
107
type which modifies the bottom two bytes of a four byte word
108
would not touch the first byte pointed to in a big endian
109
world.
110
 
111
@itemize @bullet
112
 
113
@item
114
@code{addend}
115
@end itemize
116
The @code{addend} is a value provided by the back end to be added (!)
117
to the relocation offset. Its interpretation is dependent upon
118
the howto. For example, on the 68k the code:
119
 
120
@example
121
        char foo[];
122
        main()
123
                @{
124
                return foo[0x12345678];
125
                @}
126
@end example
127
 
128
Could be compiled into:
129
 
130
@example
131
        linkw fp,#-4
132
        moveb @@#12345678,d0
133
        extbl d0
134
        unlk fp
135
        rts
136
@end example
137
 
138
This could create a reloc pointing to @code{foo}, but leave the
139
offset in the data, something like:
140
 
141
@example
142
RELOCATION RECORDS FOR [.text]:
143
offset   type      value
144
00000006 32        _foo
145
 
146
00000000 4e56 fffc          ; linkw fp,#-4
147
00000004 1039 1234 5678     ; moveb @@#12345678,d0
148
0000000a 49c0               ; extbl d0
149
0000000c 4e5e               ; unlk fp
150
0000000e 4e75               ; rts
151
@end example
152
 
153
Using coff and an 88k, some instructions don't have enough
154
space in them to represent the full address range, and
155
pointers have to be loaded in two parts. So you'd get something like:
156
 
157
@example
158
        or.u     r13,r0,hi16(_foo+0x12345678)
159
        ld.b     r2,r13,lo16(_foo+0x12345678)
160
        jmp      r1
161
@end example
162
 
163
This should create two relocs, both pointing to @code{_foo}, and with
164
0x12340000 in their addend field. The data would consist of:
165
 
166
@example
167
RELOCATION RECORDS FOR [.text]:
168
offset   type      value
169
00000002 HVRT16    _foo+0x12340000
170
00000006 LVRT16    _foo+0x12340000
171
 
172
00000000 5da05678           ; or.u r13,r0,0x5678
173
00000004 1c4d5678           ; ld.b r2,r13,0x5678
174
00000008 f400c001           ; jmp r1
175
@end example
176
 
177
The relocation routine digs out the value from the data, adds
178
it to the addend to get the original offset, and then adds the
179
value of @code{_foo}. Note that all 32 bits have to be kept around
180
somewhere, to cope with carry from bit 15 to bit 16.
181
 
182
One further example is the sparc and the a.out format. The
183
sparc has a similar problem to the 88k, in that some
184
instructions don't have room for an entire offset, but on the
185
sparc the parts are created in odd sized lumps. The designers of
186
the a.out format chose to not use the data within the section
187
for storing part of the offset; all the offset is kept within
188
the reloc. Anything in the data should be ignored.
189
 
190
@example
191
        save %sp,-112,%sp
192
        sethi %hi(_foo+0x12345678),%g2
193
        ldsb [%g2+%lo(_foo+0x12345678)],%i0
194
        ret
195
        restore
196
@end example
197
 
198
Both relocs contain a pointer to @code{foo}, and the offsets
199
contain junk.
200
 
201
@example
202
RELOCATION RECORDS FOR [.text]:
203
offset   type      value
204
00000004 HI22      _foo+0x12345678
205
00000008 LO10      _foo+0x12345678
206
 
207
00000000 9de3bf90     ; save %sp,-112,%sp
208
00000004 05000000     ; sethi %hi(_foo+0),%g2
209
00000008 f048a000     ; ldsb [%g2+%lo(_foo+0)],%i0
210
0000000c 81c7e008     ; ret
211
00000010 81e80000     ; restore
212
@end example
213
 
214
@itemize @bullet
215
 
216
@item
217
@code{howto}
218
@end itemize
219
The @code{howto} field can be imagined as a
220
relocation instruction. It is a pointer to a structure which
221
contains information on what to do with all of the other
222
information in the reloc record and data section. A back end
223
would normally have a relocation instruction set and turn
224
relocations into pointers to the correct structure on input -
225
but it would be possible to create each howto field on demand.
226
 
227
@subsubsection @code{enum complain_overflow}
228
Indicates what sort of overflow checking should be done when
229
performing a relocation.
230
 
231
 
232
@example
233
 
234
enum complain_overflow
235
@{
236
  /* Do not complain on overflow.  */
237
  complain_overflow_dont,
238
 
239
  /* Complain if the value overflows when considered as a signed
240
     number one bit larger than the field.  ie. A bitfield of N bits
241
     is allowed to represent -2**n to 2**n-1.  */
242
  complain_overflow_bitfield,
243
 
244
  /* Complain if the value overflows when considered as a signed
245
     number.  */
246
  complain_overflow_signed,
247
 
248
  /* Complain if the value overflows when considered as an
249
     unsigned number.  */
250
  complain_overflow_unsigned
251
@};
252
@end example
253
@subsubsection @code{reloc_howto_type}
254
The @code{reloc_howto_type} is a structure which contains all the
255
information that libbfd needs to know to tie up a back end's data.
256
 
257
 
258
@example
259
struct bfd_symbol;             /* Forward declaration.  */
260
 
261
struct reloc_howto_struct
262
@{
263
  /*  The type field has mainly a documentary use - the back end can
264
      do what it wants with it, though normally the back end's
265
      external idea of what a reloc number is stored
266
      in this field.  For example, a PC relative word relocation
267
      in a coff environment has the type 023 - because that's
268
      what the outside world calls a R_PCRWORD reloc.  */
269
  unsigned int type;
270
 
271
  /*  The value the final relocation is shifted right by.  This drops
272
      unwanted data from the relocation.  */
273
  unsigned int rightshift;
274
 
275
  /*  The size of the item to be relocated.  This is *not* a
276
      power-of-two measure.  To get the number of bytes operated
277
      on by a type of relocation, use bfd_get_reloc_size.  */
278
  int size;
279
 
280
  /*  The number of bits in the item to be relocated.  This is used
281
      when doing overflow checking.  */
282
  unsigned int bitsize;
283
 
284
  /*  The relocation is relative to the field being relocated.  */
285
  bfd_boolean pc_relative;
286
 
287
  /*  The bit position of the reloc value in the destination.
288
      The relocated value is left shifted by this amount.  */
289
  unsigned int bitpos;
290
 
291
  /* What type of overflow error should be checked for when
292
     relocating.  */
293
  enum complain_overflow complain_on_overflow;
294
 
295
  /* If this field is non null, then the supplied function is
296
     called rather than the normal function.  This allows really
297
     strange relocation methods to be accommodated (e.g., i960 callj
298
     instructions).  */
299
  bfd_reloc_status_type (*special_function)
300
    (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
301
     bfd *, char **);
302
 
303
  /* The textual name of the relocation type.  */
304
  char *name;
305
 
306
  /* Some formats record a relocation addend in the section contents
307
     rather than with the relocation.  For ELF formats this is the
308
     distinction between USE_REL and USE_RELA (though the code checks
309
     for USE_REL == 1/0).  The value of this field is TRUE if the
310
     addend is recorded with the section contents; when performing a
311
     partial link (ld -r) the section contents (the data) will be
312
     modified.  The value of this field is FALSE if addends are
313
     recorded with the relocation (in arelent.addend); when performing
314
     a partial link the relocation will be modified.
315
     All relocations for all ELF USE_RELA targets should set this field
316
     to FALSE (values of TRUE should be looked on with suspicion).
317
     However, the converse is not true: not all relocations of all ELF
318
     USE_REL targets set this field to TRUE.  Why this is so is peculiar
319
     to each particular target.  For relocs that aren't used in partial
320
     links (e.g. GOT stuff) it doesn't matter what this is set to.  */
321
  bfd_boolean partial_inplace;
322
 
323
  /* src_mask selects the part of the instruction (or data) to be used
324
     in the relocation sum.  If the target relocations don't have an
325
     addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
326
     dst_mask to extract the addend from the section contents.  If
327
     relocations do have an addend in the reloc, eg. ELF USE_RELA, this
328
     field should be zero.  Non-zero values for ELF USE_RELA targets are
329
     bogus as in those cases the value in the dst_mask part of the
330
     section contents should be treated as garbage.  */
331
  bfd_vma src_mask;
332
 
333
  /* dst_mask selects which parts of the instruction (or data) are
334
     replaced with a relocated value.  */
335
  bfd_vma dst_mask;
336
 
337
  /* When some formats create PC relative instructions, they leave
338
     the value of the pc of the place being relocated in the offset
339
     slot of the instruction, so that a PC relative relocation can
340
     be made just by adding in an ordinary offset (e.g., sun3 a.out).
341
     Some formats leave the displacement part of an instruction
342
     empty (e.g., m88k bcs); this flag signals the fact.  */
343
  bfd_boolean pcrel_offset;
344
@};
345
 
346
@end example
347
@findex The HOWTO Macro
348
@subsubsection @code{The HOWTO Macro}
349
@strong{Description}@*
350
The HOWTO define is horrible and will go away.
351
@example
352
#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
353
  @{ (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC @}
354
@end example
355
 
356
@strong{Description}@*
357
And will be replaced with the totally magic way. But for the
358
moment, we are compatible, so do it this way.
359
@example
360
#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
361
  HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
362
         NAME, FALSE, 0, 0, IN)
363
 
364
@end example
365
 
366
@strong{Description}@*
367
This is used to fill in an empty howto entry in an array.
368
@example
369
#define EMPTY_HOWTO(C) \
370
  HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
371
         NULL, FALSE, 0, 0, FALSE)
372
 
373
@end example
374
 
375
@strong{Description}@*
376
Helper routine to turn a symbol into a relocation value.
377
@example
378
#define HOWTO_PREPARE(relocation, symbol)               \
379
  @{                                                     \
380
    if (symbol != NULL)                                 \
381
      @{                                                 \
382
        if (bfd_is_com_section (symbol->section))       \
383
          @{                                             \
384
            relocation = 0;                             \
385
          @}                                             \
386
        else                                            \
387
          @{                                             \
388
            relocation = symbol->value;                 \
389
          @}                                             \
390
      @}                                                 \
391
  @}
392
 
393
@end example
394
 
395
@findex bfd_get_reloc_size
396
@subsubsection @code{bfd_get_reloc_size}
397
@strong{Synopsis}
398
@example
399
unsigned int bfd_get_reloc_size (reloc_howto_type *);
400
@end example
401
@strong{Description}@*
402
For a reloc_howto_type that operates on a fixed number of bytes,
403
this returns the number of bytes operated on.
404
 
405
@findex arelent_chain
406
@subsubsection @code{arelent_chain}
407
@strong{Description}@*
408
How relocs are tied together in an @code{asection}:
409
@example
410
typedef struct relent_chain
411
@{
412
  arelent relent;
413
  struct relent_chain *next;
414
@}
415
arelent_chain;
416
 
417
@end example
418
 
419
@findex bfd_check_overflow
420
@subsubsection @code{bfd_check_overflow}
421
@strong{Synopsis}
422
@example
423
bfd_reloc_status_type bfd_check_overflow
424
   (enum complain_overflow how,
425
    unsigned int bitsize,
426
    unsigned int rightshift,
427
    unsigned int addrsize,
428
    bfd_vma relocation);
429
@end example
430
@strong{Description}@*
431
Perform overflow checking on @var{relocation} which has
432
@var{bitsize} significant bits and will be shifted right by
433
@var{rightshift} bits, on a machine with addresses containing
434
@var{addrsize} significant bits.  The result is either of
435
@code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
436
 
437
@findex bfd_perform_relocation
438
@subsubsection @code{bfd_perform_relocation}
439
@strong{Synopsis}
440
@example
441
bfd_reloc_status_type bfd_perform_relocation
442
   (bfd *abfd,
443
    arelent *reloc_entry,
444
    void *data,
445
    asection *input_section,
446
    bfd *output_bfd,
447
    char **error_message);
448
@end example
449
@strong{Description}@*
450
If @var{output_bfd} is supplied to this function, the
451
generated image will be relocatable; the relocations are
452
copied to the output file after they have been changed to
453
reflect the new state of the world. There are two ways of
454
reflecting the results of partial linkage in an output file:
455
by modifying the output data in place, and by modifying the
456
relocation record.  Some native formats (e.g., basic a.out and
457
basic coff) have no way of specifying an addend in the
458
relocation type, so the addend has to go in the output data.
459
This is no big deal since in these formats the output data
460
slot will always be big enough for the addend. Complex reloc
461
types with addends were invented to solve just this problem.
462
The @var{error_message} argument is set to an error message if
463
this return @code{bfd_reloc_dangerous}.
464
 
465
@findex bfd_install_relocation
466
@subsubsection @code{bfd_install_relocation}
467
@strong{Synopsis}
468
@example
469
bfd_reloc_status_type bfd_install_relocation
470
   (bfd *abfd,
471
    arelent *reloc_entry,
472
    void *data, bfd_vma data_start,
473
    asection *input_section,
474
    char **error_message);
475
@end example
476
@strong{Description}@*
477
This looks remarkably like @code{bfd_perform_relocation}, except it
478
does not expect that the section contents have been filled in.
479
I.e., it's suitable for use when creating, rather than applying
480
a relocation.
481
 
482
For now, this function should be considered reserved for the
483
assembler.
484
 
485
 
486
@node howto manager,  , typedef arelent, Relocations
487
@subsection The howto manager
488
When an application wants to create a relocation, but doesn't
489
know what the target machine might call it, it can find out by
490
using this bit of code.
491
 
492
@findex bfd_reloc_code_type
493
@subsubsection @code{bfd_reloc_code_type}
494
@strong{Description}@*
495
The insides of a reloc code.  The idea is that, eventually, there
496
will be one enumerator for every type of relocation we ever do.
497
Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll
498
return a howto pointer.
499
 
500
This does mean that the application must determine the correct
501
enumerator value; you can't get a howto pointer from a random set
502
of attributes.
503
 
504
Here are the possible values for @code{enum bfd_reloc_code_real}:
505
 
506
@deffn {} BFD_RELOC_64
507
@deffnx {} BFD_RELOC_32
508
@deffnx {} BFD_RELOC_26
509
@deffnx {} BFD_RELOC_24
510
@deffnx {} BFD_RELOC_16
511
@deffnx {} BFD_RELOC_14
512
@deffnx {} BFD_RELOC_8
513
Basic absolute relocations of N bits.
514
@end deffn
515
@deffn {} BFD_RELOC_64_PCREL
516
@deffnx {} BFD_RELOC_32_PCREL
517
@deffnx {} BFD_RELOC_24_PCREL
518
@deffnx {} BFD_RELOC_16_PCREL
519
@deffnx {} BFD_RELOC_12_PCREL
520
@deffnx {} BFD_RELOC_8_PCREL
521
PC-relative relocations.  Sometimes these are relative to the address
522
of the relocation itself; sometimes they are relative to the start of
523
the section containing the relocation.  It depends on the specific target.
524
 
525
The 24-bit relocation is used in some Intel 960 configurations.
526
@end deffn
527
@deffn {} BFD_RELOC_32_SECREL
528
Section relative relocations.  Some targets need this for DWARF2.
529
@end deffn
530
@deffn {} BFD_RELOC_32_GOT_PCREL
531
@deffnx {} BFD_RELOC_16_GOT_PCREL
532
@deffnx {} BFD_RELOC_8_GOT_PCREL
533
@deffnx {} BFD_RELOC_32_GOTOFF
534
@deffnx {} BFD_RELOC_16_GOTOFF
535
@deffnx {} BFD_RELOC_LO16_GOTOFF
536
@deffnx {} BFD_RELOC_HI16_GOTOFF
537
@deffnx {} BFD_RELOC_HI16_S_GOTOFF
538
@deffnx {} BFD_RELOC_8_GOTOFF
539
@deffnx {} BFD_RELOC_64_PLT_PCREL
540
@deffnx {} BFD_RELOC_32_PLT_PCREL
541
@deffnx {} BFD_RELOC_24_PLT_PCREL
542
@deffnx {} BFD_RELOC_16_PLT_PCREL
543
@deffnx {} BFD_RELOC_8_PLT_PCREL
544
@deffnx {} BFD_RELOC_64_PLTOFF
545
@deffnx {} BFD_RELOC_32_PLTOFF
546
@deffnx {} BFD_RELOC_16_PLTOFF
547
@deffnx {} BFD_RELOC_LO16_PLTOFF
548
@deffnx {} BFD_RELOC_HI16_PLTOFF
549
@deffnx {} BFD_RELOC_HI16_S_PLTOFF
550
@deffnx {} BFD_RELOC_8_PLTOFF
551
For ELF.
552
@end deffn
553
@deffn {} BFD_RELOC_68K_GLOB_DAT
554
@deffnx {} BFD_RELOC_68K_JMP_SLOT
555
@deffnx {} BFD_RELOC_68K_RELATIVE
556
@deffnx {} BFD_RELOC_68K_TLS_GD32
557
@deffnx {} BFD_RELOC_68K_TLS_GD16
558
@deffnx {} BFD_RELOC_68K_TLS_GD8
559
@deffnx {} BFD_RELOC_68K_TLS_LDM32
560
@deffnx {} BFD_RELOC_68K_TLS_LDM16
561
@deffnx {} BFD_RELOC_68K_TLS_LDM8
562
@deffnx {} BFD_RELOC_68K_TLS_LDO32
563
@deffnx {} BFD_RELOC_68K_TLS_LDO16
564
@deffnx {} BFD_RELOC_68K_TLS_LDO8
565
@deffnx {} BFD_RELOC_68K_TLS_IE32
566
@deffnx {} BFD_RELOC_68K_TLS_IE16
567
@deffnx {} BFD_RELOC_68K_TLS_IE8
568
@deffnx {} BFD_RELOC_68K_TLS_LE32
569
@deffnx {} BFD_RELOC_68K_TLS_LE16
570
@deffnx {} BFD_RELOC_68K_TLS_LE8
571
Relocations used by 68K ELF.
572
@end deffn
573
@deffn {} BFD_RELOC_32_BASEREL
574
@deffnx {} BFD_RELOC_16_BASEREL
575
@deffnx {} BFD_RELOC_LO16_BASEREL
576
@deffnx {} BFD_RELOC_HI16_BASEREL
577
@deffnx {} BFD_RELOC_HI16_S_BASEREL
578
@deffnx {} BFD_RELOC_8_BASEREL
579
@deffnx {} BFD_RELOC_RVA
580
Linkage-table relative.
581
@end deffn
582
@deffn {} BFD_RELOC_8_FFnn
583
Absolute 8-bit relocation, but used to form an address like 0xFFnn.
584
@end deffn
585
@deffn {} BFD_RELOC_32_PCREL_S2
586
@deffnx {} BFD_RELOC_16_PCREL_S2
587
@deffnx {} BFD_RELOC_23_PCREL_S2
588 512 jeremybenn
@deffnx {} BFD_RELOC_28_PCREL_S2
589 330 jeremybenn
These PC-relative relocations are stored as word displacements --
590
i.e., byte displacements shifted right two bits.  The 30-bit word
591
displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
592
SPARC.  (SPARC tools generally refer to this as <<WDISP30>>.)  The
593
signed 16-bit displacement is used on the MIPS, and the 23-bit
594
displacement is used on the Alpha.
595
@end deffn
596
@deffn {} BFD_RELOC_HI22
597
@deffnx {} BFD_RELOC_LO10
598
High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
599
the target word.  These are used on the SPARC.
600
@end deffn
601
@deffn {} BFD_RELOC_GPREL16
602
@deffnx {} BFD_RELOC_GPREL32
603
For systems that allocate a Global Pointer register, these are
604
displacements off that register.  These relocation types are
605
handled specially, because the value the register will have is
606
decided relatively late.
607
@end deffn
608
@deffn {} BFD_RELOC_I960_CALLJ
609
Reloc types used for i960/b.out.
610
@end deffn
611
@deffn {} BFD_RELOC_NONE
612
@deffnx {} BFD_RELOC_SPARC_WDISP22
613
@deffnx {} BFD_RELOC_SPARC22
614
@deffnx {} BFD_RELOC_SPARC13
615
@deffnx {} BFD_RELOC_SPARC_GOT10
616
@deffnx {} BFD_RELOC_SPARC_GOT13
617
@deffnx {} BFD_RELOC_SPARC_GOT22
618
@deffnx {} BFD_RELOC_SPARC_PC10
619
@deffnx {} BFD_RELOC_SPARC_PC22
620
@deffnx {} BFD_RELOC_SPARC_WPLT30
621
@deffnx {} BFD_RELOC_SPARC_COPY
622
@deffnx {} BFD_RELOC_SPARC_GLOB_DAT
623
@deffnx {} BFD_RELOC_SPARC_JMP_SLOT
624
@deffnx {} BFD_RELOC_SPARC_RELATIVE
625
@deffnx {} BFD_RELOC_SPARC_UA16
626
@deffnx {} BFD_RELOC_SPARC_UA32
627
@deffnx {} BFD_RELOC_SPARC_UA64
628
@deffnx {} BFD_RELOC_SPARC_GOTDATA_HIX22
629
@deffnx {} BFD_RELOC_SPARC_GOTDATA_LOX10
630
@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_HIX22
631
@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_LOX10
632
@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP
633
@deffnx {} BFD_RELOC_SPARC_JMP_IREL
634
@deffnx {} BFD_RELOC_SPARC_IRELATIVE
635
SPARC ELF relocations.  There is probably some overlap with other
636
relocation types already defined.
637
@end deffn
638
@deffn {} BFD_RELOC_SPARC_BASE13
639
@deffnx {} BFD_RELOC_SPARC_BASE22
640
I think these are specific to SPARC a.out (e.g., Sun 4).
641
@end deffn
642
@deffn {} BFD_RELOC_SPARC_64
643
@deffnx {} BFD_RELOC_SPARC_10
644
@deffnx {} BFD_RELOC_SPARC_11
645
@deffnx {} BFD_RELOC_SPARC_OLO10
646
@deffnx {} BFD_RELOC_SPARC_HH22
647
@deffnx {} BFD_RELOC_SPARC_HM10
648
@deffnx {} BFD_RELOC_SPARC_LM22
649
@deffnx {} BFD_RELOC_SPARC_PC_HH22
650
@deffnx {} BFD_RELOC_SPARC_PC_HM10
651
@deffnx {} BFD_RELOC_SPARC_PC_LM22
652
@deffnx {} BFD_RELOC_SPARC_WDISP16
653
@deffnx {} BFD_RELOC_SPARC_WDISP19
654
@deffnx {} BFD_RELOC_SPARC_7
655
@deffnx {} BFD_RELOC_SPARC_6
656
@deffnx {} BFD_RELOC_SPARC_5
657
@deffnx {} BFD_RELOC_SPARC_DISP64
658
@deffnx {} BFD_RELOC_SPARC_PLT32
659
@deffnx {} BFD_RELOC_SPARC_PLT64
660
@deffnx {} BFD_RELOC_SPARC_HIX22
661
@deffnx {} BFD_RELOC_SPARC_LOX10
662
@deffnx {} BFD_RELOC_SPARC_H44
663
@deffnx {} BFD_RELOC_SPARC_M44
664
@deffnx {} BFD_RELOC_SPARC_L44
665
@deffnx {} BFD_RELOC_SPARC_REGISTER
666
SPARC64 relocations
667
@end deffn
668
@deffn {} BFD_RELOC_SPARC_REV32
669
SPARC little endian relocation
670
@end deffn
671
@deffn {} BFD_RELOC_SPARC_TLS_GD_HI22
672
@deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10
673
@deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD
674
@deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL
675
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22
676
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10
677
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD
678
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL
679
@deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22
680
@deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10
681
@deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD
682
@deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22
683
@deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10
684
@deffnx {} BFD_RELOC_SPARC_TLS_IE_LD
685
@deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX
686
@deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD
687
@deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22
688
@deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10
689
@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32
690
@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64
691
@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32
692
@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64
693
@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32
694
@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64
695
SPARC TLS relocations
696
@end deffn
697
@deffn {} BFD_RELOC_SPU_IMM7
698
@deffnx {} BFD_RELOC_SPU_IMM8
699
@deffnx {} BFD_RELOC_SPU_IMM10
700
@deffnx {} BFD_RELOC_SPU_IMM10W
701
@deffnx {} BFD_RELOC_SPU_IMM16
702
@deffnx {} BFD_RELOC_SPU_IMM16W
703
@deffnx {} BFD_RELOC_SPU_IMM18
704
@deffnx {} BFD_RELOC_SPU_PCREL9a
705
@deffnx {} BFD_RELOC_SPU_PCREL9b
706
@deffnx {} BFD_RELOC_SPU_PCREL16
707
@deffnx {} BFD_RELOC_SPU_LO16
708
@deffnx {} BFD_RELOC_SPU_HI16
709
@deffnx {} BFD_RELOC_SPU_PPU32
710
@deffnx {} BFD_RELOC_SPU_PPU64
711
@deffnx {} BFD_RELOC_SPU_ADD_PIC
712
SPU Relocations.
713
@end deffn
714
@deffn {} BFD_RELOC_ALPHA_GPDISP_HI16
715
Alpha ECOFF and ELF relocations.  Some of these treat the symbol or
716
"addend" in some special way.
717
For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
718
writing; when reading, it will be the absolute section symbol.  The
719
addend is the displacement in bytes of the "lda" instruction from
720
the "ldah" instruction (which is at the address of this reloc).
721
@end deffn
722
@deffn {} BFD_RELOC_ALPHA_GPDISP_LO16
723
For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
724
with GPDISP_HI16 relocs.  The addend is ignored when writing the
725
relocations out, and is filled in with the file's GP value on
726
reading, for convenience.
727
@end deffn
728
@deffn {} BFD_RELOC_ALPHA_GPDISP
729
The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
730
relocation except that there is no accompanying GPDISP_LO16
731
relocation.
732
@end deffn
733
@deffn {} BFD_RELOC_ALPHA_LITERAL
734
@deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL
735
@deffnx {} BFD_RELOC_ALPHA_LITUSE
736
The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
737
the assembler turns it into a LDQ instruction to load the address of
738
the symbol, and then fills in a register in the real instruction.
739
 
740
The LITERAL reloc, at the LDQ instruction, refers to the .lita
741
section symbol.  The addend is ignored when writing, but is filled
742
in with the file's GP value on reading, for convenience, as with the
743
GPDISP_LO16 reloc.
744
 
745
The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
746
It should refer to the symbol to be referenced, as with 16_GOTOFF,
747
but it generates output not based on the position within the .got
748
section, but relative to the GP value chosen for the file during the
749
final link stage.
750
 
751
The LITUSE reloc, on the instruction using the loaded address, gives
752
information to the linker that it might be able to use to optimize
753
away some literal section references.  The symbol is ignored (read
754
as the absolute section symbol), and the "addend" indicates the type
755
of instruction using the register:
756
1 - "memory" fmt insn
757
2 - byte-manipulation (byte offset reg)
758
3 - jsr (target of branch)
759
@end deffn
760
@deffn {} BFD_RELOC_ALPHA_HINT
761
The HINT relocation indicates a value that should be filled into the
762
"hint" field of a jmp/jsr/ret instruction, for possible branch-
763
prediction logic which may be provided on some processors.
764
@end deffn
765
@deffn {} BFD_RELOC_ALPHA_LINKAGE
766
The LINKAGE relocation outputs a linkage pair in the object file,
767
which is filled by the linker.
768
@end deffn
769
@deffn {} BFD_RELOC_ALPHA_CODEADDR
770
The CODEADDR relocation outputs a STO_CA in the object file,
771
which is filled by the linker.
772
@end deffn
773
@deffn {} BFD_RELOC_ALPHA_GPREL_HI16
774
@deffnx {} BFD_RELOC_ALPHA_GPREL_LO16
775
The GPREL_HI/LO relocations together form a 32-bit offset from the
776
GP register.
777
@end deffn
778
@deffn {} BFD_RELOC_ALPHA_BRSGP
779
Like BFD_RELOC_23_PCREL_S2, except that the source and target must
780
share a common GP, and the target address is adjusted for
781
STO_ALPHA_STD_GPLOAD.
782
@end deffn
783
@deffn {} BFD_RELOC_ALPHA_NOP
784
The NOP relocation outputs a NOP if the longword displacement
785
between two procedure entry points is < 2^21.
786
@end deffn
787
@deffn {} BFD_RELOC_ALPHA_BSR
788
The BSR relocation outputs a BSR if the longword displacement
789
between two procedure entry points is < 2^21.
790
@end deffn
791
@deffn {} BFD_RELOC_ALPHA_LDA
792
The LDA relocation outputs a LDA if the longword displacement
793
between two procedure entry points is < 2^16.
794
@end deffn
795
@deffn {} BFD_RELOC_ALPHA_BOH
796
The BOH relocation outputs a BSR if the longword displacement
797
between two procedure entry points is < 2^21, or else a hint.
798
@end deffn
799
@deffn {} BFD_RELOC_ALPHA_TLSGD
800
@deffnx {} BFD_RELOC_ALPHA_TLSLDM
801
@deffnx {} BFD_RELOC_ALPHA_DTPMOD64
802
@deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16
803
@deffnx {} BFD_RELOC_ALPHA_DTPREL64
804
@deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16
805
@deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16
806
@deffnx {} BFD_RELOC_ALPHA_DTPREL16
807
@deffnx {} BFD_RELOC_ALPHA_GOTTPREL16
808
@deffnx {} BFD_RELOC_ALPHA_TPREL64
809
@deffnx {} BFD_RELOC_ALPHA_TPREL_HI16
810
@deffnx {} BFD_RELOC_ALPHA_TPREL_LO16
811
@deffnx {} BFD_RELOC_ALPHA_TPREL16
812
Alpha thread-local storage relocations.
813
@end deffn
814
@deffn {} BFD_RELOC_MIPS_JMP
815
Bits 27..2 of the relocation address shifted right 2 bits;
816
simple reloc otherwise.
817
@end deffn
818
@deffn {} BFD_RELOC_MIPS16_JMP
819
The MIPS16 jump instruction.
820
@end deffn
821
@deffn {} BFD_RELOC_MIPS16_GPREL
822
MIPS16 GP relative reloc.
823
@end deffn
824
@deffn {} BFD_RELOC_HI16
825
High 16 bits of 32-bit value; simple reloc.
826
@end deffn
827
@deffn {} BFD_RELOC_HI16_S
828
High 16 bits of 32-bit value but the low 16 bits will be sign
829
extended and added to form the final result.  If the low 16
830
bits form a negative number, we need to add one to the high value
831
to compensate for the borrow when the low bits are added.
832
@end deffn
833
@deffn {} BFD_RELOC_LO16
834
Low 16 bits.
835
@end deffn
836
@deffn {} BFD_RELOC_HI16_PCREL
837
High 16 bits of 32-bit pc-relative value
838
@end deffn
839
@deffn {} BFD_RELOC_HI16_S_PCREL
840
High 16 bits of 32-bit pc-relative value, adjusted
841
@end deffn
842
@deffn {} BFD_RELOC_LO16_PCREL
843
Low 16 bits of pc-relative value
844
@end deffn
845
@deffn {} BFD_RELOC_MIPS16_GOT16
846
@deffnx {} BFD_RELOC_MIPS16_CALL16
847
Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
848
16-bit immediate fields
849
@end deffn
850
@deffn {} BFD_RELOC_MIPS16_HI16
851
MIPS16 high 16 bits of 32-bit value.
852
@end deffn
853
@deffn {} BFD_RELOC_MIPS16_HI16_S
854
MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
855
extended and added to form the final result.  If the low 16
856
bits form a negative number, we need to add one to the high value
857
to compensate for the borrow when the low bits are added.
858
@end deffn
859
@deffn {} BFD_RELOC_MIPS16_LO16
860
MIPS16 low 16 bits.
861
@end deffn
862
@deffn {} BFD_RELOC_MIPS_LITERAL
863
Relocation against a MIPS literal section.
864
@end deffn
865
@deffn {} BFD_RELOC_MIPS_GOT16
866
@deffnx {} BFD_RELOC_MIPS_CALL16
867
@deffnx {} BFD_RELOC_MIPS_GOT_HI16
868
@deffnx {} BFD_RELOC_MIPS_GOT_LO16
869
@deffnx {} BFD_RELOC_MIPS_CALL_HI16
870
@deffnx {} BFD_RELOC_MIPS_CALL_LO16
871
@deffnx {} BFD_RELOC_MIPS_SUB
872
@deffnx {} BFD_RELOC_MIPS_GOT_PAGE
873
@deffnx {} BFD_RELOC_MIPS_GOT_OFST
874
@deffnx {} BFD_RELOC_MIPS_GOT_DISP
875
@deffnx {} BFD_RELOC_MIPS_SHIFT5
876
@deffnx {} BFD_RELOC_MIPS_SHIFT6
877
@deffnx {} BFD_RELOC_MIPS_INSERT_A
878
@deffnx {} BFD_RELOC_MIPS_INSERT_B
879
@deffnx {} BFD_RELOC_MIPS_DELETE
880
@deffnx {} BFD_RELOC_MIPS_HIGHEST
881
@deffnx {} BFD_RELOC_MIPS_HIGHER
882
@deffnx {} BFD_RELOC_MIPS_SCN_DISP
883
@deffnx {} BFD_RELOC_MIPS_REL16
884
@deffnx {} BFD_RELOC_MIPS_RELGOT
885
@deffnx {} BFD_RELOC_MIPS_JALR
886
@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD32
887
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL32
888
@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD64
889
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL64
890
@deffnx {} BFD_RELOC_MIPS_TLS_GD
891
@deffnx {} BFD_RELOC_MIPS_TLS_LDM
892
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_HI16
893
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_LO16
894
@deffnx {} BFD_RELOC_MIPS_TLS_GOTTPREL
895
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL32
896
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL64
897
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_HI16
898
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_LO16
899
MIPS ELF relocations.
900
@end deffn
901
@deffn {} BFD_RELOC_MIPS_COPY
902
@deffnx {} BFD_RELOC_MIPS_JUMP_SLOT
903
MIPS ELF relocations (VxWorks and PLT extensions).
904
@end deffn
905
@deffn {} BFD_RELOC_MOXIE_10_PCREL
906
Moxie ELF relocations.
907
@end deffn
908
@deffn {} BFD_RELOC_FRV_LABEL16
909
@deffnx {} BFD_RELOC_FRV_LABEL24
910
@deffnx {} BFD_RELOC_FRV_LO16
911
@deffnx {} BFD_RELOC_FRV_HI16
912
@deffnx {} BFD_RELOC_FRV_GPREL12
913
@deffnx {} BFD_RELOC_FRV_GPRELU12
914
@deffnx {} BFD_RELOC_FRV_GPREL32
915
@deffnx {} BFD_RELOC_FRV_GPRELHI
916
@deffnx {} BFD_RELOC_FRV_GPRELLO
917
@deffnx {} BFD_RELOC_FRV_GOT12
918
@deffnx {} BFD_RELOC_FRV_GOTHI
919
@deffnx {} BFD_RELOC_FRV_GOTLO
920
@deffnx {} BFD_RELOC_FRV_FUNCDESC
921
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12
922
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI
923
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO
924
@deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE
925
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12
926
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
927
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
928
@deffnx {} BFD_RELOC_FRV_GOTOFF12
929
@deffnx {} BFD_RELOC_FRV_GOTOFFHI
930
@deffnx {} BFD_RELOC_FRV_GOTOFFLO
931
@deffnx {} BFD_RELOC_FRV_GETTLSOFF
932
@deffnx {} BFD_RELOC_FRV_TLSDESC_VALUE
933
@deffnx {} BFD_RELOC_FRV_GOTTLSDESC12
934
@deffnx {} BFD_RELOC_FRV_GOTTLSDESCHI
935
@deffnx {} BFD_RELOC_FRV_GOTTLSDESCLO
936
@deffnx {} BFD_RELOC_FRV_TLSMOFF12
937
@deffnx {} BFD_RELOC_FRV_TLSMOFFHI
938
@deffnx {} BFD_RELOC_FRV_TLSMOFFLO
939
@deffnx {} BFD_RELOC_FRV_GOTTLSOFF12
940
@deffnx {} BFD_RELOC_FRV_GOTTLSOFFHI
941
@deffnx {} BFD_RELOC_FRV_GOTTLSOFFLO
942
@deffnx {} BFD_RELOC_FRV_TLSOFF
943
@deffnx {} BFD_RELOC_FRV_TLSDESC_RELAX
944
@deffnx {} BFD_RELOC_FRV_GETTLSOFF_RELAX
945
@deffnx {} BFD_RELOC_FRV_TLSOFF_RELAX
946
@deffnx {} BFD_RELOC_FRV_TLSMOFF
947
Fujitsu Frv Relocations.
948
@end deffn
949
@deffn {} BFD_RELOC_MN10300_GOTOFF24
950
This is a 24bit GOT-relative reloc for the mn10300.
951
@end deffn
952
@deffn {} BFD_RELOC_MN10300_GOT32
953
This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
954
in the instruction.
955
@end deffn
956
@deffn {} BFD_RELOC_MN10300_GOT24
957
This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
958
in the instruction.
959
@end deffn
960
@deffn {} BFD_RELOC_MN10300_GOT16
961
This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
962
in the instruction.
963
@end deffn
964
@deffn {} BFD_RELOC_MN10300_COPY
965
Copy symbol at runtime.
966
@end deffn
967
@deffn {} BFD_RELOC_MN10300_GLOB_DAT
968
Create GOT entry.
969
@end deffn
970
@deffn {} BFD_RELOC_MN10300_JMP_SLOT
971
Create PLT entry.
972
@end deffn
973
@deffn {} BFD_RELOC_MN10300_RELATIVE
974
Adjust by program base.
975
@end deffn
976
@deffn {} BFD_RELOC_MN10300_SYM_DIFF
977
Together with another reloc targeted at the same location,
978
allows for a value that is the difference of two symbols
979
in the same section.
980
@end deffn
981
@deffn {} BFD_RELOC_MN10300_ALIGN
982
The addend of this reloc is an alignment power that must
983
be honoured at the offset's location, regardless of linker
984
relaxation.
985
@end deffn
986
@deffn {} BFD_RELOC_386_GOT32
987
@deffnx {} BFD_RELOC_386_PLT32
988
@deffnx {} BFD_RELOC_386_COPY
989
@deffnx {} BFD_RELOC_386_GLOB_DAT
990
@deffnx {} BFD_RELOC_386_JUMP_SLOT
991
@deffnx {} BFD_RELOC_386_RELATIVE
992
@deffnx {} BFD_RELOC_386_GOTOFF
993
@deffnx {} BFD_RELOC_386_GOTPC
994
@deffnx {} BFD_RELOC_386_TLS_TPOFF
995
@deffnx {} BFD_RELOC_386_TLS_IE
996
@deffnx {} BFD_RELOC_386_TLS_GOTIE
997
@deffnx {} BFD_RELOC_386_TLS_LE
998
@deffnx {} BFD_RELOC_386_TLS_GD
999
@deffnx {} BFD_RELOC_386_TLS_LDM
1000
@deffnx {} BFD_RELOC_386_TLS_LDO_32
1001
@deffnx {} BFD_RELOC_386_TLS_IE_32
1002
@deffnx {} BFD_RELOC_386_TLS_LE_32
1003
@deffnx {} BFD_RELOC_386_TLS_DTPMOD32
1004
@deffnx {} BFD_RELOC_386_TLS_DTPOFF32
1005
@deffnx {} BFD_RELOC_386_TLS_TPOFF32
1006
@deffnx {} BFD_RELOC_386_TLS_GOTDESC
1007
@deffnx {} BFD_RELOC_386_TLS_DESC_CALL
1008
@deffnx {} BFD_RELOC_386_TLS_DESC
1009
@deffnx {} BFD_RELOC_386_IRELATIVE
1010
i386/elf relocations
1011
@end deffn
1012
@deffn {} BFD_RELOC_X86_64_GOT32
1013
@deffnx {} BFD_RELOC_X86_64_PLT32
1014
@deffnx {} BFD_RELOC_X86_64_COPY
1015
@deffnx {} BFD_RELOC_X86_64_GLOB_DAT
1016
@deffnx {} BFD_RELOC_X86_64_JUMP_SLOT
1017
@deffnx {} BFD_RELOC_X86_64_RELATIVE
1018
@deffnx {} BFD_RELOC_X86_64_GOTPCREL
1019
@deffnx {} BFD_RELOC_X86_64_32S
1020
@deffnx {} BFD_RELOC_X86_64_DTPMOD64
1021
@deffnx {} BFD_RELOC_X86_64_DTPOFF64
1022
@deffnx {} BFD_RELOC_X86_64_TPOFF64
1023
@deffnx {} BFD_RELOC_X86_64_TLSGD
1024
@deffnx {} BFD_RELOC_X86_64_TLSLD
1025
@deffnx {} BFD_RELOC_X86_64_DTPOFF32
1026
@deffnx {} BFD_RELOC_X86_64_GOTTPOFF
1027
@deffnx {} BFD_RELOC_X86_64_TPOFF32
1028
@deffnx {} BFD_RELOC_X86_64_GOTOFF64
1029
@deffnx {} BFD_RELOC_X86_64_GOTPC32
1030
@deffnx {} BFD_RELOC_X86_64_GOT64
1031
@deffnx {} BFD_RELOC_X86_64_GOTPCREL64
1032
@deffnx {} BFD_RELOC_X86_64_GOTPC64
1033
@deffnx {} BFD_RELOC_X86_64_GOTPLT64
1034
@deffnx {} BFD_RELOC_X86_64_PLTOFF64
1035
@deffnx {} BFD_RELOC_X86_64_GOTPC32_TLSDESC
1036
@deffnx {} BFD_RELOC_X86_64_TLSDESC_CALL
1037
@deffnx {} BFD_RELOC_X86_64_TLSDESC
1038
@deffnx {} BFD_RELOC_X86_64_IRELATIVE
1039
x86-64/elf relocations
1040
@end deffn
1041
@deffn {} BFD_RELOC_NS32K_IMM_8
1042
@deffnx {} BFD_RELOC_NS32K_IMM_16
1043
@deffnx {} BFD_RELOC_NS32K_IMM_32
1044
@deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL
1045
@deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL
1046
@deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL
1047
@deffnx {} BFD_RELOC_NS32K_DISP_8
1048
@deffnx {} BFD_RELOC_NS32K_DISP_16
1049
@deffnx {} BFD_RELOC_NS32K_DISP_32
1050
@deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL
1051
@deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL
1052
@deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL
1053
ns32k relocations
1054
@end deffn
1055
@deffn {} BFD_RELOC_PDP11_DISP_8_PCREL
1056
@deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL
1057
PDP11 relocations
1058
@end deffn
1059
@deffn {} BFD_RELOC_PJ_CODE_HI16
1060
@deffnx {} BFD_RELOC_PJ_CODE_LO16
1061
@deffnx {} BFD_RELOC_PJ_CODE_DIR16
1062
@deffnx {} BFD_RELOC_PJ_CODE_DIR32
1063
@deffnx {} BFD_RELOC_PJ_CODE_REL16
1064
@deffnx {} BFD_RELOC_PJ_CODE_REL32
1065
Picojava relocs.  Not all of these appear in object files.
1066
@end deffn
1067
@deffn {} BFD_RELOC_PPC_B26
1068
@deffnx {} BFD_RELOC_PPC_BA26
1069
@deffnx {} BFD_RELOC_PPC_TOC16
1070
@deffnx {} BFD_RELOC_PPC_B16
1071
@deffnx {} BFD_RELOC_PPC_B16_BRTAKEN
1072
@deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN
1073
@deffnx {} BFD_RELOC_PPC_BA16
1074
@deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN
1075
@deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN
1076
@deffnx {} BFD_RELOC_PPC_COPY
1077
@deffnx {} BFD_RELOC_PPC_GLOB_DAT
1078
@deffnx {} BFD_RELOC_PPC_JMP_SLOT
1079
@deffnx {} BFD_RELOC_PPC_RELATIVE
1080
@deffnx {} BFD_RELOC_PPC_LOCAL24PC
1081
@deffnx {} BFD_RELOC_PPC_EMB_NADDR32
1082
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16
1083
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO
1084
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI
1085
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA
1086
@deffnx {} BFD_RELOC_PPC_EMB_SDAI16
1087
@deffnx {} BFD_RELOC_PPC_EMB_SDA2I16
1088
@deffnx {} BFD_RELOC_PPC_EMB_SDA2REL
1089
@deffnx {} BFD_RELOC_PPC_EMB_SDA21
1090
@deffnx {} BFD_RELOC_PPC_EMB_MRKREF
1091
@deffnx {} BFD_RELOC_PPC_EMB_RELSEC16
1092
@deffnx {} BFD_RELOC_PPC_EMB_RELST_LO
1093
@deffnx {} BFD_RELOC_PPC_EMB_RELST_HI
1094
@deffnx {} BFD_RELOC_PPC_EMB_RELST_HA
1095
@deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD
1096
@deffnx {} BFD_RELOC_PPC_EMB_RELSDA
1097
@deffnx {} BFD_RELOC_PPC64_HIGHER
1098
@deffnx {} BFD_RELOC_PPC64_HIGHER_S
1099
@deffnx {} BFD_RELOC_PPC64_HIGHEST
1100
@deffnx {} BFD_RELOC_PPC64_HIGHEST_S
1101
@deffnx {} BFD_RELOC_PPC64_TOC16_LO
1102
@deffnx {} BFD_RELOC_PPC64_TOC16_HI
1103
@deffnx {} BFD_RELOC_PPC64_TOC16_HA
1104
@deffnx {} BFD_RELOC_PPC64_TOC
1105
@deffnx {} BFD_RELOC_PPC64_PLTGOT16
1106
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO
1107
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI
1108
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA
1109
@deffnx {} BFD_RELOC_PPC64_ADDR16_DS
1110
@deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS
1111
@deffnx {} BFD_RELOC_PPC64_GOT16_DS
1112
@deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS
1113
@deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS
1114
@deffnx {} BFD_RELOC_PPC64_SECTOFF_DS
1115
@deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS
1116
@deffnx {} BFD_RELOC_PPC64_TOC16_DS
1117
@deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS
1118
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS
1119
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS
1120
Power(rs6000) and PowerPC relocations.
1121
@end deffn
1122
@deffn {} BFD_RELOC_PPC_TLS
1123
@deffnx {} BFD_RELOC_PPC_TLSGD
1124
@deffnx {} BFD_RELOC_PPC_TLSLD
1125
@deffnx {} BFD_RELOC_PPC_DTPMOD
1126
@deffnx {} BFD_RELOC_PPC_TPREL16
1127
@deffnx {} BFD_RELOC_PPC_TPREL16_LO
1128
@deffnx {} BFD_RELOC_PPC_TPREL16_HI
1129
@deffnx {} BFD_RELOC_PPC_TPREL16_HA
1130
@deffnx {} BFD_RELOC_PPC_TPREL
1131
@deffnx {} BFD_RELOC_PPC_DTPREL16
1132
@deffnx {} BFD_RELOC_PPC_DTPREL16_LO
1133
@deffnx {} BFD_RELOC_PPC_DTPREL16_HI
1134
@deffnx {} BFD_RELOC_PPC_DTPREL16_HA
1135
@deffnx {} BFD_RELOC_PPC_DTPREL
1136
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16
1137
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO
1138
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI
1139
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA
1140
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16
1141
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO
1142
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI
1143
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA
1144
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16
1145
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO
1146
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI
1147
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA
1148
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16
1149
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO
1150
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI
1151
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA
1152
@deffnx {} BFD_RELOC_PPC64_TPREL16_DS
1153
@deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS
1154
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER
1155
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA
1156
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST
1157
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA
1158
@deffnx {} BFD_RELOC_PPC64_DTPREL16_DS
1159
@deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS
1160
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER
1161
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA
1162
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST
1163
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA
1164
PowerPC and PowerPC64 thread-local storage relocations.
1165
@end deffn
1166
@deffn {} BFD_RELOC_I370_D12
1167
IBM 370/390 relocations
1168
@end deffn
1169
@deffn {} BFD_RELOC_CTOR
1170
The type of reloc used to build a constructor table - at the moment
1171
probably a 32 bit wide absolute relocation, but the target can choose.
1172
It generally does map to one of the other relocation types.
1173
@end deffn
1174
@deffn {} BFD_RELOC_ARM_PCREL_BRANCH
1175
ARM 26 bit pc-relative branch.  The lowest two bits must be zero and are
1176
not stored in the instruction.
1177
@end deffn
1178
@deffn {} BFD_RELOC_ARM_PCREL_BLX
1179
ARM 26 bit pc-relative branch.  The lowest bit must be zero and is
1180
not stored in the instruction.  The 2nd lowest bit comes from a 1 bit
1181
field in the instruction.
1182
@end deffn
1183
@deffn {} BFD_RELOC_THUMB_PCREL_BLX
1184
Thumb 22 bit pc-relative branch.  The lowest bit must be zero and is
1185
not stored in the instruction.  The 2nd lowest bit comes from a 1 bit
1186
field in the instruction.
1187
@end deffn
1188
@deffn {} BFD_RELOC_ARM_PCREL_CALL
1189
ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
1190
@end deffn
1191
@deffn {} BFD_RELOC_ARM_PCREL_JUMP
1192
ARM 26-bit pc-relative branch for B or conditional BL instruction.
1193
@end deffn
1194
@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH7
1195
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH9
1196
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12
1197
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH20
1198
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23
1199
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH25
1200
Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
1201
The lowest bit must be zero and is not stored in the instruction.
1202
Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
1203
"nn" one smaller in all cases.  Note further that BRANCH23
1204
corresponds to R_ARM_THM_CALL.
1205
@end deffn
1206
@deffn {} BFD_RELOC_ARM_OFFSET_IMM
1207
12-bit immediate offset, used in ARM-format ldr and str instructions.
1208
@end deffn
1209
@deffn {} BFD_RELOC_ARM_THUMB_OFFSET
1210
5-bit immediate offset, used in Thumb-format ldr and str instructions.
1211
@end deffn
1212
@deffn {} BFD_RELOC_ARM_TARGET1
1213
Pc-relative or absolute relocation depending on target.  Used for
1214
entries in .init_array sections.
1215
@end deffn
1216
@deffn {} BFD_RELOC_ARM_ROSEGREL32
1217
Read-only segment base relative address.
1218
@end deffn
1219
@deffn {} BFD_RELOC_ARM_SBREL32
1220
Data segment base relative address.
1221
@end deffn
1222
@deffn {} BFD_RELOC_ARM_TARGET2
1223
This reloc is used for references to RTTI data from exception handling
1224
tables.  The actual definition depends on the target.  It may be a
1225
pc-relative or some form of GOT-indirect relocation.
1226
@end deffn
1227
@deffn {} BFD_RELOC_ARM_PREL31
1228
31-bit PC relative address.
1229
@end deffn
1230
@deffn {} BFD_RELOC_ARM_MOVW
1231
@deffnx {} BFD_RELOC_ARM_MOVT
1232
@deffnx {} BFD_RELOC_ARM_MOVW_PCREL
1233
@deffnx {} BFD_RELOC_ARM_MOVT_PCREL
1234
@deffnx {} BFD_RELOC_ARM_THUMB_MOVW
1235
@deffnx {} BFD_RELOC_ARM_THUMB_MOVT
1236
@deffnx {} BFD_RELOC_ARM_THUMB_MOVW_PCREL
1237
@deffnx {} BFD_RELOC_ARM_THUMB_MOVT_PCREL
1238
Low and High halfword relocations for MOVW and MOVT instructions.
1239
@end deffn
1240
@deffn {} BFD_RELOC_ARM_JUMP_SLOT
1241
@deffnx {} BFD_RELOC_ARM_GLOB_DAT
1242
@deffnx {} BFD_RELOC_ARM_GOT32
1243
@deffnx {} BFD_RELOC_ARM_PLT32
1244
@deffnx {} BFD_RELOC_ARM_RELATIVE
1245
@deffnx {} BFD_RELOC_ARM_GOTOFF
1246
@deffnx {} BFD_RELOC_ARM_GOTPC
1247
@deffnx {} BFD_RELOC_ARM_GOT_PREL
1248
Relocations for setting up GOTs and PLTs for shared libraries.
1249
@end deffn
1250
@deffn {} BFD_RELOC_ARM_TLS_GD32
1251
@deffnx {} BFD_RELOC_ARM_TLS_LDO32
1252
@deffnx {} BFD_RELOC_ARM_TLS_LDM32
1253
@deffnx {} BFD_RELOC_ARM_TLS_DTPOFF32
1254
@deffnx {} BFD_RELOC_ARM_TLS_DTPMOD32
1255
@deffnx {} BFD_RELOC_ARM_TLS_TPOFF32
1256
@deffnx {} BFD_RELOC_ARM_TLS_IE32
1257
@deffnx {} BFD_RELOC_ARM_TLS_LE32
1258
ARM thread-local storage relocations.
1259
@end deffn
1260
@deffn {} BFD_RELOC_ARM_ALU_PC_G0_NC
1261
@deffnx {} BFD_RELOC_ARM_ALU_PC_G0
1262
@deffnx {} BFD_RELOC_ARM_ALU_PC_G1_NC
1263
@deffnx {} BFD_RELOC_ARM_ALU_PC_G1
1264
@deffnx {} BFD_RELOC_ARM_ALU_PC_G2
1265
@deffnx {} BFD_RELOC_ARM_LDR_PC_G0
1266
@deffnx {} BFD_RELOC_ARM_LDR_PC_G1
1267
@deffnx {} BFD_RELOC_ARM_LDR_PC_G2
1268
@deffnx {} BFD_RELOC_ARM_LDRS_PC_G0
1269
@deffnx {} BFD_RELOC_ARM_LDRS_PC_G1
1270
@deffnx {} BFD_RELOC_ARM_LDRS_PC_G2
1271
@deffnx {} BFD_RELOC_ARM_LDC_PC_G0
1272
@deffnx {} BFD_RELOC_ARM_LDC_PC_G1
1273
@deffnx {} BFD_RELOC_ARM_LDC_PC_G2
1274
@deffnx {} BFD_RELOC_ARM_ALU_SB_G0_NC
1275
@deffnx {} BFD_RELOC_ARM_ALU_SB_G0
1276
@deffnx {} BFD_RELOC_ARM_ALU_SB_G1_NC
1277
@deffnx {} BFD_RELOC_ARM_ALU_SB_G1
1278
@deffnx {} BFD_RELOC_ARM_ALU_SB_G2
1279
@deffnx {} BFD_RELOC_ARM_LDR_SB_G0
1280
@deffnx {} BFD_RELOC_ARM_LDR_SB_G1
1281
@deffnx {} BFD_RELOC_ARM_LDR_SB_G2
1282
@deffnx {} BFD_RELOC_ARM_LDRS_SB_G0
1283
@deffnx {} BFD_RELOC_ARM_LDRS_SB_G1
1284
@deffnx {} BFD_RELOC_ARM_LDRS_SB_G2
1285
@deffnx {} BFD_RELOC_ARM_LDC_SB_G0
1286
@deffnx {} BFD_RELOC_ARM_LDC_SB_G1
1287
@deffnx {} BFD_RELOC_ARM_LDC_SB_G2
1288
ARM group relocations.
1289
@end deffn
1290
@deffn {} BFD_RELOC_ARM_V4BX
1291
Annotation of BX instructions.
1292
@end deffn
1293
@deffn {} BFD_RELOC_ARM_IMMEDIATE
1294
@deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE
1295
@deffnx {} BFD_RELOC_ARM_T32_IMMEDIATE
1296
@deffnx {} BFD_RELOC_ARM_T32_ADD_IMM
1297
@deffnx {} BFD_RELOC_ARM_T32_IMM12
1298
@deffnx {} BFD_RELOC_ARM_T32_ADD_PC12
1299
@deffnx {} BFD_RELOC_ARM_SHIFT_IMM
1300
@deffnx {} BFD_RELOC_ARM_SMC
1301
@deffnx {} BFD_RELOC_ARM_SWI
1302
@deffnx {} BFD_RELOC_ARM_MULTI
1303
@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM
1304
@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2
1305
@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM
1306
@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
1307
@deffnx {} BFD_RELOC_ARM_ADR_IMM
1308
@deffnx {} BFD_RELOC_ARM_LDR_IMM
1309
@deffnx {} BFD_RELOC_ARM_LITERAL
1310
@deffnx {} BFD_RELOC_ARM_IN_POOL
1311
@deffnx {} BFD_RELOC_ARM_OFFSET_IMM8
1312
@deffnx {} BFD_RELOC_ARM_T32_OFFSET_U8
1313
@deffnx {} BFD_RELOC_ARM_T32_OFFSET_IMM
1314
@deffnx {} BFD_RELOC_ARM_HWLITERAL
1315
@deffnx {} BFD_RELOC_ARM_THUMB_ADD
1316
@deffnx {} BFD_RELOC_ARM_THUMB_IMM
1317
@deffnx {} BFD_RELOC_ARM_THUMB_SHIFT
1318
These relocs are only used within the ARM assembler.  They are not
1319
(at present) written to any object files.
1320
@end deffn
1321
@deffn {} BFD_RELOC_SH_PCDISP8BY2
1322
@deffnx {} BFD_RELOC_SH_PCDISP12BY2
1323
@deffnx {} BFD_RELOC_SH_IMM3
1324
@deffnx {} BFD_RELOC_SH_IMM3U
1325
@deffnx {} BFD_RELOC_SH_DISP12
1326
@deffnx {} BFD_RELOC_SH_DISP12BY2
1327
@deffnx {} BFD_RELOC_SH_DISP12BY4
1328
@deffnx {} BFD_RELOC_SH_DISP12BY8
1329
@deffnx {} BFD_RELOC_SH_DISP20
1330
@deffnx {} BFD_RELOC_SH_DISP20BY8
1331
@deffnx {} BFD_RELOC_SH_IMM4
1332
@deffnx {} BFD_RELOC_SH_IMM4BY2
1333
@deffnx {} BFD_RELOC_SH_IMM4BY4
1334
@deffnx {} BFD_RELOC_SH_IMM8
1335
@deffnx {} BFD_RELOC_SH_IMM8BY2
1336
@deffnx {} BFD_RELOC_SH_IMM8BY4
1337
@deffnx {} BFD_RELOC_SH_PCRELIMM8BY2
1338
@deffnx {} BFD_RELOC_SH_PCRELIMM8BY4
1339
@deffnx {} BFD_RELOC_SH_SWITCH16
1340
@deffnx {} BFD_RELOC_SH_SWITCH32
1341
@deffnx {} BFD_RELOC_SH_USES
1342
@deffnx {} BFD_RELOC_SH_COUNT
1343
@deffnx {} BFD_RELOC_SH_ALIGN
1344
@deffnx {} BFD_RELOC_SH_CODE
1345
@deffnx {} BFD_RELOC_SH_DATA
1346
@deffnx {} BFD_RELOC_SH_LABEL
1347
@deffnx {} BFD_RELOC_SH_LOOP_START
1348
@deffnx {} BFD_RELOC_SH_LOOP_END
1349
@deffnx {} BFD_RELOC_SH_COPY
1350
@deffnx {} BFD_RELOC_SH_GLOB_DAT
1351
@deffnx {} BFD_RELOC_SH_JMP_SLOT
1352
@deffnx {} BFD_RELOC_SH_RELATIVE
1353
@deffnx {} BFD_RELOC_SH_GOTPC
1354
@deffnx {} BFD_RELOC_SH_GOT_LOW16
1355
@deffnx {} BFD_RELOC_SH_GOT_MEDLOW16
1356
@deffnx {} BFD_RELOC_SH_GOT_MEDHI16
1357
@deffnx {} BFD_RELOC_SH_GOT_HI16
1358
@deffnx {} BFD_RELOC_SH_GOTPLT_LOW16
1359
@deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16
1360
@deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16
1361
@deffnx {} BFD_RELOC_SH_GOTPLT_HI16
1362
@deffnx {} BFD_RELOC_SH_PLT_LOW16
1363
@deffnx {} BFD_RELOC_SH_PLT_MEDLOW16
1364
@deffnx {} BFD_RELOC_SH_PLT_MEDHI16
1365
@deffnx {} BFD_RELOC_SH_PLT_HI16
1366
@deffnx {} BFD_RELOC_SH_GOTOFF_LOW16
1367
@deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16
1368
@deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16
1369
@deffnx {} BFD_RELOC_SH_GOTOFF_HI16
1370
@deffnx {} BFD_RELOC_SH_GOTPC_LOW16
1371
@deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16
1372
@deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16
1373
@deffnx {} BFD_RELOC_SH_GOTPC_HI16
1374
@deffnx {} BFD_RELOC_SH_COPY64
1375
@deffnx {} BFD_RELOC_SH_GLOB_DAT64
1376
@deffnx {} BFD_RELOC_SH_JMP_SLOT64
1377
@deffnx {} BFD_RELOC_SH_RELATIVE64
1378
@deffnx {} BFD_RELOC_SH_GOT10BY4
1379
@deffnx {} BFD_RELOC_SH_GOT10BY8
1380
@deffnx {} BFD_RELOC_SH_GOTPLT10BY4
1381
@deffnx {} BFD_RELOC_SH_GOTPLT10BY8
1382
@deffnx {} BFD_RELOC_SH_GOTPLT32
1383
@deffnx {} BFD_RELOC_SH_SHMEDIA_CODE
1384
@deffnx {} BFD_RELOC_SH_IMMU5
1385
@deffnx {} BFD_RELOC_SH_IMMS6
1386
@deffnx {} BFD_RELOC_SH_IMMS6BY32
1387
@deffnx {} BFD_RELOC_SH_IMMU6
1388
@deffnx {} BFD_RELOC_SH_IMMS10
1389
@deffnx {} BFD_RELOC_SH_IMMS10BY2
1390
@deffnx {} BFD_RELOC_SH_IMMS10BY4
1391
@deffnx {} BFD_RELOC_SH_IMMS10BY8
1392
@deffnx {} BFD_RELOC_SH_IMMS16
1393
@deffnx {} BFD_RELOC_SH_IMMU16
1394
@deffnx {} BFD_RELOC_SH_IMM_LOW16
1395
@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL
1396
@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16
1397
@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL
1398
@deffnx {} BFD_RELOC_SH_IMM_MEDHI16
1399
@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL
1400
@deffnx {} BFD_RELOC_SH_IMM_HI16
1401
@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL
1402
@deffnx {} BFD_RELOC_SH_PT_16
1403
@deffnx {} BFD_RELOC_SH_TLS_GD_32
1404
@deffnx {} BFD_RELOC_SH_TLS_LD_32
1405
@deffnx {} BFD_RELOC_SH_TLS_LDO_32
1406
@deffnx {} BFD_RELOC_SH_TLS_IE_32
1407
@deffnx {} BFD_RELOC_SH_TLS_LE_32
1408
@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32
1409
@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32
1410
@deffnx {} BFD_RELOC_SH_TLS_TPOFF32
1411
@deffnx {} BFD_RELOC_SH_GOT20
1412
@deffnx {} BFD_RELOC_SH_GOTOFF20
1413
@deffnx {} BFD_RELOC_SH_GOTFUNCDESC
1414
@deffnx {} BFD_RELOC_SH_GOTFUNCDESC20
1415
@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC
1416
@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC20
1417
@deffnx {} BFD_RELOC_SH_FUNCDESC
1418
Renesas / SuperH SH relocs.  Not all of these appear in object files.
1419
@end deffn
1420
@deffn {} BFD_RELOC_ARC_B22_PCREL
1421
ARC Cores relocs.
1422
ARC 22 bit pc-relative branch.  The lowest two bits must be zero and are
1423
not stored in the instruction.  The high 20 bits are installed in bits 26
1424
through 7 of the instruction.
1425
@end deffn
1426
@deffn {} BFD_RELOC_ARC_B26
1427
ARC 26 bit absolute branch.  The lowest two bits must be zero and are not
1428
stored in the instruction.  The high 24 bits are installed in bits 23
1429
through 0.
1430
@end deffn
1431
@deffn {} BFD_RELOC_BFIN_16_IMM
1432
ADI Blackfin 16 bit immediate absolute reloc.
1433
@end deffn
1434
@deffn {} BFD_RELOC_BFIN_16_HIGH
1435
ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
1436
@end deffn
1437
@deffn {} BFD_RELOC_BFIN_4_PCREL
1438
ADI Blackfin 'a' part of LSETUP.
1439
@end deffn
1440
@deffn {} BFD_RELOC_BFIN_5_PCREL
1441
ADI Blackfin.
1442
@end deffn
1443
@deffn {} BFD_RELOC_BFIN_16_LOW
1444
ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
1445
@end deffn
1446
@deffn {} BFD_RELOC_BFIN_10_PCREL
1447
ADI Blackfin.
1448
@end deffn
1449
@deffn {} BFD_RELOC_BFIN_11_PCREL
1450
ADI Blackfin 'b' part of LSETUP.
1451
@end deffn
1452
@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP
1453
ADI Blackfin.
1454
@end deffn
1455
@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP_S
1456
ADI Blackfin Short jump, pcrel.
1457
@end deffn
1458
@deffn {} BFD_RELOC_BFIN_24_PCREL_CALL_X
1459
ADI Blackfin Call.x not implemented.
1460
@end deffn
1461
@deffn {} BFD_RELOC_BFIN_24_PCREL_JUMP_L
1462
ADI Blackfin Long Jump pcrel.
1463
@end deffn
1464
@deffn {} BFD_RELOC_BFIN_GOT17M4
1465
@deffnx {} BFD_RELOC_BFIN_GOTHI
1466
@deffnx {} BFD_RELOC_BFIN_GOTLO
1467
@deffnx {} BFD_RELOC_BFIN_FUNCDESC
1468
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOT17M4
1469
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTHI
1470
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTLO
1471
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_VALUE
1472
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
1473
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
1474
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
1475
@deffnx {} BFD_RELOC_BFIN_GOTOFF17M4
1476
@deffnx {} BFD_RELOC_BFIN_GOTOFFHI
1477
@deffnx {} BFD_RELOC_BFIN_GOTOFFLO
1478
ADI Blackfin FD-PIC relocations.
1479
@end deffn
1480
@deffn {} BFD_RELOC_BFIN_GOT
1481
ADI Blackfin GOT relocation.
1482
@end deffn
1483
@deffn {} BFD_RELOC_BFIN_PLTPC
1484
ADI Blackfin PLTPC relocation.
1485
@end deffn
1486
@deffn {} BFD_ARELOC_BFIN_PUSH
1487
ADI Blackfin arithmetic relocation.
1488
@end deffn
1489
@deffn {} BFD_ARELOC_BFIN_CONST
1490
ADI Blackfin arithmetic relocation.
1491
@end deffn
1492
@deffn {} BFD_ARELOC_BFIN_ADD
1493
ADI Blackfin arithmetic relocation.
1494
@end deffn
1495
@deffn {} BFD_ARELOC_BFIN_SUB
1496
ADI Blackfin arithmetic relocation.
1497
@end deffn
1498
@deffn {} BFD_ARELOC_BFIN_MULT
1499
ADI Blackfin arithmetic relocation.
1500
@end deffn
1501
@deffn {} BFD_ARELOC_BFIN_DIV
1502
ADI Blackfin arithmetic relocation.
1503
@end deffn
1504
@deffn {} BFD_ARELOC_BFIN_MOD
1505
ADI Blackfin arithmetic relocation.
1506
@end deffn
1507
@deffn {} BFD_ARELOC_BFIN_LSHIFT
1508
ADI Blackfin arithmetic relocation.
1509
@end deffn
1510
@deffn {} BFD_ARELOC_BFIN_RSHIFT
1511
ADI Blackfin arithmetic relocation.
1512
@end deffn
1513
@deffn {} BFD_ARELOC_BFIN_AND
1514
ADI Blackfin arithmetic relocation.
1515
@end deffn
1516
@deffn {} BFD_ARELOC_BFIN_OR
1517
ADI Blackfin arithmetic relocation.
1518
@end deffn
1519
@deffn {} BFD_ARELOC_BFIN_XOR
1520
ADI Blackfin arithmetic relocation.
1521
@end deffn
1522
@deffn {} BFD_ARELOC_BFIN_LAND
1523
ADI Blackfin arithmetic relocation.
1524
@end deffn
1525
@deffn {} BFD_ARELOC_BFIN_LOR
1526
ADI Blackfin arithmetic relocation.
1527
@end deffn
1528
@deffn {} BFD_ARELOC_BFIN_LEN
1529
ADI Blackfin arithmetic relocation.
1530
@end deffn
1531
@deffn {} BFD_ARELOC_BFIN_NEG
1532
ADI Blackfin arithmetic relocation.
1533
@end deffn
1534
@deffn {} BFD_ARELOC_BFIN_COMP
1535
ADI Blackfin arithmetic relocation.
1536
@end deffn
1537
@deffn {} BFD_ARELOC_BFIN_PAGE
1538
ADI Blackfin arithmetic relocation.
1539
@end deffn
1540
@deffn {} BFD_ARELOC_BFIN_HWPAGE
1541
ADI Blackfin arithmetic relocation.
1542
@end deffn
1543
@deffn {} BFD_ARELOC_BFIN_ADDR
1544
ADI Blackfin arithmetic relocation.
1545
@end deffn
1546
@deffn {} BFD_RELOC_D10V_10_PCREL_R
1547
Mitsubishi D10V relocs.
1548
This is a 10-bit reloc with the right 2 bits
1549
assumed to be 0.
1550
@end deffn
1551
@deffn {} BFD_RELOC_D10V_10_PCREL_L
1552
Mitsubishi D10V relocs.
1553
This is a 10-bit reloc with the right 2 bits
1554
assumed to be 0.  This is the same as the previous reloc
1555
except it is in the left container, i.e.,
1556
shifted left 15 bits.
1557
@end deffn
1558
@deffn {} BFD_RELOC_D10V_18
1559
This is an 18-bit reloc with the right 2 bits
1560
assumed to be 0.
1561
@end deffn
1562
@deffn {} BFD_RELOC_D10V_18_PCREL
1563
This is an 18-bit reloc with the right 2 bits
1564
assumed to be 0.
1565
@end deffn
1566
@deffn {} BFD_RELOC_D30V_6
1567
Mitsubishi D30V relocs.
1568
This is a 6-bit absolute reloc.
1569
@end deffn
1570
@deffn {} BFD_RELOC_D30V_9_PCREL
1571
This is a 6-bit pc-relative reloc with
1572
the right 3 bits assumed to be 0.
1573
@end deffn
1574
@deffn {} BFD_RELOC_D30V_9_PCREL_R
1575
This is a 6-bit pc-relative reloc with
1576
the right 3 bits assumed to be 0. Same
1577
as the previous reloc but on the right side
1578
of the container.
1579
@end deffn
1580
@deffn {} BFD_RELOC_D30V_15
1581
This is a 12-bit absolute reloc with the
1582
right 3 bitsassumed to be 0.
1583
@end deffn
1584
@deffn {} BFD_RELOC_D30V_15_PCREL
1585
This is a 12-bit pc-relative reloc with
1586
the right 3 bits assumed to be 0.
1587
@end deffn
1588
@deffn {} BFD_RELOC_D30V_15_PCREL_R
1589
This is a 12-bit pc-relative reloc with
1590
the right 3 bits assumed to be 0. Same
1591
as the previous reloc but on the right side
1592
of the container.
1593
@end deffn
1594
@deffn {} BFD_RELOC_D30V_21
1595
This is an 18-bit absolute reloc with
1596
the right 3 bits assumed to be 0.
1597
@end deffn
1598
@deffn {} BFD_RELOC_D30V_21_PCREL
1599
This is an 18-bit pc-relative reloc with
1600
the right 3 bits assumed to be 0.
1601
@end deffn
1602
@deffn {} BFD_RELOC_D30V_21_PCREL_R
1603
This is an 18-bit pc-relative reloc with
1604
the right 3 bits assumed to be 0. Same
1605
as the previous reloc but on the right side
1606
of the container.
1607
@end deffn
1608
@deffn {} BFD_RELOC_D30V_32
1609
This is a 32-bit absolute reloc.
1610
@end deffn
1611
@deffn {} BFD_RELOC_D30V_32_PCREL
1612
This is a 32-bit pc-relative reloc.
1613
@end deffn
1614
@deffn {} BFD_RELOC_DLX_HI16_S
1615
DLX relocs
1616
@end deffn
1617
@deffn {} BFD_RELOC_DLX_LO16
1618
DLX relocs
1619
@end deffn
1620
@deffn {} BFD_RELOC_DLX_JMP26
1621
DLX relocs
1622
@end deffn
1623
@deffn {} BFD_RELOC_M32C_HI8
1624
@deffnx {} BFD_RELOC_M32C_RL_JUMP
1625
@deffnx {} BFD_RELOC_M32C_RL_1ADDR
1626
@deffnx {} BFD_RELOC_M32C_RL_2ADDR
1627
Renesas M16C/M32C Relocations.
1628
@end deffn
1629
@deffn {} BFD_RELOC_M32R_24
1630
Renesas M32R (formerly Mitsubishi M32R) relocs.
1631
This is a 24 bit absolute address.
1632
@end deffn
1633
@deffn {} BFD_RELOC_M32R_10_PCREL
1634
This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
1635
@end deffn
1636
@deffn {} BFD_RELOC_M32R_18_PCREL
1637
This is an 18-bit reloc with the right 2 bits assumed to be 0.
1638
@end deffn
1639
@deffn {} BFD_RELOC_M32R_26_PCREL
1640
This is a 26-bit reloc with the right 2 bits assumed to be 0.
1641
@end deffn
1642
@deffn {} BFD_RELOC_M32R_HI16_ULO
1643
This is a 16-bit reloc containing the high 16 bits of an address
1644
used when the lower 16 bits are treated as unsigned.
1645
@end deffn
1646
@deffn {} BFD_RELOC_M32R_HI16_SLO
1647
This is a 16-bit reloc containing the high 16 bits of an address
1648
used when the lower 16 bits are treated as signed.
1649
@end deffn
1650
@deffn {} BFD_RELOC_M32R_LO16
1651
This is a 16-bit reloc containing the lower 16 bits of an address.
1652
@end deffn
1653
@deffn {} BFD_RELOC_M32R_SDA16
1654
This is a 16-bit reloc containing the small data area offset for use in
1655
add3, load, and store instructions.
1656
@end deffn
1657
@deffn {} BFD_RELOC_M32R_GOT24
1658
@deffnx {} BFD_RELOC_M32R_26_PLTREL
1659
@deffnx {} BFD_RELOC_M32R_COPY
1660
@deffnx {} BFD_RELOC_M32R_GLOB_DAT
1661
@deffnx {} BFD_RELOC_M32R_JMP_SLOT
1662
@deffnx {} BFD_RELOC_M32R_RELATIVE
1663
@deffnx {} BFD_RELOC_M32R_GOTOFF
1664
@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_ULO
1665
@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_SLO
1666
@deffnx {} BFD_RELOC_M32R_GOTOFF_LO
1667
@deffnx {} BFD_RELOC_M32R_GOTPC24
1668
@deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO
1669
@deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO
1670
@deffnx {} BFD_RELOC_M32R_GOT16_LO
1671
@deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO
1672
@deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO
1673
@deffnx {} BFD_RELOC_M32R_GOTPC_LO
1674
For PIC.
1675
@end deffn
1676
@deffn {} BFD_RELOC_V850_9_PCREL
1677
This is a 9-bit reloc
1678
@end deffn
1679
@deffn {} BFD_RELOC_V850_22_PCREL
1680
This is a 22-bit reloc
1681
@end deffn
1682
@deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET
1683
This is a 16 bit offset from the short data area pointer.
1684
@end deffn
1685
@deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET
1686
This is a 16 bit offset (of which only 15 bits are used) from the
1687
short data area pointer.
1688
@end deffn
1689
@deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET
1690
This is a 16 bit offset from the zero data area pointer.
1691
@end deffn
1692
@deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET
1693
This is a 16 bit offset (of which only 15 bits are used) from the
1694
zero data area pointer.
1695
@end deffn
1696
@deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET
1697
This is an 8 bit offset (of which only 6 bits are used) from the
1698
tiny data area pointer.
1699
@end deffn
1700
@deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET
1701
This is an 8bit offset (of which only 7 bits are used) from the tiny
1702
data area pointer.
1703
@end deffn
1704
@deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET
1705
This is a 7 bit offset from the tiny data area pointer.
1706
@end deffn
1707
@deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET
1708
This is a 16 bit offset from the tiny data area pointer.
1709
@end deffn
1710
@deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET
1711
This is a 5 bit offset (of which only 4 bits are used) from the tiny
1712
data area pointer.
1713
@end deffn
1714
@deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET
1715
This is a 4 bit offset from the tiny data area pointer.
1716
@end deffn
1717
@deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
1718
This is a 16 bit offset from the short data area pointer, with the
1719
bits placed non-contiguously in the instruction.
1720
@end deffn
1721
@deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
1722
This is a 16 bit offset from the zero data area pointer, with the
1723
bits placed non-contiguously in the instruction.
1724
@end deffn
1725
@deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET
1726
This is a 6 bit offset from the call table base pointer.
1727
@end deffn
1728
@deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET
1729
This is a 16 bit offset from the call table base pointer.
1730
@end deffn
1731
@deffn {} BFD_RELOC_V850_LONGCALL
1732
Used for relaxing indirect function calls.
1733
@end deffn
1734
@deffn {} BFD_RELOC_V850_LONGJUMP
1735
Used for relaxing indirect jumps.
1736
@end deffn
1737
@deffn {} BFD_RELOC_V850_ALIGN
1738
Used to maintain alignment whilst relaxing.
1739
@end deffn
1740
@deffn {} BFD_RELOC_V850_LO16_SPLIT_OFFSET
1741
This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
1742
instructions.
1743
@end deffn
1744
@deffn {} BFD_RELOC_MN10300_32_PCREL
1745
This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
1746
instruction.
1747
@end deffn
1748
@deffn {} BFD_RELOC_MN10300_16_PCREL
1749
This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
1750
instruction.
1751
@end deffn
1752
@deffn {} BFD_RELOC_TIC30_LDP
1753
This is a 8bit DP reloc for the tms320c30, where the most
1754
significant 8 bits of a 24 bit word are placed into the least
1755
significant 8 bits of the opcode.
1756
@end deffn
1757
@deffn {} BFD_RELOC_TIC54X_PARTLS7
1758
This is a 7bit reloc for the tms320c54x, where the least
1759
significant 7 bits of a 16 bit word are placed into the least
1760
significant 7 bits of the opcode.
1761
@end deffn
1762
@deffn {} BFD_RELOC_TIC54X_PARTMS9
1763
This is a 9bit DP reloc for the tms320c54x, where the most
1764
significant 9 bits of a 16 bit word are placed into the least
1765
significant 9 bits of the opcode.
1766
@end deffn
1767
@deffn {} BFD_RELOC_TIC54X_23
1768
This is an extended address 23-bit reloc for the tms320c54x.
1769
@end deffn
1770
@deffn {} BFD_RELOC_TIC54X_16_OF_23
1771
This is a 16-bit reloc for the tms320c54x, where the least
1772
significant 16 bits of a 23-bit extended address are placed into
1773
the opcode.
1774
@end deffn
1775
@deffn {} BFD_RELOC_TIC54X_MS7_OF_23
1776
This is a reloc for the tms320c54x, where the most
1777
significant 7 bits of a 23-bit extended address are placed into
1778
the opcode.
1779
@end deffn
1780
@deffn {} BFD_RELOC_C6000_PCR_S21
1781
@deffnx {} BFD_RELOC_C6000_PCR_S12
1782
@deffnx {} BFD_RELOC_C6000_PCR_S10
1783
@deffnx {} BFD_RELOC_C6000_PCR_S7
1784
@deffnx {} BFD_RELOC_C6000_ABS_S16
1785
@deffnx {} BFD_RELOC_C6000_ABS_L16
1786
@deffnx {} BFD_RELOC_C6000_ABS_H16
1787
@deffnx {} BFD_RELOC_C6000_SBR_U15_B
1788
@deffnx {} BFD_RELOC_C6000_SBR_U15_H
1789
@deffnx {} BFD_RELOC_C6000_SBR_U15_W
1790
@deffnx {} BFD_RELOC_C6000_SBR_S16
1791
@deffnx {} BFD_RELOC_C6000_SBR_L16_B
1792
@deffnx {} BFD_RELOC_C6000_SBR_L16_H
1793
@deffnx {} BFD_RELOC_C6000_SBR_L16_W
1794
@deffnx {} BFD_RELOC_C6000_SBR_H16_B
1795
@deffnx {} BFD_RELOC_C6000_SBR_H16_H
1796
@deffnx {} BFD_RELOC_C6000_SBR_H16_W
1797
@deffnx {} BFD_RELOC_C6000_SBR_GOT_U15_W
1798
@deffnx {} BFD_RELOC_C6000_SBR_GOT_L16_W
1799
@deffnx {} BFD_RELOC_C6000_SBR_GOT_H16_W
1800
@deffnx {} BFD_RELOC_C6000_DSBT_INDEX
1801
@deffnx {} BFD_RELOC_C6000_PREL31
1802
@deffnx {} BFD_RELOC_C6000_COPY
1803
@deffnx {} BFD_RELOC_C6000_ALIGN
1804
@deffnx {} BFD_RELOC_C6000_FPHEAD
1805
@deffnx {} BFD_RELOC_C6000_NOCMP
1806
TMS320C6000 relocations.
1807
@end deffn
1808
@deffn {} BFD_RELOC_FR30_48
1809
This is a 48 bit reloc for the FR30 that stores 32 bits.
1810
@end deffn
1811
@deffn {} BFD_RELOC_FR30_20
1812
This is a 32 bit reloc for the FR30 that stores 20 bits split up into
1813
two sections.
1814
@end deffn
1815
@deffn {} BFD_RELOC_FR30_6_IN_4
1816
This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
1817
4 bits.
1818
@end deffn
1819
@deffn {} BFD_RELOC_FR30_8_IN_8
1820
This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
1821
into 8 bits.
1822
@end deffn
1823
@deffn {} BFD_RELOC_FR30_9_IN_8
1824
This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
1825
into 8 bits.
1826
@end deffn
1827
@deffn {} BFD_RELOC_FR30_10_IN_8
1828
This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
1829
into 8 bits.
1830
@end deffn
1831
@deffn {} BFD_RELOC_FR30_9_PCREL
1832
This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
1833
short offset into 8 bits.
1834
@end deffn
1835
@deffn {} BFD_RELOC_FR30_12_PCREL
1836
This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
1837
short offset into 11 bits.
1838
@end deffn
1839
@deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4
1840
@deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2
1841
@deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2
1842
@deffnx {} BFD_RELOC_MCORE_PCREL_32
1843
@deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
1844
@deffnx {} BFD_RELOC_MCORE_RVA
1845
Motorola Mcore relocations.
1846
@end deffn
1847
@deffn {} BFD_RELOC_MEP_8
1848
@deffnx {} BFD_RELOC_MEP_16
1849
@deffnx {} BFD_RELOC_MEP_32
1850
@deffnx {} BFD_RELOC_MEP_PCREL8A2
1851
@deffnx {} BFD_RELOC_MEP_PCREL12A2
1852
@deffnx {} BFD_RELOC_MEP_PCREL17A2
1853
@deffnx {} BFD_RELOC_MEP_PCREL24A2
1854
@deffnx {} BFD_RELOC_MEP_PCABS24A2
1855
@deffnx {} BFD_RELOC_MEP_LOW16
1856
@deffnx {} BFD_RELOC_MEP_HI16U
1857
@deffnx {} BFD_RELOC_MEP_HI16S
1858
@deffnx {} BFD_RELOC_MEP_GPREL
1859
@deffnx {} BFD_RELOC_MEP_TPREL
1860
@deffnx {} BFD_RELOC_MEP_TPREL7
1861
@deffnx {} BFD_RELOC_MEP_TPREL7A2
1862
@deffnx {} BFD_RELOC_MEP_TPREL7A4
1863
@deffnx {} BFD_RELOC_MEP_UIMM24
1864
@deffnx {} BFD_RELOC_MEP_ADDR24A4
1865
@deffnx {} BFD_RELOC_MEP_GNU_VTINHERIT
1866
@deffnx {} BFD_RELOC_MEP_GNU_VTENTRY
1867
Toshiba Media Processor Relocations.
1868
@end deffn
1869
@deffn {} BFD_RELOC_MMIX_GETA
1870
@deffnx {} BFD_RELOC_MMIX_GETA_1
1871
@deffnx {} BFD_RELOC_MMIX_GETA_2
1872
@deffnx {} BFD_RELOC_MMIX_GETA_3
1873
These are relocations for the GETA instruction.
1874
@end deffn
1875
@deffn {} BFD_RELOC_MMIX_CBRANCH
1876
@deffnx {} BFD_RELOC_MMIX_CBRANCH_J
1877
@deffnx {} BFD_RELOC_MMIX_CBRANCH_1
1878
@deffnx {} BFD_RELOC_MMIX_CBRANCH_2
1879
@deffnx {} BFD_RELOC_MMIX_CBRANCH_3
1880
These are relocations for a conditional branch instruction.
1881
@end deffn
1882
@deffn {} BFD_RELOC_MMIX_PUSHJ
1883
@deffnx {} BFD_RELOC_MMIX_PUSHJ_1
1884
@deffnx {} BFD_RELOC_MMIX_PUSHJ_2
1885
@deffnx {} BFD_RELOC_MMIX_PUSHJ_3
1886
@deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE
1887
These are relocations for the PUSHJ instruction.
1888
@end deffn
1889
@deffn {} BFD_RELOC_MMIX_JMP
1890
@deffnx {} BFD_RELOC_MMIX_JMP_1
1891
@deffnx {} BFD_RELOC_MMIX_JMP_2
1892
@deffnx {} BFD_RELOC_MMIX_JMP_3
1893
These are relocations for the JMP instruction.
1894
@end deffn
1895
@deffn {} BFD_RELOC_MMIX_ADDR19
1896
This is a relocation for a relative address as in a GETA instruction or
1897
a branch.
1898
@end deffn
1899
@deffn {} BFD_RELOC_MMIX_ADDR27
1900
This is a relocation for a relative address as in a JMP instruction.
1901
@end deffn
1902
@deffn {} BFD_RELOC_MMIX_REG_OR_BYTE
1903
This is a relocation for an instruction field that may be a general
1904
register or a value 0..255.
1905
@end deffn
1906
@deffn {} BFD_RELOC_MMIX_REG
1907
This is a relocation for an instruction field that may be a general
1908
register.
1909
@end deffn
1910
@deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET
1911
This is a relocation for two instruction fields holding a register and
1912
an offset, the equivalent of the relocation.
1913
@end deffn
1914
@deffn {} BFD_RELOC_MMIX_LOCAL
1915
This relocation is an assertion that the expression is not allocated as
1916
a global register.  It does not modify contents.
1917
@end deffn
1918
@deffn {} BFD_RELOC_AVR_7_PCREL
1919
This is a 16 bit reloc for the AVR that stores 8 bit pc relative
1920
short offset into 7 bits.
1921
@end deffn
1922
@deffn {} BFD_RELOC_AVR_13_PCREL
1923
This is a 16 bit reloc for the AVR that stores 13 bit pc relative
1924
short offset into 12 bits.
1925
@end deffn
1926
@deffn {} BFD_RELOC_AVR_16_PM
1927
This is a 16 bit reloc for the AVR that stores 17 bit value (usually
1928
program memory address) into 16 bits.
1929
@end deffn
1930
@deffn {} BFD_RELOC_AVR_LO8_LDI
1931
This is a 16 bit reloc for the AVR that stores 8 bit value (usually
1932
data memory address) into 8 bit immediate value of LDI insn.
1933
@end deffn
1934
@deffn {} BFD_RELOC_AVR_HI8_LDI
1935
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1936
of data memory address) into 8 bit immediate value of LDI insn.
1937
@end deffn
1938
@deffn {} BFD_RELOC_AVR_HH8_LDI
1939
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1940
of program memory address) into 8 bit immediate value of LDI insn.
1941
@end deffn
1942
@deffn {} BFD_RELOC_AVR_MS8_LDI
1943
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1944
of 32 bit value) into 8 bit immediate value of LDI insn.
1945
@end deffn
1946
@deffn {} BFD_RELOC_AVR_LO8_LDI_NEG
1947
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1948
(usually data memory address) into 8 bit immediate value of SUBI insn.
1949
@end deffn
1950
@deffn {} BFD_RELOC_AVR_HI8_LDI_NEG
1951
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1952
(high 8 bit of data memory address) into 8 bit immediate value of
1953
SUBI insn.
1954
@end deffn
1955
@deffn {} BFD_RELOC_AVR_HH8_LDI_NEG
1956
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1957
(most high 8 bit of program memory address) into 8 bit immediate value
1958
of LDI or SUBI insn.
1959
@end deffn
1960
@deffn {} BFD_RELOC_AVR_MS8_LDI_NEG
1961
This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
1962
of 32 bit value) into 8 bit immediate value of LDI insn.
1963
@end deffn
1964
@deffn {} BFD_RELOC_AVR_LO8_LDI_PM
1965
This is a 16 bit reloc for the AVR that stores 8 bit value (usually
1966
command address) into 8 bit immediate value of LDI insn.
1967
@end deffn
1968
@deffn {} BFD_RELOC_AVR_LO8_LDI_GS
1969
This is a 16 bit reloc for the AVR that stores 8 bit value
1970
(command address) into 8 bit immediate value of LDI insn. If the address
1971
is beyond the 128k boundary, the linker inserts a jump stub for this reloc
1972
in the lower 128k.
1973
@end deffn
1974
@deffn {} BFD_RELOC_AVR_HI8_LDI_PM
1975
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1976
of command address) into 8 bit immediate value of LDI insn.
1977
@end deffn
1978
@deffn {} BFD_RELOC_AVR_HI8_LDI_GS
1979
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1980
of command address) into 8 bit immediate value of LDI insn.  If the address
1981
is beyond the 128k boundary, the linker inserts a jump stub for this reloc
1982
below 128k.
1983
@end deffn
1984
@deffn {} BFD_RELOC_AVR_HH8_LDI_PM
1985
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1986
of command address) into 8 bit immediate value of LDI insn.
1987
@end deffn
1988
@deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG
1989
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1990
(usually command address) into 8 bit immediate value of SUBI insn.
1991
@end deffn
1992
@deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG
1993
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1994
(high 8 bit of 16 bit command address) into 8 bit immediate value
1995
of SUBI insn.
1996
@end deffn
1997
@deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG
1998
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1999
(high 6 bit of 22 bit command address) into 8 bit immediate
2000
value of SUBI insn.
2001
@end deffn
2002
@deffn {} BFD_RELOC_AVR_CALL
2003
This is a 32 bit reloc for the AVR that stores 23 bit value
2004
into 22 bits.
2005
@end deffn
2006
@deffn {} BFD_RELOC_AVR_LDI
2007
This is a 16 bit reloc for the AVR that stores all needed bits
2008
for absolute addressing with ldi with overflow check to linktime
2009
@end deffn
2010
@deffn {} BFD_RELOC_AVR_6
2011
This is a 6 bit reloc for the AVR that stores offset for ldd/std
2012
instructions
2013
@end deffn
2014
@deffn {} BFD_RELOC_AVR_6_ADIW
2015
This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
2016
instructions
2017
@end deffn
2018
@deffn {} BFD_RELOC_RX_NEG8
2019
@deffnx {} BFD_RELOC_RX_NEG16
2020
@deffnx {} BFD_RELOC_RX_NEG24
2021
@deffnx {} BFD_RELOC_RX_NEG32
2022
@deffnx {} BFD_RELOC_RX_16_OP
2023
@deffnx {} BFD_RELOC_RX_24_OP
2024
@deffnx {} BFD_RELOC_RX_32_OP
2025
@deffnx {} BFD_RELOC_RX_8U
2026
@deffnx {} BFD_RELOC_RX_16U
2027
@deffnx {} BFD_RELOC_RX_24U
2028
@deffnx {} BFD_RELOC_RX_DIR3U_PCREL
2029
@deffnx {} BFD_RELOC_RX_DIFF
2030
@deffnx {} BFD_RELOC_RX_GPRELB
2031
@deffnx {} BFD_RELOC_RX_GPRELW
2032
@deffnx {} BFD_RELOC_RX_GPRELL
2033
@deffnx {} BFD_RELOC_RX_SYM
2034
@deffnx {} BFD_RELOC_RX_OP_SUBTRACT
2035
@deffnx {} BFD_RELOC_RX_ABS8
2036
@deffnx {} BFD_RELOC_RX_ABS16
2037
@deffnx {} BFD_RELOC_RX_ABS32
2038
@deffnx {} BFD_RELOC_RX_ABS16U
2039
@deffnx {} BFD_RELOC_RX_ABS16UW
2040
@deffnx {} BFD_RELOC_RX_ABS16UL
2041
@deffnx {} BFD_RELOC_RX_RELAX
2042
Renesas RX Relocations.
2043
@end deffn
2044
@deffn {} BFD_RELOC_390_12
2045
Direct 12 bit.
2046
@end deffn
2047
@deffn {} BFD_RELOC_390_GOT12
2048
12 bit GOT offset.
2049
@end deffn
2050
@deffn {} BFD_RELOC_390_PLT32
2051
32 bit PC relative PLT address.
2052
@end deffn
2053
@deffn {} BFD_RELOC_390_COPY
2054
Copy symbol at runtime.
2055
@end deffn
2056
@deffn {} BFD_RELOC_390_GLOB_DAT
2057
Create GOT entry.
2058
@end deffn
2059
@deffn {} BFD_RELOC_390_JMP_SLOT
2060
Create PLT entry.
2061
@end deffn
2062
@deffn {} BFD_RELOC_390_RELATIVE
2063
Adjust by program base.
2064
@end deffn
2065
@deffn {} BFD_RELOC_390_GOTPC
2066
32 bit PC relative offset to GOT.
2067
@end deffn
2068
@deffn {} BFD_RELOC_390_GOT16
2069
16 bit GOT offset.
2070
@end deffn
2071
@deffn {} BFD_RELOC_390_PC16DBL
2072
PC relative 16 bit shifted by 1.
2073
@end deffn
2074
@deffn {} BFD_RELOC_390_PLT16DBL
2075
16 bit PC rel. PLT shifted by 1.
2076
@end deffn
2077
@deffn {} BFD_RELOC_390_PC32DBL
2078
PC relative 32 bit shifted by 1.
2079
@end deffn
2080
@deffn {} BFD_RELOC_390_PLT32DBL
2081
32 bit PC rel. PLT shifted by 1.
2082
@end deffn
2083
@deffn {} BFD_RELOC_390_GOTPCDBL
2084
32 bit PC rel. GOT shifted by 1.
2085
@end deffn
2086
@deffn {} BFD_RELOC_390_GOT64
2087
64 bit GOT offset.
2088
@end deffn
2089
@deffn {} BFD_RELOC_390_PLT64
2090
64 bit PC relative PLT address.
2091
@end deffn
2092
@deffn {} BFD_RELOC_390_GOTENT
2093
32 bit rel. offset to GOT entry.
2094
@end deffn
2095
@deffn {} BFD_RELOC_390_GOTOFF64
2096
64 bit offset to GOT.
2097
@end deffn
2098
@deffn {} BFD_RELOC_390_GOTPLT12
2099
12-bit offset to symbol-entry within GOT, with PLT handling.
2100
@end deffn
2101
@deffn {} BFD_RELOC_390_GOTPLT16
2102
16-bit offset to symbol-entry within GOT, with PLT handling.
2103
@end deffn
2104
@deffn {} BFD_RELOC_390_GOTPLT32
2105
32-bit offset to symbol-entry within GOT, with PLT handling.
2106
@end deffn
2107
@deffn {} BFD_RELOC_390_GOTPLT64
2108
64-bit offset to symbol-entry within GOT, with PLT handling.
2109
@end deffn
2110
@deffn {} BFD_RELOC_390_GOTPLTENT
2111
32-bit rel. offset to symbol-entry within GOT, with PLT handling.
2112
@end deffn
2113
@deffn {} BFD_RELOC_390_PLTOFF16
2114
16-bit rel. offset from the GOT to a PLT entry.
2115
@end deffn
2116
@deffn {} BFD_RELOC_390_PLTOFF32
2117
32-bit rel. offset from the GOT to a PLT entry.
2118
@end deffn
2119
@deffn {} BFD_RELOC_390_PLTOFF64
2120
64-bit rel. offset from the GOT to a PLT entry.
2121
@end deffn
2122
@deffn {} BFD_RELOC_390_TLS_LOAD
2123
@deffnx {} BFD_RELOC_390_TLS_GDCALL
2124
@deffnx {} BFD_RELOC_390_TLS_LDCALL
2125
@deffnx {} BFD_RELOC_390_TLS_GD32
2126
@deffnx {} BFD_RELOC_390_TLS_GD64
2127
@deffnx {} BFD_RELOC_390_TLS_GOTIE12
2128
@deffnx {} BFD_RELOC_390_TLS_GOTIE32
2129
@deffnx {} BFD_RELOC_390_TLS_GOTIE64
2130
@deffnx {} BFD_RELOC_390_TLS_LDM32
2131
@deffnx {} BFD_RELOC_390_TLS_LDM64
2132
@deffnx {} BFD_RELOC_390_TLS_IE32
2133
@deffnx {} BFD_RELOC_390_TLS_IE64
2134
@deffnx {} BFD_RELOC_390_TLS_IEENT
2135
@deffnx {} BFD_RELOC_390_TLS_LE32
2136
@deffnx {} BFD_RELOC_390_TLS_LE64
2137
@deffnx {} BFD_RELOC_390_TLS_LDO32
2138
@deffnx {} BFD_RELOC_390_TLS_LDO64
2139
@deffnx {} BFD_RELOC_390_TLS_DTPMOD
2140
@deffnx {} BFD_RELOC_390_TLS_DTPOFF
2141
@deffnx {} BFD_RELOC_390_TLS_TPOFF
2142
s390 tls relocations.
2143
@end deffn
2144
@deffn {} BFD_RELOC_390_20
2145
@deffnx {} BFD_RELOC_390_GOT20
2146
@deffnx {} BFD_RELOC_390_GOTPLT20
2147
@deffnx {} BFD_RELOC_390_TLS_GOTIE20
2148
Long displacement extension.
2149
@end deffn
2150
@deffn {} BFD_RELOC_SCORE_GPREL15
2151
Score relocations
2152
Low 16 bit for load/store
2153
@end deffn
2154
@deffn {} BFD_RELOC_SCORE_DUMMY2
2155
@deffnx {} BFD_RELOC_SCORE_JMP
2156
This is a 24-bit reloc with the right 1 bit assumed to be 0
2157
@end deffn
2158
@deffn {} BFD_RELOC_SCORE_BRANCH
2159
This is a 19-bit reloc with the right 1 bit assumed to be 0
2160
@end deffn
2161
@deffn {} BFD_RELOC_SCORE_IMM30
2162
This is a 32-bit reloc for 48-bit instructions.
2163
@end deffn
2164
@deffn {} BFD_RELOC_SCORE_IMM32
2165
This is a 32-bit reloc for 48-bit instructions.
2166
@end deffn
2167
@deffn {} BFD_RELOC_SCORE16_JMP
2168
This is a 11-bit reloc with the right 1 bit assumed to be 0
2169
@end deffn
2170
@deffn {} BFD_RELOC_SCORE16_BRANCH
2171
This is a 8-bit reloc with the right 1 bit assumed to be 0
2172
@end deffn
2173
@deffn {} BFD_RELOC_SCORE_BCMP
2174
This is a 9-bit reloc with the right 1 bit assumed to be 0
2175
@end deffn
2176
@deffn {} BFD_RELOC_SCORE_GOT15
2177
@deffnx {} BFD_RELOC_SCORE_GOT_LO16
2178
@deffnx {} BFD_RELOC_SCORE_CALL15
2179
@deffnx {} BFD_RELOC_SCORE_DUMMY_HI16
2180
Undocumented Score relocs
2181
@end deffn
2182
@deffn {} BFD_RELOC_IP2K_FR9
2183
Scenix IP2K - 9-bit register number / data address
2184
@end deffn
2185
@deffn {} BFD_RELOC_IP2K_BANK
2186
Scenix IP2K - 4-bit register/data bank number
2187
@end deffn
2188
@deffn {} BFD_RELOC_IP2K_ADDR16CJP
2189
Scenix IP2K - low 13 bits of instruction word address
2190
@end deffn
2191
@deffn {} BFD_RELOC_IP2K_PAGE3
2192
Scenix IP2K - high 3 bits of instruction word address
2193
@end deffn
2194
@deffn {} BFD_RELOC_IP2K_LO8DATA
2195
@deffnx {} BFD_RELOC_IP2K_HI8DATA
2196
@deffnx {} BFD_RELOC_IP2K_EX8DATA
2197
Scenix IP2K - ext/low/high 8 bits of data address
2198
@end deffn
2199
@deffn {} BFD_RELOC_IP2K_LO8INSN
2200
@deffnx {} BFD_RELOC_IP2K_HI8INSN
2201
Scenix IP2K - low/high 8 bits of instruction word address
2202
@end deffn
2203
@deffn {} BFD_RELOC_IP2K_PC_SKIP
2204
Scenix IP2K - even/odd PC modifier to modify snb pcl.0
2205
@end deffn
2206
@deffn {} BFD_RELOC_IP2K_TEXT
2207
Scenix IP2K - 16 bit word address in text section.
2208
@end deffn
2209
@deffn {} BFD_RELOC_IP2K_FR_OFFSET
2210
Scenix IP2K - 7-bit sp or dp offset
2211
@end deffn
2212
@deffn {} BFD_RELOC_VPE4KMATH_DATA
2213
@deffnx {} BFD_RELOC_VPE4KMATH_INSN
2214
Scenix VPE4K coprocessor - data/insn-space addressing
2215
@end deffn
2216
@deffn {} BFD_RELOC_VTABLE_INHERIT
2217
@deffnx {} BFD_RELOC_VTABLE_ENTRY
2218
These two relocations are used by the linker to determine which of
2219
the entries in a C++ virtual function table are actually used.  When
2220
the --gc-sections option is given, the linker will zero out the entries
2221
that are not used, so that the code for those functions need not be
2222
included in the output.
2223
 
2224
VTABLE_INHERIT is a zero-space relocation used to describe to the
2225
linker the inheritance tree of a C++ virtual function table.  The
2226
relocation's symbol should be the parent class' vtable, and the
2227
relocation should be located at the child vtable.
2228
 
2229
VTABLE_ENTRY is a zero-space relocation that describes the use of a
2230
virtual function table entry.  The reloc's symbol should refer to the
2231
table of the class mentioned in the code.  Off of that base, an offset
2232
describes the entry that is being used.  For Rela hosts, this offset
2233
is stored in the reloc's addend.  For Rel hosts, we are forced to put
2234
this offset in the reloc's section offset.
2235
@end deffn
2236
@deffn {} BFD_RELOC_IA64_IMM14
2237
@deffnx {} BFD_RELOC_IA64_IMM22
2238
@deffnx {} BFD_RELOC_IA64_IMM64
2239
@deffnx {} BFD_RELOC_IA64_DIR32MSB
2240
@deffnx {} BFD_RELOC_IA64_DIR32LSB
2241
@deffnx {} BFD_RELOC_IA64_DIR64MSB
2242
@deffnx {} BFD_RELOC_IA64_DIR64LSB
2243
@deffnx {} BFD_RELOC_IA64_GPREL22
2244
@deffnx {} BFD_RELOC_IA64_GPREL64I
2245
@deffnx {} BFD_RELOC_IA64_GPREL32MSB
2246
@deffnx {} BFD_RELOC_IA64_GPREL32LSB
2247
@deffnx {} BFD_RELOC_IA64_GPREL64MSB
2248
@deffnx {} BFD_RELOC_IA64_GPREL64LSB
2249
@deffnx {} BFD_RELOC_IA64_LTOFF22
2250
@deffnx {} BFD_RELOC_IA64_LTOFF64I
2251
@deffnx {} BFD_RELOC_IA64_PLTOFF22
2252
@deffnx {} BFD_RELOC_IA64_PLTOFF64I
2253
@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB
2254
@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB
2255
@deffnx {} BFD_RELOC_IA64_FPTR64I
2256
@deffnx {} BFD_RELOC_IA64_FPTR32MSB
2257
@deffnx {} BFD_RELOC_IA64_FPTR32LSB
2258
@deffnx {} BFD_RELOC_IA64_FPTR64MSB
2259
@deffnx {} BFD_RELOC_IA64_FPTR64LSB
2260
@deffnx {} BFD_RELOC_IA64_PCREL21B
2261
@deffnx {} BFD_RELOC_IA64_PCREL21BI
2262
@deffnx {} BFD_RELOC_IA64_PCREL21M
2263
@deffnx {} BFD_RELOC_IA64_PCREL21F
2264
@deffnx {} BFD_RELOC_IA64_PCREL22
2265
@deffnx {} BFD_RELOC_IA64_PCREL60B
2266
@deffnx {} BFD_RELOC_IA64_PCREL64I
2267
@deffnx {} BFD_RELOC_IA64_PCREL32MSB
2268
@deffnx {} BFD_RELOC_IA64_PCREL32LSB
2269
@deffnx {} BFD_RELOC_IA64_PCREL64MSB
2270
@deffnx {} BFD_RELOC_IA64_PCREL64LSB
2271
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22
2272
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I
2273
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB
2274
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB
2275
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB
2276
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB
2277
@deffnx {} BFD_RELOC_IA64_SEGREL32MSB
2278
@deffnx {} BFD_RELOC_IA64_SEGREL32LSB
2279
@deffnx {} BFD_RELOC_IA64_SEGREL64MSB
2280
@deffnx {} BFD_RELOC_IA64_SEGREL64LSB
2281
@deffnx {} BFD_RELOC_IA64_SECREL32MSB
2282
@deffnx {} BFD_RELOC_IA64_SECREL32LSB
2283
@deffnx {} BFD_RELOC_IA64_SECREL64MSB
2284
@deffnx {} BFD_RELOC_IA64_SECREL64LSB
2285
@deffnx {} BFD_RELOC_IA64_REL32MSB
2286
@deffnx {} BFD_RELOC_IA64_REL32LSB
2287
@deffnx {} BFD_RELOC_IA64_REL64MSB
2288
@deffnx {} BFD_RELOC_IA64_REL64LSB
2289
@deffnx {} BFD_RELOC_IA64_LTV32MSB
2290
@deffnx {} BFD_RELOC_IA64_LTV32LSB
2291
@deffnx {} BFD_RELOC_IA64_LTV64MSB
2292
@deffnx {} BFD_RELOC_IA64_LTV64LSB
2293
@deffnx {} BFD_RELOC_IA64_IPLTMSB
2294
@deffnx {} BFD_RELOC_IA64_IPLTLSB
2295
@deffnx {} BFD_RELOC_IA64_COPY
2296
@deffnx {} BFD_RELOC_IA64_LTOFF22X
2297
@deffnx {} BFD_RELOC_IA64_LDXMOV
2298
@deffnx {} BFD_RELOC_IA64_TPREL14
2299
@deffnx {} BFD_RELOC_IA64_TPREL22
2300
@deffnx {} BFD_RELOC_IA64_TPREL64I
2301
@deffnx {} BFD_RELOC_IA64_TPREL64MSB
2302
@deffnx {} BFD_RELOC_IA64_TPREL64LSB
2303
@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22
2304
@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB
2305
@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB
2306
@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22
2307
@deffnx {} BFD_RELOC_IA64_DTPREL14
2308
@deffnx {} BFD_RELOC_IA64_DTPREL22
2309
@deffnx {} BFD_RELOC_IA64_DTPREL64I
2310
@deffnx {} BFD_RELOC_IA64_DTPREL32MSB
2311
@deffnx {} BFD_RELOC_IA64_DTPREL32LSB
2312
@deffnx {} BFD_RELOC_IA64_DTPREL64MSB
2313
@deffnx {} BFD_RELOC_IA64_DTPREL64LSB
2314
@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22
2315
Intel IA64 Relocations.
2316
@end deffn
2317
@deffn {} BFD_RELOC_M68HC11_HI8
2318
Motorola 68HC11 reloc.
2319
This is the 8 bit high part of an absolute address.
2320
@end deffn
2321
@deffn {} BFD_RELOC_M68HC11_LO8
2322
Motorola 68HC11 reloc.
2323
This is the 8 bit low part of an absolute address.
2324
@end deffn
2325
@deffn {} BFD_RELOC_M68HC11_3B
2326
Motorola 68HC11 reloc.
2327
This is the 3 bit of a value.
2328
@end deffn
2329
@deffn {} BFD_RELOC_M68HC11_RL_JUMP
2330
Motorola 68HC11 reloc.
2331
This reloc marks the beginning of a jump/call instruction.
2332
It is used for linker relaxation to correctly identify beginning
2333
of instruction and change some branches to use PC-relative
2334
addressing mode.
2335
@end deffn
2336
@deffn {} BFD_RELOC_M68HC11_RL_GROUP
2337
Motorola 68HC11 reloc.
2338
This reloc marks a group of several instructions that gcc generates
2339
and for which the linker relaxation pass can modify and/or remove
2340
some of them.
2341
@end deffn
2342
@deffn {} BFD_RELOC_M68HC11_LO16
2343
Motorola 68HC11 reloc.
2344
This is the 16-bit lower part of an address.  It is used for 'call'
2345
instruction to specify the symbol address without any special
2346
transformation (due to memory bank window).
2347
@end deffn
2348
@deffn {} BFD_RELOC_M68HC11_PAGE
2349
Motorola 68HC11 reloc.
2350
This is a 8-bit reloc that specifies the page number of an address.
2351
It is used by 'call' instruction to specify the page number of
2352
the symbol.
2353
@end deffn
2354
@deffn {} BFD_RELOC_M68HC11_24
2355
Motorola 68HC11 reloc.
2356
This is a 24-bit reloc that represents the address with a 16-bit
2357
value and a 8-bit page number.  The symbol address is transformed
2358
to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
2359
@end deffn
2360
@deffn {} BFD_RELOC_M68HC12_5B
2361
Motorola 68HC12 reloc.
2362
This is the 5 bits of a value.
2363
@end deffn
2364
@deffn {} BFD_RELOC_16C_NUM08
2365
@deffnx {} BFD_RELOC_16C_NUM08_C
2366
@deffnx {} BFD_RELOC_16C_NUM16
2367
@deffnx {} BFD_RELOC_16C_NUM16_C
2368
@deffnx {} BFD_RELOC_16C_NUM32
2369
@deffnx {} BFD_RELOC_16C_NUM32_C
2370
@deffnx {} BFD_RELOC_16C_DISP04
2371
@deffnx {} BFD_RELOC_16C_DISP04_C
2372
@deffnx {} BFD_RELOC_16C_DISP08
2373
@deffnx {} BFD_RELOC_16C_DISP08_C
2374
@deffnx {} BFD_RELOC_16C_DISP16
2375
@deffnx {} BFD_RELOC_16C_DISP16_C
2376
@deffnx {} BFD_RELOC_16C_DISP24
2377
@deffnx {} BFD_RELOC_16C_DISP24_C
2378
@deffnx {} BFD_RELOC_16C_DISP24a
2379
@deffnx {} BFD_RELOC_16C_DISP24a_C
2380
@deffnx {} BFD_RELOC_16C_REG04
2381
@deffnx {} BFD_RELOC_16C_REG04_C
2382
@deffnx {} BFD_RELOC_16C_REG04a
2383
@deffnx {} BFD_RELOC_16C_REG04a_C
2384
@deffnx {} BFD_RELOC_16C_REG14
2385
@deffnx {} BFD_RELOC_16C_REG14_C
2386
@deffnx {} BFD_RELOC_16C_REG16
2387
@deffnx {} BFD_RELOC_16C_REG16_C
2388
@deffnx {} BFD_RELOC_16C_REG20
2389
@deffnx {} BFD_RELOC_16C_REG20_C
2390
@deffnx {} BFD_RELOC_16C_ABS20
2391
@deffnx {} BFD_RELOC_16C_ABS20_C
2392
@deffnx {} BFD_RELOC_16C_ABS24
2393
@deffnx {} BFD_RELOC_16C_ABS24_C
2394
@deffnx {} BFD_RELOC_16C_IMM04
2395
@deffnx {} BFD_RELOC_16C_IMM04_C
2396
@deffnx {} BFD_RELOC_16C_IMM16
2397
@deffnx {} BFD_RELOC_16C_IMM16_C
2398
@deffnx {} BFD_RELOC_16C_IMM20
2399
@deffnx {} BFD_RELOC_16C_IMM20_C
2400
@deffnx {} BFD_RELOC_16C_IMM24
2401
@deffnx {} BFD_RELOC_16C_IMM24_C
2402
@deffnx {} BFD_RELOC_16C_IMM32
2403
@deffnx {} BFD_RELOC_16C_IMM32_C
2404
NS CR16C Relocations.
2405
@end deffn
2406
@deffn {} BFD_RELOC_CR16_NUM8
2407
@deffnx {} BFD_RELOC_CR16_NUM16
2408
@deffnx {} BFD_RELOC_CR16_NUM32
2409
@deffnx {} BFD_RELOC_CR16_NUM32a
2410
@deffnx {} BFD_RELOC_CR16_REGREL0
2411
@deffnx {} BFD_RELOC_CR16_REGREL4
2412
@deffnx {} BFD_RELOC_CR16_REGREL4a
2413
@deffnx {} BFD_RELOC_CR16_REGREL14
2414
@deffnx {} BFD_RELOC_CR16_REGREL14a
2415
@deffnx {} BFD_RELOC_CR16_REGREL16
2416
@deffnx {} BFD_RELOC_CR16_REGREL20
2417
@deffnx {} BFD_RELOC_CR16_REGREL20a
2418
@deffnx {} BFD_RELOC_CR16_ABS20
2419
@deffnx {} BFD_RELOC_CR16_ABS24
2420
@deffnx {} BFD_RELOC_CR16_IMM4
2421
@deffnx {} BFD_RELOC_CR16_IMM8
2422
@deffnx {} BFD_RELOC_CR16_IMM16
2423
@deffnx {} BFD_RELOC_CR16_IMM20
2424
@deffnx {} BFD_RELOC_CR16_IMM24
2425
@deffnx {} BFD_RELOC_CR16_IMM32
2426
@deffnx {} BFD_RELOC_CR16_IMM32a
2427
@deffnx {} BFD_RELOC_CR16_DISP4
2428
@deffnx {} BFD_RELOC_CR16_DISP8
2429
@deffnx {} BFD_RELOC_CR16_DISP16
2430
@deffnx {} BFD_RELOC_CR16_DISP20
2431
@deffnx {} BFD_RELOC_CR16_DISP24
2432
@deffnx {} BFD_RELOC_CR16_DISP24a
2433
@deffnx {} BFD_RELOC_CR16_SWITCH8
2434
@deffnx {} BFD_RELOC_CR16_SWITCH16
2435
@deffnx {} BFD_RELOC_CR16_SWITCH32
2436
@deffnx {} BFD_RELOC_CR16_GOT_REGREL20
2437
@deffnx {} BFD_RELOC_CR16_GOTC_REGREL20
2438
@deffnx {} BFD_RELOC_CR16_GLOB_DAT
2439
NS CR16 Relocations.
2440
@end deffn
2441
@deffn {} BFD_RELOC_CRX_REL4
2442
@deffnx {} BFD_RELOC_CRX_REL8
2443
@deffnx {} BFD_RELOC_CRX_REL8_CMP
2444
@deffnx {} BFD_RELOC_CRX_REL16
2445
@deffnx {} BFD_RELOC_CRX_REL24
2446
@deffnx {} BFD_RELOC_CRX_REL32
2447
@deffnx {} BFD_RELOC_CRX_REGREL12
2448
@deffnx {} BFD_RELOC_CRX_REGREL22
2449
@deffnx {} BFD_RELOC_CRX_REGREL28
2450
@deffnx {} BFD_RELOC_CRX_REGREL32
2451
@deffnx {} BFD_RELOC_CRX_ABS16
2452
@deffnx {} BFD_RELOC_CRX_ABS32
2453
@deffnx {} BFD_RELOC_CRX_NUM8
2454
@deffnx {} BFD_RELOC_CRX_NUM16
2455
@deffnx {} BFD_RELOC_CRX_NUM32
2456
@deffnx {} BFD_RELOC_CRX_IMM16
2457
@deffnx {} BFD_RELOC_CRX_IMM32
2458
@deffnx {} BFD_RELOC_CRX_SWITCH8
2459
@deffnx {} BFD_RELOC_CRX_SWITCH16
2460
@deffnx {} BFD_RELOC_CRX_SWITCH32
2461
NS CRX Relocations.
2462
@end deffn
2463
@deffn {} BFD_RELOC_CRIS_BDISP8
2464
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_5
2465
@deffnx {} BFD_RELOC_CRIS_SIGNED_6
2466
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_6
2467
@deffnx {} BFD_RELOC_CRIS_SIGNED_8
2468
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_8
2469
@deffnx {} BFD_RELOC_CRIS_SIGNED_16
2470
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_16
2471
@deffnx {} BFD_RELOC_CRIS_LAPCQ_OFFSET
2472
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_4
2473
These relocs are only used within the CRIS assembler.  They are not
2474
(at present) written to any object files.
2475
@end deffn
2476
@deffn {} BFD_RELOC_CRIS_COPY
2477
@deffnx {} BFD_RELOC_CRIS_GLOB_DAT
2478
@deffnx {} BFD_RELOC_CRIS_JUMP_SLOT
2479
@deffnx {} BFD_RELOC_CRIS_RELATIVE
2480
Relocs used in ELF shared libraries for CRIS.
2481
@end deffn
2482
@deffn {} BFD_RELOC_CRIS_32_GOT
2483
32-bit offset to symbol-entry within GOT.
2484
@end deffn
2485
@deffn {} BFD_RELOC_CRIS_16_GOT
2486
16-bit offset to symbol-entry within GOT.
2487
@end deffn
2488
@deffn {} BFD_RELOC_CRIS_32_GOTPLT
2489
32-bit offset to symbol-entry within GOT, with PLT handling.
2490
@end deffn
2491
@deffn {} BFD_RELOC_CRIS_16_GOTPLT
2492
16-bit offset to symbol-entry within GOT, with PLT handling.
2493
@end deffn
2494
@deffn {} BFD_RELOC_CRIS_32_GOTREL
2495
32-bit offset to symbol, relative to GOT.
2496
@end deffn
2497
@deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL
2498
32-bit offset to symbol with PLT entry, relative to GOT.
2499
@end deffn
2500
@deffn {} BFD_RELOC_CRIS_32_PLT_PCREL
2501
32-bit offset to symbol with PLT entry, relative to this relocation.
2502
@end deffn
2503
@deffn {} BFD_RELOC_CRIS_32_GOT_GD
2504
@deffnx {} BFD_RELOC_CRIS_16_GOT_GD
2505
@deffnx {} BFD_RELOC_CRIS_32_GD
2506
@deffnx {} BFD_RELOC_CRIS_DTP
2507
@deffnx {} BFD_RELOC_CRIS_32_DTPREL
2508
@deffnx {} BFD_RELOC_CRIS_16_DTPREL
2509
@deffnx {} BFD_RELOC_CRIS_32_GOT_TPREL
2510
@deffnx {} BFD_RELOC_CRIS_16_GOT_TPREL
2511
@deffnx {} BFD_RELOC_CRIS_32_TPREL
2512
@deffnx {} BFD_RELOC_CRIS_16_TPREL
2513
@deffnx {} BFD_RELOC_CRIS_DTPMOD
2514
@deffnx {} BFD_RELOC_CRIS_32_IE
2515
Relocs used in TLS code for CRIS.
2516
@end deffn
2517
@deffn {} BFD_RELOC_860_COPY
2518
@deffnx {} BFD_RELOC_860_GLOB_DAT
2519
@deffnx {} BFD_RELOC_860_JUMP_SLOT
2520
@deffnx {} BFD_RELOC_860_RELATIVE
2521
@deffnx {} BFD_RELOC_860_PC26
2522
@deffnx {} BFD_RELOC_860_PLT26
2523
@deffnx {} BFD_RELOC_860_PC16
2524
@deffnx {} BFD_RELOC_860_LOW0
2525
@deffnx {} BFD_RELOC_860_SPLIT0
2526
@deffnx {} BFD_RELOC_860_LOW1
2527
@deffnx {} BFD_RELOC_860_SPLIT1
2528
@deffnx {} BFD_RELOC_860_LOW2
2529
@deffnx {} BFD_RELOC_860_SPLIT2
2530
@deffnx {} BFD_RELOC_860_LOW3
2531
@deffnx {} BFD_RELOC_860_LOGOT0
2532
@deffnx {} BFD_RELOC_860_SPGOT0
2533
@deffnx {} BFD_RELOC_860_LOGOT1
2534
@deffnx {} BFD_RELOC_860_SPGOT1
2535
@deffnx {} BFD_RELOC_860_LOGOTOFF0
2536
@deffnx {} BFD_RELOC_860_SPGOTOFF0
2537
@deffnx {} BFD_RELOC_860_LOGOTOFF1
2538
@deffnx {} BFD_RELOC_860_SPGOTOFF1
2539
@deffnx {} BFD_RELOC_860_LOGOTOFF2
2540
@deffnx {} BFD_RELOC_860_LOGOTOFF3
2541
@deffnx {} BFD_RELOC_860_LOPC
2542
@deffnx {} BFD_RELOC_860_HIGHADJ
2543
@deffnx {} BFD_RELOC_860_HAGOT
2544
@deffnx {} BFD_RELOC_860_HAGOTOFF
2545
@deffnx {} BFD_RELOC_860_HAPC
2546
@deffnx {} BFD_RELOC_860_HIGH
2547
@deffnx {} BFD_RELOC_860_HIGOT
2548
@deffnx {} BFD_RELOC_860_HIGOTOFF
2549
Intel i860 Relocations.
2550
@end deffn
2551
@deffn {} BFD_RELOC_OPENRISC_ABS_26
2552
@deffnx {} BFD_RELOC_OPENRISC_REL_26
2553
OpenRISC Relocations.
2554
@end deffn
2555
@deffn {} BFD_RELOC_H8_DIR16A8
2556
@deffnx {} BFD_RELOC_H8_DIR16R8
2557
@deffnx {} BFD_RELOC_H8_DIR24A8
2558
@deffnx {} BFD_RELOC_H8_DIR24R8
2559
@deffnx {} BFD_RELOC_H8_DIR32A16
2560
H8 elf Relocations.
2561
@end deffn
2562
@deffn {} BFD_RELOC_XSTORMY16_REL_12
2563
@deffnx {} BFD_RELOC_XSTORMY16_12
2564
@deffnx {} BFD_RELOC_XSTORMY16_24
2565
@deffnx {} BFD_RELOC_XSTORMY16_FPTR16
2566
Sony Xstormy16 Relocations.
2567
@end deffn
2568
@deffn {} BFD_RELOC_RELC
2569
Self-describing complex relocations.
2570
@end deffn
2571
@deffn {} BFD_RELOC_XC16X_PAG
2572
@deffnx {} BFD_RELOC_XC16X_POF
2573
@deffnx {} BFD_RELOC_XC16X_SEG
2574
@deffnx {} BFD_RELOC_XC16X_SOF
2575
Infineon Relocations.
2576
@end deffn
2577
@deffn {} BFD_RELOC_VAX_GLOB_DAT
2578
@deffnx {} BFD_RELOC_VAX_JMP_SLOT
2579
@deffnx {} BFD_RELOC_VAX_RELATIVE
2580
Relocations used by VAX ELF.
2581
@end deffn
2582
@deffn {} BFD_RELOC_MT_PC16
2583
Morpho MT - 16 bit immediate relocation.
2584
@end deffn
2585
@deffn {} BFD_RELOC_MT_HI16
2586
Morpho MT - Hi 16 bits of an address.
2587
@end deffn
2588
@deffn {} BFD_RELOC_MT_LO16
2589
Morpho MT - Low 16 bits of an address.
2590
@end deffn
2591
@deffn {} BFD_RELOC_MT_GNU_VTINHERIT
2592
Morpho MT - Used to tell the linker which vtable entries are used.
2593
@end deffn
2594
@deffn {} BFD_RELOC_MT_GNU_VTENTRY
2595
Morpho MT - Used to tell the linker which vtable entries are used.
2596
@end deffn
2597
@deffn {} BFD_RELOC_MT_PCINSN8
2598
Morpho MT - 8 bit immediate relocation.
2599
@end deffn
2600
@deffn {} BFD_RELOC_MSP430_10_PCREL
2601
@deffnx {} BFD_RELOC_MSP430_16_PCREL
2602
@deffnx {} BFD_RELOC_MSP430_16
2603
@deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE
2604
@deffnx {} BFD_RELOC_MSP430_16_BYTE
2605
@deffnx {} BFD_RELOC_MSP430_2X_PCREL
2606
@deffnx {} BFD_RELOC_MSP430_RL_PCREL
2607
msp430 specific relocation codes
2608
@end deffn
2609
@deffn {} BFD_RELOC_IQ2000_OFFSET_16
2610
@deffnx {} BFD_RELOC_IQ2000_OFFSET_21
2611
@deffnx {} BFD_RELOC_IQ2000_UHI16
2612
IQ2000 Relocations.
2613
@end deffn
2614
@deffn {} BFD_RELOC_XTENSA_RTLD
2615
Special Xtensa relocation used only by PLT entries in ELF shared
2616
objects to indicate that the runtime linker should set the value
2617
to one of its own internal functions or data structures.
2618
@end deffn
2619
@deffn {} BFD_RELOC_XTENSA_GLOB_DAT
2620
@deffnx {} BFD_RELOC_XTENSA_JMP_SLOT
2621
@deffnx {} BFD_RELOC_XTENSA_RELATIVE
2622
Xtensa relocations for ELF shared objects.
2623
@end deffn
2624
@deffn {} BFD_RELOC_XTENSA_PLT
2625
Xtensa relocation used in ELF object files for symbols that may require
2626
PLT entries.  Otherwise, this is just a generic 32-bit relocation.
2627
@end deffn
2628
@deffn {} BFD_RELOC_XTENSA_DIFF8
2629
@deffnx {} BFD_RELOC_XTENSA_DIFF16
2630
@deffnx {} BFD_RELOC_XTENSA_DIFF32
2631
Xtensa relocations to mark the difference of two local symbols.
2632
These are only needed to support linker relaxation and can be ignored
2633
when not relaxing.  The field is set to the value of the difference
2634
assuming no relaxation.  The relocation encodes the position of the
2635
first symbol so the linker can determine whether to adjust the field
2636
value.
2637
@end deffn
2638
@deffn {} BFD_RELOC_XTENSA_SLOT0_OP
2639
@deffnx {} BFD_RELOC_XTENSA_SLOT1_OP
2640
@deffnx {} BFD_RELOC_XTENSA_SLOT2_OP
2641
@deffnx {} BFD_RELOC_XTENSA_SLOT3_OP
2642
@deffnx {} BFD_RELOC_XTENSA_SLOT4_OP
2643
@deffnx {} BFD_RELOC_XTENSA_SLOT5_OP
2644
@deffnx {} BFD_RELOC_XTENSA_SLOT6_OP
2645
@deffnx {} BFD_RELOC_XTENSA_SLOT7_OP
2646
@deffnx {} BFD_RELOC_XTENSA_SLOT8_OP
2647
@deffnx {} BFD_RELOC_XTENSA_SLOT9_OP
2648
@deffnx {} BFD_RELOC_XTENSA_SLOT10_OP
2649
@deffnx {} BFD_RELOC_XTENSA_SLOT11_OP
2650
@deffnx {} BFD_RELOC_XTENSA_SLOT12_OP
2651
@deffnx {} BFD_RELOC_XTENSA_SLOT13_OP
2652
@deffnx {} BFD_RELOC_XTENSA_SLOT14_OP
2653
Generic Xtensa relocations for instruction operands.  Only the slot
2654
number is encoded in the relocation.  The relocation applies to the
2655
last PC-relative immediate operand, or if there are no PC-relative
2656
immediates, to the last immediate operand.
2657
@end deffn
2658
@deffn {} BFD_RELOC_XTENSA_SLOT0_ALT
2659
@deffnx {} BFD_RELOC_XTENSA_SLOT1_ALT
2660
@deffnx {} BFD_RELOC_XTENSA_SLOT2_ALT
2661
@deffnx {} BFD_RELOC_XTENSA_SLOT3_ALT
2662
@deffnx {} BFD_RELOC_XTENSA_SLOT4_ALT
2663
@deffnx {} BFD_RELOC_XTENSA_SLOT5_ALT
2664
@deffnx {} BFD_RELOC_XTENSA_SLOT6_ALT
2665
@deffnx {} BFD_RELOC_XTENSA_SLOT7_ALT
2666
@deffnx {} BFD_RELOC_XTENSA_SLOT8_ALT
2667
@deffnx {} BFD_RELOC_XTENSA_SLOT9_ALT
2668
@deffnx {} BFD_RELOC_XTENSA_SLOT10_ALT
2669
@deffnx {} BFD_RELOC_XTENSA_SLOT11_ALT
2670
@deffnx {} BFD_RELOC_XTENSA_SLOT12_ALT
2671
@deffnx {} BFD_RELOC_XTENSA_SLOT13_ALT
2672
@deffnx {} BFD_RELOC_XTENSA_SLOT14_ALT
2673
Alternate Xtensa relocations.  Only the slot is encoded in the
2674
relocation.  The meaning of these relocations is opcode-specific.
2675
@end deffn
2676
@deffn {} BFD_RELOC_XTENSA_OP0
2677
@deffnx {} BFD_RELOC_XTENSA_OP1
2678
@deffnx {} BFD_RELOC_XTENSA_OP2
2679
Xtensa relocations for backward compatibility.  These have all been
2680
replaced by BFD_RELOC_XTENSA_SLOT0_OP.
2681
@end deffn
2682
@deffn {} BFD_RELOC_XTENSA_ASM_EXPAND
2683
Xtensa relocation to mark that the assembler expanded the
2684
instructions from an original target.  The expansion size is
2685
encoded in the reloc size.
2686
@end deffn
2687
@deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY
2688
Xtensa relocation to mark that the linker should simplify
2689
assembler-expanded instructions.  This is commonly used
2690
internally by the linker after analysis of a
2691
BFD_RELOC_XTENSA_ASM_EXPAND.
2692
@end deffn
2693
@deffn {} BFD_RELOC_XTENSA_TLSDESC_FN
2694
@deffnx {} BFD_RELOC_XTENSA_TLSDESC_ARG
2695
@deffnx {} BFD_RELOC_XTENSA_TLS_DTPOFF
2696
@deffnx {} BFD_RELOC_XTENSA_TLS_TPOFF
2697
@deffnx {} BFD_RELOC_XTENSA_TLS_FUNC
2698
@deffnx {} BFD_RELOC_XTENSA_TLS_ARG
2699
@deffnx {} BFD_RELOC_XTENSA_TLS_CALL
2700
Xtensa TLS relocations.
2701
@end deffn
2702
@deffn {} BFD_RELOC_Z80_DISP8
2703
8 bit signed offset in (ix+d) or (iy+d).
2704
@end deffn
2705
@deffn {} BFD_RELOC_Z8K_DISP7
2706
DJNZ offset.
2707
@end deffn
2708
@deffn {} BFD_RELOC_Z8K_CALLR
2709
CALR offset.
2710
@end deffn
2711
@deffn {} BFD_RELOC_Z8K_IMM4L
2712
4 bit value.
2713
@end deffn
2714
@deffn {} BFD_RELOC_LM32_CALL
2715
@deffnx {} BFD_RELOC_LM32_BRANCH
2716
@deffnx {} BFD_RELOC_LM32_16_GOT
2717
@deffnx {} BFD_RELOC_LM32_GOTOFF_HI16
2718
@deffnx {} BFD_RELOC_LM32_GOTOFF_LO16
2719
@deffnx {} BFD_RELOC_LM32_COPY
2720
@deffnx {} BFD_RELOC_LM32_GLOB_DAT
2721
@deffnx {} BFD_RELOC_LM32_JMP_SLOT
2722
@deffnx {} BFD_RELOC_LM32_RELATIVE
2723
Lattice Mico32 relocations.
2724
@end deffn
2725
@deffn {} BFD_RELOC_MACH_O_SECTDIFF
2726
Difference between two section addreses.  Must be followed by a
2727
BFD_RELOC_MACH_O_PAIR.
2728
@end deffn
2729
@deffn {} BFD_RELOC_MACH_O_PAIR
2730
Pair of relocation.  Contains the first symbol.
2731
@end deffn
2732
@deffn {} BFD_RELOC_MACH_O_X86_64_BRANCH32
2733
@deffnx {} BFD_RELOC_MACH_O_X86_64_BRANCH8
2734
PCREL relocations.  They are marked as branch to create PLT entry if
2735
required.
2736
@end deffn
2737
@deffn {} BFD_RELOC_MACH_O_X86_64_GOT
2738
Used when referencing a GOT entry.
2739
@end deffn
2740
@deffn {} BFD_RELOC_MACH_O_X86_64_GOT_LOAD
2741
Used when loading a GOT entry with movq.  It is specially marked so that
2742
the linker could optimize the movq to a leaq if possible.
2743
@end deffn
2744
@deffn {} BFD_RELOC_MACH_O_X86_64_SUBTRACTOR32
2745
Symbol will be substracted.  Must be followed by a BFD_RELOC_64.
2746
@end deffn
2747
@deffn {} BFD_RELOC_MACH_O_X86_64_SUBTRACTOR64
2748
Symbol will be substracted.  Must be followed by a BFD_RELOC_64.
2749
@end deffn
2750
@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_1
2751
Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
2752
@end deffn
2753
@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_2
2754
Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
2755
@end deffn
2756
@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_4
2757
Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
2758
@end deffn
2759
@deffn {} BFD_RELOC_MICROBLAZE_32_LO
2760
This is a 32 bit reloc for the microblaze that stores the
2761
low 16 bits of a value
2762
@end deffn
2763
@deffn {} BFD_RELOC_MICROBLAZE_32_LO_PCREL
2764
This is a 32 bit pc-relative reloc for the microblaze that
2765
stores the low 16 bits of a value
2766
@end deffn
2767
@deffn {} BFD_RELOC_MICROBLAZE_32_ROSDA
2768
This is a 32 bit reloc for the microblaze that stores a
2769
value relative to the read-only small data area anchor
2770
@end deffn
2771
@deffn {} BFD_RELOC_MICROBLAZE_32_RWSDA
2772
This is a 32 bit reloc for the microblaze that stores a
2773
value relative to the read-write small data area anchor
2774
@end deffn
2775
@deffn {} BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
2776
This is a 32 bit reloc for the microblaze to handle
2777
expressions of the form "Symbol Op Symbol"
2778
@end deffn
2779
@deffn {} BFD_RELOC_MICROBLAZE_64_NONE
2780
This is a 64 bit reloc that stores the 32 bit pc relative
2781
value in two words (with an imm instruction).  No relocation is
2782
done here - only used for relaxing
2783
@end deffn
2784
@deffn {} BFD_RELOC_MICROBLAZE_64_GOTPC
2785
This is a 64 bit reloc that stores the 32 bit pc relative
2786
value in two words (with an imm instruction).  The relocation is
2787
PC-relative GOT offset
2788
@end deffn
2789
@deffn {} BFD_RELOC_MICROBLAZE_64_GOT
2790
This is a 64 bit reloc that stores the 32 bit pc relative
2791
value in two words (with an imm instruction).  The relocation is
2792
GOT offset
2793
@end deffn
2794
@deffn {} BFD_RELOC_MICROBLAZE_64_PLT
2795
This is a 64 bit reloc that stores the 32 bit pc relative
2796
value in two words (with an imm instruction).  The relocation is
2797
PC-relative offset into PLT
2798
@end deffn
2799
@deffn {} BFD_RELOC_MICROBLAZE_64_GOTOFF
2800
This is a 64 bit reloc that stores the 32 bit GOT relative
2801
value in two words (with an imm instruction).  The relocation is
2802
relative offset from _GLOBAL_OFFSET_TABLE_
2803
@end deffn
2804
@deffn {} BFD_RELOC_MICROBLAZE_32_GOTOFF
2805
This is a 32 bit reloc that stores the 32 bit GOT relative
2806
value in a word.  The relocation is relative offset from
2807
@end deffn
2808
@deffn {} BFD_RELOC_MICROBLAZE_COPY
2809
This is used to tell the dynamic linker to copy the value out of
2810
the dynamic object into the runtime process image.
2811
@end deffn
2812
 
2813
@example
2814
 
2815
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
2816
@end example
2817
@findex bfd_reloc_type_lookup
2818
@subsubsection @code{bfd_reloc_type_lookup}
2819
@strong{Synopsis}
2820
@example
2821
reloc_howto_type *bfd_reloc_type_lookup
2822
   (bfd *abfd, bfd_reloc_code_real_type code);
2823
reloc_howto_type *bfd_reloc_name_lookup
2824
   (bfd *abfd, const char *reloc_name);
2825
@end example
2826
@strong{Description}@*
2827
Return a pointer to a howto structure which, when
2828
invoked, will perform the relocation @var{code} on data from the
2829
architecture noted.
2830
 
2831
@findex bfd_default_reloc_type_lookup
2832
@subsubsection @code{bfd_default_reloc_type_lookup}
2833
@strong{Synopsis}
2834
@example
2835
reloc_howto_type *bfd_default_reloc_type_lookup
2836
   (bfd *abfd, bfd_reloc_code_real_type  code);
2837
@end example
2838
@strong{Description}@*
2839
Provides a default relocation lookup routine for any architecture.
2840
 
2841
@findex bfd_get_reloc_code_name
2842
@subsubsection @code{bfd_get_reloc_code_name}
2843
@strong{Synopsis}
2844
@example
2845
const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
2846
@end example
2847
@strong{Description}@*
2848
Provides a printable name for the supplied relocation code.
2849
Useful mainly for printing error messages.
2850
 
2851
@findex bfd_generic_relax_section
2852
@subsubsection @code{bfd_generic_relax_section}
2853
@strong{Synopsis}
2854
@example
2855
bfd_boolean bfd_generic_relax_section
2856
   (bfd *abfd,
2857
    asection *section,
2858
    struct bfd_link_info *,
2859
    bfd_boolean *);
2860
@end example
2861
@strong{Description}@*
2862
Provides default handling for relaxing for back ends which
2863
don't do relaxing.
2864
 
2865
@findex bfd_generic_gc_sections
2866
@subsubsection @code{bfd_generic_gc_sections}
2867
@strong{Synopsis}
2868
@example
2869
bfd_boolean bfd_generic_gc_sections
2870
   (bfd *, struct bfd_link_info *);
2871
@end example
2872
@strong{Description}@*
2873
Provides default handling for relaxing for back ends which
2874
don't do section gc -- i.e., does nothing.
2875
 
2876
@findex bfd_generic_merge_sections
2877
@subsubsection @code{bfd_generic_merge_sections}
2878
@strong{Synopsis}
2879
@example
2880
bfd_boolean bfd_generic_merge_sections
2881
   (bfd *, struct bfd_link_info *);
2882
@end example
2883
@strong{Description}@*
2884
Provides default handling for SEC_MERGE section merging for back ends
2885
which don't have SEC_MERGE support -- i.e., does nothing.
2886
 
2887
@findex bfd_generic_get_relocated_section_contents
2888
@subsubsection @code{bfd_generic_get_relocated_section_contents}
2889
@strong{Synopsis}
2890
@example
2891
bfd_byte *bfd_generic_get_relocated_section_contents
2892
   (bfd *abfd,
2893
    struct bfd_link_info *link_info,
2894
    struct bfd_link_order *link_order,
2895
    bfd_byte *data,
2896
    bfd_boolean relocatable,
2897
    asymbol **symbols);
2898
@end example
2899
@strong{Description}@*
2900
Provides default handling of relocation effort for back ends
2901
which can't be bothered to do it efficiently.
2902
 

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