OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [gdb/] [gdbserver/] [linux-or32-low.c] - Blame information for rev 565

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 441 jeremybenn
/* GNU/Linux/or32 specific low level interface, for the remote server for GDB.
2
   Copyright (C) 2005, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
3
   Copyright (C) 2010 Embecosm Limited
4
 
5
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
6
 
7
   This file is part of GDB.
8
 
9
   This program is free software; you can redistribute it and/or modify
10
   it under the terms of the GNU General Public License as published by
11
   the Free Software Foundation; either version 3 of the License, or
12
   (at your option) any later version.
13
 
14
   This program is distributed in the hope that it will be useful,
15
   but WITHOUT ANY WARRANTY; without even the implied warranty of
16
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17
   GNU General Public License for more details.
18
 
19
   You should have received a copy of the GNU General Public License
20
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
21
 
22
/* -------------------------------------------------------------------------- */
23
/* OpenRISC 1000 specific low level Linux interface for GDB server.
24
 
25
   This implementation includes full Doxygen compatible documentation         */
26
/* -------------------------------------------------------------------------- */
27
 
28
#ifdef HAVE_STRINGS_H
29
#include <strings.h>
30
#endif
31
 
32
#include "server.h"
33
#include "regdef.h"
34
#include "linux-low.h"
35
 
36 445 julius
#include <asm/ptrace.h> /* For openrisc kernel ptrace register offsets */
37
 
38 512 jeremybenn
/* Defined in auto-generated file reg-or32.c.  */
39
void init_registers_or32 (void);
40
 
41 441 jeremybenn
#ifdef HAVE_SYS_REG_H
42
#include <sys/reg.h>
43
#endif
44
 
45 447 jeremybenn
 
46 453 jeremybenn
/*! Some useful GDB register numbers. */
47
#define GDB_REGNUM_R0    0
48
#define GDB_REGNUM_R31  31
49
#define GDB_REGNUM_PPC  32
50
#define GDB_REGNUM_NPC  33
51
#define GDB_REGNUM_SR   34
52
 
53 565 jeremybenn
/*! This is the number of *GDB* registers. I.e. r0-r31, PPC, NPC and SR. */
54 453 jeremybenn
#define or32_num_regs  (GDB_REGNUM_SR + 1)
55 441 jeremybenn
 
56
 
57
/* -------------------------------------------------------------------------- */
58
/*!Provide the ptrace "address" of a register.
59 447 jeremybenn
 
60
   This must be in GDB order (r0-r1, ppc, npc, sr) to ptrace offset. As with
61
   regs_or32, we substitute r31 for r0 and NPC for PPC.                       */
62 441 jeremybenn
/* -------------------------------------------------------------------------- */
63
static int or32_regmap[] = {
64 565 jeremybenn
  PT_GPR31, PT_SP,    PT_GPR2,  PT_GPR3,
65
  PT_GPR4,  PT_GPR5,  PT_GPR6,  PT_GPR7,
66
  PT_GPR8,  PT_GPR9,  PT_GPR10, PT_GPR11,
67
  PT_GPR12, PT_GPR13, PT_GPR14, PT_GPR15,
68
  PT_GPR16, PT_GPR17, PT_GPR18, PT_GPR19,
69
  PT_GPR20, PT_GPR21, PT_GPR22, PT_GPR23,
70
  PT_GPR24, PT_GPR25, PT_GPR26, PT_GPR27,
71
  PT_GPR28, PT_GPR29, PT_GPR30, PT_GPR31,
72
  PT_PC,    PT_PC,    PT_SR
73 441 jeremybenn
};
74
 
75
 
76
/* -------------------------------------------------------------------------- */
77
/*!Predicate to indicate if a register can be read.
78
 
79 453 jeremybenn
   We mark r0 as not readable.
80 441 jeremybenn
 
81
   @param[in] regno  Register to read.
82
 
83
   @return  Non-zero (TRUE) if the register can be read, zero (FALSE)
84
            otherwise.                                                        */
85
/* -------------------------------------------------------------------------- */
86
static int
87
or32_cannot_fetch_register (int  regno)
88
{
89 453 jeremybenn
  return (GDB_REGNUM_R0 == regno) || (regno >= or32_num_regs);
90 441 jeremybenn
 
91
}       /* or32_cannot_fetch_register () */
92
 
93
 
94
/* -------------------------------------------------------------------------- */
95
/*!Predicate to indicate if a register can be written.
96
 
97 453 jeremybenn
   We mark r0 and the SR as not writeable.
98 441 jeremybenn
 
99
   @param[in] regno  Register to write.
100
 
101
   @return  Non-zero (TRUE) if the register can be written, zero (FALSE)
102
            otherwise.                                                        */
103
/* -------------------------------------------------------------------------- */
104
static int
105
or32_cannot_store_register (int  regno)
106
{
107 453 jeremybenn
  return (GDB_REGNUM_R0 == regno) || (GDB_REGNUM_SR == regno) ||
108
         (regno >= or32_num_regs);
109 441 jeremybenn
 
110
}       /* or32_cannot_store_register () */
111
 
112
 
113
/* -------------------------------------------------------------------------- */
114
/*!Get the current program counter.
115
 
116
   On the OR32, this is NPC, the *next* program counter.
117
 
118
   @param[in] regcache  Current register cache.
119
 
120
   @return  The value of the NPC.                                             */
121
/* -------------------------------------------------------------------------- */
122
static CORE_ADDR
123
or32_get_pc (struct regcache *regcache)
124
{
125
  unsigned long int  npc;
126 565 jeremybenn
  collect_register_by_name (regcache, "pc", &npc);
127 441 jeremybenn
 
128 445 julius
    if (debug_threads)
129 441 jeremybenn
    {
130
      fprintf (stderr, "stop pc is %08lx\n", npc);
131
    }
132 445 julius
 
133 441 jeremybenn
  return  npc;
134
 
135
}       /* or32_get_pc () */
136
 
137
 
138
/* -------------------------------------------------------------------------- */
139
/*!Set the current program counter.
140
 
141
   On the OR32, this is NPC, the *next* program counter.
142
 
143
   @param[in] regcache  Current register cache.
144
   @param[in] pc        The value of the program counter to set.              */
145
/* -------------------------------------------------------------------------- */
146
static void
147
or32_set_pc (struct regcache *regcache,
148
             CORE_ADDR        pc)
149
{
150
  unsigned long int  npc = pc;
151 565 jeremybenn
  supply_register_by_name (regcache, "pc", &npc);
152 441 jeremybenn
 
153
}       /* or32_set_pc () */
154
 
155
 
156
/*! The value of a breakpoint instruction (l.trap  1). */
157
static const unsigned char or32_breakpoint [] = {0x21, 0x00, 0x00, 0x01};
158
 
159
 
160
/*! The length of a breakpoint instruction. */
161
#define OR32_BREAKPOINT_LEN  4
162
 
163
 
164
/* -------------------------------------------------------------------------- */
165
/*!Predicate to indicate if there is a breakpoint at the current address.
166
 
167
   For the OR32 we, just look for the l.trap 1 instruction.
168
 
169
   @param[in] where  The address to look for a breakpoint at.
170
 
171
   @return  Non-zero (TRUE) if there is a breakpoint, zero (FALSE) otherwise. */
172
/* -------------------------------------------------------------------------- */
173
static int
174
or32_breakpoint_at (CORE_ADDR where)
175
{
176
  unsigned char  insn[OR32_BREAKPOINT_LEN];
177
 
178
  (*the_target->read_memory) (where, insn, OR32_BREAKPOINT_LEN);
179
 
180
  return  (0 ==  bcmp (insn, or32_breakpoint, OR32_BREAKPOINT_LEN));
181
 
182
}       /* or32_breakpoint_at () */
183
 
184
 
185
/* -------------------------------------------------------------------------- */
186
/*!Data structure giving all the target specific functions.
187
 
188
   Details are in struct linux_target_ops in linux-low.h.                     */
189
/* -------------------------------------------------------------------------- */
190
struct linux_target_ops the_low_target = {
191
  init_registers_or32,                  /* Arch initialization */
192
  or32_num_regs,                        /* Num regs in arch */
193
  or32_regmap,                          /* Reg offsets for ptrace */
194
  or32_cannot_fetch_register,           /* Predicate for reg reading */
195
  or32_cannot_store_register,           /* Predicate for reg writing */
196
  or32_get_pc,                          /* Read the PC */
197
  or32_set_pc,                          /* Write the PC */
198
  or32_breakpoint,                      /* Breakpoint instruction bytes */
199
  OR32_BREAKPOINT_LEN,                  /* Breakpoint length */
200
  NULL,                                 /* Breakpoint reinsertion (unused) */
201
  0,                                     /* Decrement PC after break (FALSE) */
202
  or32_breakpoint_at,                   /* Predicate to check for breakpoint */
203 512 jeremybenn
  NULL,                                 /* Insert watchpoint (unused) */
204
  NULL,                                 /* Remove watchpoint (unused) */
205 441 jeremybenn
  NULL,                                 /* Predicate if stopped by watchpoint */
206
  NULL,                                 /* Data address for watchpoint stop */
207
  NULL,                                 /* ptrace PEEKUSR hook */
208
  NULL,                                 /* ptrace POKEUSR hook */
209
  NULL,                                 /* ptrace conversion predicate */
210
  NULL,                                 /* New process hook */
211
  NULL,                                 /* New thread hook */
212
  NULL,                                 /* Prepare to resume thread */
213
  NULL,                                 /* Target specific qSupported */
214
  NULL,                                 /* Tracepoint supported predicate */
215
  NULL,                                 /* Get thread area address */
216
  NULL,                                 /* Fast tracepoint jump pad */
217
  NULL,                                 /* Get bytecode operations vector */
218
};

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.