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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [gdb/] [sh-tdep.c] - Blame information for rev 517

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1 330 jeremybenn 
/* Target-dependent code for Renesas Super-H, for GDB.
2 
 
3 
   Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
4 
   2003, 2004, 2005, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
5 
 
6 
   This file is part of GDB.
7 
 
8 
   This program is free software; you can redistribute it and/or modify
9 
   it under the terms of the GNU General Public License as published by
10 
   the Free Software Foundation; either version 3 of the License, or
11 
   (at your option) any later version.
12 
 
13 
   This program is distributed in the hope that it will be useful,
14 
   but WITHOUT ANY WARRANTY; without even the implied warranty of
15 
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 
   GNU General Public License for more details.
17 
 
18 
   You should have received a copy of the GNU General Public License
19 
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
20 
 
21 
/*
22 
   Contributed by Steve Chamberlain
23 
   sac@cygnus.com
24 
 */
25 
 
26 
#include "defs.h"
27 
#include "frame.h"
28 
#include "frame-base.h"
29 
#include "frame-unwind.h"
30 
#include "dwarf2-frame.h"
31 
#include "symtab.h"
32 
#include "gdbtypes.h"
33 
#include "gdbcmd.h"
34 
#include "gdbcore.h"
35 
#include "value.h"
36 
#include "dis-asm.h"
37 
#include "inferior.h"
38 
#include "gdb_string.h"
39 
#include "gdb_assert.h"
40 
#include "arch-utils.h"
41 
#include "floatformat.h"
42 
#include "regcache.h"
43 
#include "doublest.h"
44 
#include "osabi.h"
45 
#include "reggroups.h"
46 
#include "regset.h"
47 
 
48 
#include "sh-tdep.h"
49 
 
50 
#include "elf-bfd.h"
51 
#include "solib-svr4.h"
52 
 
53 
/* sh flags */
54 
#include "elf/sh.h"
55 
#include "dwarf2.h"
56 
/* registers numbers shared with the simulator */
57 
#include "gdb/sim-sh.h"
58 
 
59 
/* List of "set sh ..." and "show sh ..." commands.  */
60 
static struct cmd_list_element *setshcmdlist = NULL;
61 
static struct cmd_list_element *showshcmdlist = NULL;
62 
 
63 
static const char sh_cc_gcc[] = "gcc";
64 
static const char sh_cc_renesas[] = "renesas";
65 
static const char *sh_cc_enum[] = {
66 
  sh_cc_gcc,
67 
  sh_cc_renesas,
68 
  NULL
69 
};
70 
 
71 
static const char *sh_active_calling_convention = sh_cc_gcc;
72 
 
73 
static void (*sh_show_regs) (struct frame_info *);
74 
 
75 
#define SH_NUM_REGS 67
76 
 
77 
struct sh_frame_cache
78 
{
79 
  /* Base address.  */
80 
  CORE_ADDR base;
81 
  LONGEST sp_offset;
82 
  CORE_ADDR pc;
83 
 
84 
  /* Flag showing that a frame has been created in the prologue code. */
85 
  int uses_fp;
86 
 
87 
  /* Saved registers.  */
88 
  CORE_ADDR saved_regs[SH_NUM_REGS];
89 
  CORE_ADDR saved_sp;
90 
};
91 
 
92 
static int
93 
sh_is_renesas_calling_convention (struct type *func_type)
94 
{
95 
  return ((func_type
96 
           && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh)
97 
          || sh_active_calling_convention == sh_cc_renesas);
98 
}
99 
 
100 
static const char *
101 
sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr)
102 
{
103 
  static char *register_names[] = {
104 
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
105 
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
106 
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
107 
    "", "",
108 
    "", "", "", "", "", "", "", "",
109 
    "", "", "", "", "", "", "", "",
110 
    "", "",
111 
    "", "", "", "", "", "", "", "",
112 
    "", "", "", "", "", "", "", "",
113 
    "", "", "", "", "", "", "", "",
114 
  };
115 
  if (reg_nr < 0)
116 
    return NULL;
117 
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
118 
    return NULL;
119 
  return register_names[reg_nr];
120 
}
121 
 
122 
static const char *
123 
sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr)
124 
{
125 
  static char *register_names[] = {
126 
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
127 
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
128 
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
129 
    "", "",
130 
    "", "", "", "", "", "", "", "",
131 
    "", "", "", "", "", "", "", "",
132 
    "ssr", "spc",
133 
    "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
134 
    "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
135 
    "", "", "", "", "", "", "", "",
136 
  };
137 
  if (reg_nr < 0)
138 
    return NULL;
139 
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
140 
    return NULL;
141 
  return register_names[reg_nr];
142 
}
143 
 
144 
static const char *
145 
sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr)
146 
{
147 
  static char *register_names[] = {
148 
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
149 
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
150 
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
151 
    "fpul", "fpscr",
152 
    "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
153 
    "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
154 
    "ssr", "spc",
155 
    "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
156 
    "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
157 
    "", "", "", "", "", "", "", "",
158 
  };
159 
  if (reg_nr < 0)
160 
    return NULL;
161 
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
162 
    return NULL;
163 
  return register_names[reg_nr];
164 
}
165 
 
166 
static const char *
167 
sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr)
168 
{
169 
  static char *register_names[] = {
170 
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
171 
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
172 
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
173 
    "fpul", "fpscr",
174 
    "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
175 
    "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
176 
    "", "",
177 
    "", "", "", "", "", "", "", "",
178 
    "", "", "", "", "", "", "", "",
179 
    "", "", "", "", "", "", "", "",
180 
  };
181 
  if (reg_nr < 0)
182 
    return NULL;
183 
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
184 
    return NULL;
185 
  return register_names[reg_nr];
186 
}
187 
 
188 
static const char *
189 
sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr)
190 
{
191 
  static char *register_names[] = {
192 
    /* general registers 0-15 */
193 
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
194 
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
195 
    /* 16 - 22 */
196 
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
197 
    /* 23, 24 */
198 
    "fpul", "fpscr",
199 
    /* floating point registers 25 - 40 */
200 
    "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
201 
    "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
202 
    /* 41, 42 */
203 
    "", "",
204 
    /* 43 - 62.  Banked registers.  The bank number used is determined by
205 
       the bank register (63). */
206 
    "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
207 
    "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
208 
    "machb", "ivnb", "prb", "gbrb", "maclb",
209 
    /* 63: register bank number, not a real register but used to
210 
       communicate the register bank currently get/set.  This register
211 
       is hidden to the user, who manipulates it using the pseudo
212 
       register called "bank" (67).  See below.  */
213 
    "",
214 
    /* 64 - 66 */
215 
    "ibcr", "ibnr", "tbr",
216 
    /* 67: register bank number, the user visible pseudo register.  */
217 
    "bank",
218 
    /* double precision (pseudo) 68 - 75 */
219 
    "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
220 
  };
221 
  if (reg_nr < 0)
222 
    return NULL;
223 
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
224 
    return NULL;
225 
  return register_names[reg_nr];
226 
}
227 
 
228 
static const char *
229 
sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
230 
{
231 
  static char *register_names[] = {
232 
    /* general registers 0-15 */
233 
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
234 
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
235 
    /* 16 - 22 */
236 
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
237 
    /* 23, 24 */
238 
    "", "",
239 
    /* floating point registers 25 - 40 */
240 
    "", "", "", "", "", "", "", "",
241 
    "", "", "", "", "", "", "", "",
242 
    /* 41, 42 */
243 
    "", "",
244 
    /* 43 - 62.  Banked registers.  The bank number used is determined by
245 
       the bank register (63). */
246 
    "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
247 
    "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
248 
    "machb", "ivnb", "prb", "gbrb", "maclb",
249 
    /* 63: register bank number, not a real register but used to
250 
       communicate the register bank currently get/set.  This register
251 
       is hidden to the user, who manipulates it using the pseudo
252 
       register called "bank" (67).  See below.  */
253 
    "",
254 
    /* 64 - 66 */
255 
    "ibcr", "ibnr", "tbr",
256 
    /* 67: register bank number, the user visible pseudo register.  */
257 
    "bank",
258 
    /* double precision (pseudo) 68 - 75 */
259 
    "", "", "", "", "", "", "", "",
260 
  };
261 
  if (reg_nr < 0)
262 
    return NULL;
263 
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
264 
    return NULL;
265 
  return register_names[reg_nr];
266 
}
267 
 
268 
static const char *
269 
sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
270 
{
271 
  static char *register_names[] = {
272 
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
273 
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
274 
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
275 
    "", "dsr",
276 
    "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
277 
    "y0", "y1", "", "", "", "", "", "mod",
278 
    "", "",
279 
    "rs", "re", "", "", "", "", "", "",
280 
    "", "", "", "", "", "", "", "",
281 
    "", "", "", "", "", "", "", "",
282 
  };
283 
  if (reg_nr < 0)
284 
    return NULL;
285 
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
286 
    return NULL;
287 
  return register_names[reg_nr];
288 
}
289 
 
290 
static const char *
291 
sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
292 
{
293 
  static char *register_names[] = {
294 
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
295 
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
296 
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
297 
    "", "dsr",
298 
    "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
299 
    "y0", "y1", "", "", "", "", "", "mod",
300 
    "ssr", "spc",
301 
    "rs", "re", "", "", "", "", "", "",
302 
    "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
303 
    "", "", "", "", "", "", "", "",
304 
    "", "", "", "", "", "", "", "",
305 
  };
306 
  if (reg_nr < 0)
307 
    return NULL;
308 
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
309 
    return NULL;
310 
  return register_names[reg_nr];
311 
}
312 
 
313 
static const char *
314 
sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr)
315 
{
316 
  static char *register_names[] = {
317 
    /* general registers 0-15 */
318 
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
319 
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
320 
    /* 16 - 22 */
321 
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
322 
    /* 23, 24 */
323 
    "fpul", "fpscr",
324 
    /* floating point registers 25 - 40 */
325 
    "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
326 
    "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
327 
    /* 41, 42 */
328 
    "ssr", "spc",
329 
    /* bank 0 43 - 50 */
330 
    "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
331 
    /* bank 1 51 - 58 */
332 
    "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
333 
    "", "", "", "", "", "", "", "",
334 
    /* pseudo bank register. */
335 
    "",
336 
    /* double precision (pseudo) 59 - 66 */
337 
    "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
338 
    /* vectors (pseudo) 67 - 70 */
339 
    "fv0", "fv4", "fv8", "fv12",
340 
    /* FIXME: missing XF 71 - 86 */
341 
    /* FIXME: missing XD 87 - 94 */
342 
  };
343 
  if (reg_nr < 0)
344 
    return NULL;
345 
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
346 
    return NULL;
347 
  return register_names[reg_nr];
348 
}
349 
 
350 
static const char *
351 
sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
352 
{
353 
  static char *register_names[] = {
354 
    /* general registers 0-15 */
355 
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
356 
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
357 
    /* 16 - 22 */
358 
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
359 
    /* 23, 24 */
360 
    "", "",
361 
    /* floating point registers 25 - 40 -- not for nofpu target */
362 
    "", "", "", "", "", "", "", "",
363 
    "", "", "", "", "", "", "", "",
364 
    /* 41, 42 */
365 
    "ssr", "spc",
366 
    /* bank 0 43 - 50 */
367 
    "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
368 
    /* bank 1 51 - 58 */
369 
    "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
370 
    "", "", "", "", "", "", "", "",
371 
    /* pseudo bank register. */
372 
    "",
373 
    /* double precision (pseudo) 59 - 66 -- not for nofpu target */
374 
    "", "", "", "", "", "", "", "",
375 
    /* vectors (pseudo) 67 - 70 -- not for nofpu target */
376 
    "", "", "", "",
377 
  };
378 
  if (reg_nr < 0)
379 
    return NULL;
380 
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
381 
    return NULL;
382 
  return register_names[reg_nr];
383 
}
384 
 
385 
static const char *
386 
sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
387 
{
388 
  static char *register_names[] = {
389 
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
390 
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
391 
    "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
392 
    "", "dsr",
393 
    "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
394 
    "y0", "y1", "", "", "", "", "", "mod",
395 
    "ssr", "spc",
396 
    "rs", "re", "", "", "", "", "", "",
397 
    "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
398 
    "", "", "", "", "", "", "", "",
399 
    "", "", "", "", "", "", "", "",
400 
  };
401 
  if (reg_nr < 0)
402 
    return NULL;
403 
  if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
404 
    return NULL;
405 
  return register_names[reg_nr];
406 
}
407 
 
408 
static const unsigned char *
409 
sh_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
410 
{
411 
  /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
412 
  static unsigned char breakpoint[] = { 0xc3, 0xc3 };
413 
 
414 
  /* For remote stub targets, trapa #20 is used.  */
415 
  if (strcmp (target_shortname, "remote") == 0)
416 
    {
417 
      static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
418 
      static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };
419 
 
420 
      if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
421 
        {
422 
          *lenptr = sizeof (big_remote_breakpoint);
423 
          return big_remote_breakpoint;
424 
        }
425 
      else
426 
        {
427 
          *lenptr = sizeof (little_remote_breakpoint);
428 
          return little_remote_breakpoint;
429 
        }
430 
    }
431 
 
432 
  *lenptr = sizeof (breakpoint);
433 
  return breakpoint;
434 
}
435 
 
436 
/* Prologue looks like
437 
   mov.l        r14,@-r15
438 
   sts.l        pr,@-r15
439 
   mov.l        <regs>,@-r15
440 
   sub          <room_for_loca_vars>,r15
441 
   mov          r15,r14
442 
 
443 
   Actually it can be more complicated than this but that's it, basically.
444 
 */
445 
 
446 
#define GET_SOURCE_REG(x)       (((x) >> 4) & 0xf)
447 
#define GET_TARGET_REG(x)       (((x) >> 8) & 0xf)
448 
 
449 
/* JSR @Rm         0100mmmm00001011 */
450 
#define IS_JSR(x)               (((x) & 0xf0ff) == 0x400b)
451 
 
452 
/* STS.L PR,@-r15  0100111100100010
453 
   r15-4-->r15, PR-->(r15) */
454 
#define IS_STS(x)               ((x) == 0x4f22)
455 
 
456 
/* STS.L MACL,@-r15  0100111100010010
457 
   r15-4-->r15, MACL-->(r15) */
458 
#define IS_MACL_STS(x)          ((x) == 0x4f12)
459 
 
460 
/* MOV.L Rm,@-r15  00101111mmmm0110
461 
   r15-4-->r15, Rm-->(R15) */
462 
#define IS_PUSH(x)              (((x) & 0xff0f) == 0x2f06)
463 
 
464 
/* MOV r15,r14     0110111011110011
465 
   r15-->r14  */
466 
#define IS_MOV_SP_FP(x)         ((x) == 0x6ef3)
467 
 
468 
/* ADD #imm,r15    01111111iiiiiiii
469 
   r15+imm-->r15 */
470 
#define IS_ADD_IMM_SP(x)        (((x) & 0xff00) == 0x7f00)
471 
 
472 
#define IS_MOV_R3(x)            (((x) & 0xff00) == 0x1a00)
473 
#define IS_SHLL_R3(x)           ((x) == 0x4300)
474 
 
475 
/* ADD r3,r15      0011111100111100
476 
   r15+r3-->r15 */
477 
#define IS_ADD_R3SP(x)          ((x) == 0x3f3c)
478 
 
479 
/* FMOV.S FRm,@-Rn  Rn-4-->Rn, FRm-->(Rn)     1111nnnnmmmm1011
480 
   FMOV DRm,@-Rn    Rn-8-->Rn, DRm-->(Rn)     1111nnnnmmm01011
481 
   FMOV XDm,@-Rn    Rn-8-->Rn, XDm-->(Rn)     1111nnnnmmm11011 */
482 
/* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
483 
                   make this entirely clear. */
484 
/* #define IS_FMOV(x)           (((x) & 0xf00f) == 0xf00b) */
485 
#define IS_FPUSH(x)             (((x) & 0xff0f) == 0xff0b)
486 
 
487 
/* MOV Rm,Rn          Rm-->Rn        0110nnnnmmmm0011  4 <= m <= 7 */
488 
#define IS_MOV_ARG_TO_REG(x) \
489 
        (((x) & 0xf00f) == 0x6003 && \
490 
         ((x) & 0x00f0) >= 0x0040 && \
491 
         ((x) & 0x00f0) <= 0x0070)
492 
/* MOV.L Rm,@Rn               0010nnnnmmmm0010  n = 14, 4 <= m <= 7 */
493 
#define IS_MOV_ARG_TO_IND_R14(x) \
494 
        (((x) & 0xff0f) == 0x2e02 && \
495 
         ((x) & 0x00f0) >= 0x0040 && \
496 
         ((x) & 0x00f0) <= 0x0070)
497 
/* MOV.L Rm,@(disp*4,Rn)      00011110mmmmdddd  n = 14, 4 <= m <= 7 */
498 
#define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
499 
        (((x) & 0xff00) == 0x1e00 && \
500 
         ((x) & 0x00f0) >= 0x0040 && \
501 
         ((x) & 0x00f0) <= 0x0070)
502 
 
503 
/* MOV.W @(disp*2,PC),Rn      1001nnnndddddddd */
504 
#define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
505 
/* MOV.L @(disp*4,PC),Rn      1101nnnndddddddd */
506 
#define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
507 
/* MOVI20 #imm20,Rn           0000nnnniiii0000 */
508 
#define IS_MOVI20(x)            (((x) & 0xf00f) == 0x0000)
509 
/* SUB Rn,R15                 00111111nnnn1000 */
510 
#define IS_SUB_REG_FROM_SP(x)   (((x) & 0xff0f) == 0x3f08)
511 
 
512 
#define FPSCR_SZ                (1 << 20)
513 
 
514 
/* The following instructions are used for epilogue testing. */
515 
#define IS_RESTORE_FP(x)        ((x) == 0x6ef6)
516 
#define IS_RTS(x)               ((x) == 0x000b)
517 
#define IS_LDS(x)               ((x) == 0x4f26)
518 
#define IS_MACL_LDS(x)          ((x) == 0x4f16)
519 
#define IS_MOV_FP_SP(x)         ((x) == 0x6fe3)
520 
#define IS_ADD_REG_TO_FP(x)     (((x) & 0xff0f) == 0x3e0c)
521 
#define IS_ADD_IMM_FP(x)        (((x) & 0xff00) == 0x7e00)
522 
 
523 
static CORE_ADDR
524 
sh_analyze_prologue (struct gdbarch *gdbarch,
525 
                     CORE_ADDR pc, CORE_ADDR current_pc,
526 
                     struct sh_frame_cache *cache, ULONGEST fpscr)
527 
{
528 
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
529 
  ULONGEST inst;
530 
  CORE_ADDR opc;
531 
  int offset;
532 
  int sav_offset = 0;
533 
  int r3_val = 0;
534 
  int reg, sav_reg = -1;
535 
 
536 
  if (pc >= current_pc)
537 
    return current_pc;
538 
 
539 
  cache->uses_fp = 0;
540 
  for (opc = pc + (2 * 28); pc < opc; pc += 2)
541 
    {
542 
      inst = read_memory_unsigned_integer (pc, 2, byte_order);
543 
      /* See where the registers will be saved to */
544 
      if (IS_PUSH (inst))
545 
        {
546 
          cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
547 
          cache->sp_offset += 4;
548 
        }
549 
      else if (IS_STS (inst))
550 
        {
551 
          cache->saved_regs[PR_REGNUM] = cache->sp_offset;
552 
          cache->sp_offset += 4;
553 
        }
554 
      else if (IS_MACL_STS (inst))
555 
        {
556 
          cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
557 
          cache->sp_offset += 4;
558 
        }
559 
      else if (IS_MOV_R3 (inst))
560 
        {
561 
          r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
562 
        }
563 
      else if (IS_SHLL_R3 (inst))
564 
        {
565 
          r3_val <<= 1;
566 
        }
567 
      else if (IS_ADD_R3SP (inst))
568 
        {
569 
          cache->sp_offset += -r3_val;
570 
        }
571 
      else if (IS_ADD_IMM_SP (inst))
572 
        {
573 
          offset = ((inst & 0xff) ^ 0x80) - 0x80;
574 
          cache->sp_offset -= offset;
575 
        }
576 
      else if (IS_MOVW_PCREL_TO_REG (inst))
577 
        {
578 
          if (sav_reg < 0)
579 
            {
580 
              reg = GET_TARGET_REG (inst);
581 
              if (reg < 14)
582 
                {
583 
                  sav_reg = reg;
584 
                  offset = (inst & 0xff) << 1;
585 
                  sav_offset =
586 
                    read_memory_integer ((pc + 4) + offset, 2, byte_order);
587 
                }
588 
            }
589 
        }
590 
      else if (IS_MOVL_PCREL_TO_REG (inst))
591 
        {
592 
          if (sav_reg < 0)
593 
            {
594 
              reg = GET_TARGET_REG (inst);
595 
              if (reg < 14)
596 
                {
597 
                  sav_reg = reg;
598 
                  offset = (inst & 0xff) << 2;
599 
                  sav_offset =
600 
                    read_memory_integer (((pc & 0xfffffffc) + 4) + offset,
601 
                                         4, byte_order);
602 
                }
603 
            }
604 
        }
605 
      else if (IS_MOVI20 (inst))
606 
        {
607 
          if (sav_reg < 0)
608 
            {
609 
              reg = GET_TARGET_REG (inst);
610 
              if (reg < 14)
611 
                {
612 
                  sav_reg = reg;
613 
                  sav_offset = GET_SOURCE_REG (inst) << 16;
614 
                  /* MOVI20 is a 32 bit instruction! */
615 
                  pc += 2;
616 
                  sav_offset
617 
                    |= read_memory_unsigned_integer (pc, 2, byte_order);
618 
                  /* Now sav_offset contains an unsigned 20 bit value.
619 
                     It must still get sign extended.  */
620 
                  if (sav_offset & 0x00080000)
621 
                    sav_offset |= 0xfff00000;
622 
                }
623 
            }
624 
        }
625 
      else if (IS_SUB_REG_FROM_SP (inst))
626 
        {
627 
          reg = GET_SOURCE_REG (inst);
628 
          if (sav_reg > 0 && reg == sav_reg)
629 
            {
630 
              sav_reg = -1;
631 
            }
632 
          cache->sp_offset += sav_offset;
633 
        }
634 
      else if (IS_FPUSH (inst))
635 
        {
636 
          if (fpscr & FPSCR_SZ)
637 
            {
638 
              cache->sp_offset += 8;
639 
            }
640 
          else
641 
            {
642 
              cache->sp_offset += 4;
643 
            }
644 
        }
645 
      else if (IS_MOV_SP_FP (inst))
646 
        {
647 
          cache->uses_fp = 1;
648 
          /* At this point, only allow argument register moves to other
649 
             registers or argument register moves to @(X,fp) which are
650 
             moving the register arguments onto the stack area allocated
651 
             by a former add somenumber to SP call.  Don't allow moving
652 
             to an fp indirect address above fp + cache->sp_offset. */
653 
          pc += 2;
654 
          for (opc = pc + 12; pc < opc; pc += 2)
655 
            {
656 
              inst = read_memory_integer (pc, 2, byte_order);
657 
              if (IS_MOV_ARG_TO_IND_R14 (inst))
658 
                {
659 
                  reg = GET_SOURCE_REG (inst);
660 
                  if (cache->sp_offset > 0)
661 
                    cache->saved_regs[reg] = cache->sp_offset;
662 
                }
663 
              else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
664 
                {
665 
                  reg = GET_SOURCE_REG (inst);
666 
                  offset = (inst & 0xf) * 4;
667 
                  if (cache->sp_offset > offset)
668 
                    cache->saved_regs[reg] = cache->sp_offset - offset;
669 
                }
670 
              else if (IS_MOV_ARG_TO_REG (inst))
671 
                continue;
672 
              else
673 
                break;
674 
            }
675 
          break;
676 
        }
677 
      else if (IS_JSR (inst))
678 
        {
679 
          /* We have found a jsr that has been scheduled into the prologue.
680 
             If we continue the scan and return a pc someplace after this,
681 
             then setting a breakpoint on this function will cause it to
682 
             appear to be called after the function it is calling via the
683 
             jsr, which will be very confusing.  Most likely the next
684 
             instruction is going to be IS_MOV_SP_FP in the delay slot.  If
685 
             so, note that before returning the current pc. */
686 
          inst = read_memory_integer (pc + 2, 2, byte_order);
687 
          if (IS_MOV_SP_FP (inst))
688 
            cache->uses_fp = 1;
689 
          break;
690 
        }
691 
#if 0                           /* This used to just stop when it found an instruction that
692 
                                   was not considered part of the prologue.  Now, we just
693 
                                   keep going looking for likely instructions. */
694 
      else
695 
        break;
696 
#endif
697 
    }
698 
 
699 
  return pc;
700 
}
701 
 
702 
/* Skip any prologue before the guts of a function */
703 
 
704 
/* Skip the prologue using the debug information. If this fails we'll
705 
   fall back on the 'guess' method below. */
706 
static CORE_ADDR
707 
after_prologue (CORE_ADDR pc)
708 
{
709 
  struct symtab_and_line sal;
710 
  CORE_ADDR func_addr, func_end;
711 
 
712 
  /* If we can not find the symbol in the partial symbol table, then
713 
     there is no hope we can determine the function's start address
714 
     with this code.  */
715 
  if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
716 
    return 0;
717 
 
718 
  /* Get the line associated with FUNC_ADDR.  */
719 
  sal = find_pc_line (func_addr, 0);
720 
 
721 
  /* There are only two cases to consider.  First, the end of the source line
722 
     is within the function bounds.  In that case we return the end of the
723 
     source line.  Second is the end of the source line extends beyond the
724 
     bounds of the current function.  We need to use the slow code to
725 
     examine instructions in that case.  */
726 
  if (sal.end < func_end)
727 
    return sal.end;
728 
  else
729 
    return 0;
730 
}
731 
 
732 
static CORE_ADDR
733 
sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
734 
{
735 
  CORE_ADDR pc;
736 
  struct sh_frame_cache cache;
737 
 
738 
  /* See if we can determine the end of the prologue via the symbol table.
739 
     If so, then return either PC, or the PC after the prologue, whichever
740 
     is greater.  */
741 
  pc = after_prologue (start_pc);
742 
 
743 
  /* If after_prologue returned a useful address, then use it.  Else
744 
     fall back on the instruction skipping code. */
745 
  if (pc)
746 
    return max (pc, start_pc);
747 
 
748 
  cache.sp_offset = -4;
749 
  pc = sh_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache, 0);
750 
  if (!cache.uses_fp)
751 
    return start_pc;
752 
 
753 
  return pc;
754 
}
755 
 
756 
/* The ABI says:
757 
 
758 
   Aggregate types not bigger than 8 bytes that have the same size and
759 
   alignment as one of the integer scalar types are returned in the
760 
   same registers as the integer type they match.
761 
 
762 
   For example, a 2-byte aligned structure with size 2 bytes has the
763 
   same size and alignment as a short int, and will be returned in R0.
764 
   A 4-byte aligned structure with size 8 bytes has the same size and
765 
   alignment as a long long int, and will be returned in R0 and R1.
766 
 
767 
   When an aggregate type is returned in R0 and R1, R0 contains the
768 
   first four bytes of the aggregate, and R1 contains the
769 
   remainder. If the size of the aggregate type is not a multiple of 4
770 
   bytes, the aggregate is tail-padded up to a multiple of 4
771 
   bytes. The value of the padding is undefined. For little-endian
772 
   targets the padding will appear at the most significant end of the
773 
   last element, for big-endian targets the padding appears at the
774 
   least significant end of the last element.
775 
 
776 
   All other aggregate types are returned by address. The caller
777 
   function passes the address of an area large enough to hold the
778 
   aggregate value in R2. The called function stores the result in
779 
   this location.
780 
 
781 
   To reiterate, structs smaller than 8 bytes could also be returned
782 
   in memory, if they don't pass the "same size and alignment as an
783 
   integer type" rule.
784 
 
785 
   For example, in
786 
 
787 
   struct s { char c[3]; } wibble;
788 
   struct s foo(void) {  return wibble; }
789 
 
790 
   the return value from foo() will be in memory, not
791 
   in R0, because there is no 3-byte integer type.
792 
 
793 
   Similarly, in
794 
 
795 
   struct s { char c[2]; } wibble;
796 
   struct s foo(void) {  return wibble; }
797 
 
798 
   because a struct containing two chars has alignment 1, that matches
799 
   type char, but size 2, that matches type short.  There's no integer
800 
   type that has alignment 1 and size 2, so the struct is returned in
801 
   memory.
802 
 
803 
*/
804 
 
805 
static int
806 
sh_use_struct_convention (int renesas_abi, struct type *type)
807 
{
808 
  int len = TYPE_LENGTH (type);
809 
  int nelem = TYPE_NFIELDS (type);
810 
 
811 
  /* The Renesas ABI returns aggregate types always on stack.  */
812 
  if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT
813 
                      || TYPE_CODE (type) == TYPE_CODE_UNION))
814 
    return 1;
815 
 
816 
  /* Non-power of 2 length types and types bigger than 8 bytes (which don't
817 
     fit in two registers anyway) use struct convention.  */
818 
  if (len != 1 && len != 2 && len != 4 && len != 8)
819 
    return 1;
820 
 
821 
  /* Scalar types and aggregate types with exactly one field are aligned
822 
     by definition.  They are returned in registers.  */
823 
  if (nelem <= 1)
824 
    return 0;
825 
 
826 
  /* If the first field in the aggregate has the same length as the entire
827 
     aggregate type, the type is returned in registers.  */
828 
  if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
829 
    return 0;
830 
 
831 
  /* If the size of the aggregate is 8 bytes and the first field is
832 
     of size 4 bytes its alignment is equal to long long's alignment,
833 
     so it's returned in registers.  */
834 
  if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
835 
    return 0;
836 
 
837 
  /* Otherwise use struct convention.  */
838 
  return 1;
839 
}
840 
 
841 
static int
842 
sh_use_struct_convention_nofpu (int renesas_abi, struct type *type)
843 
{
844 
  /* The Renesas ABI returns long longs/doubles etc. always on stack.  */
845 
  if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8)
846 
    return 1;
847 
  return sh_use_struct_convention (renesas_abi, type);
848 
}
849 
 
850 
static CORE_ADDR
851 
sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
852 
{
853 
  return sp & ~3;
854 
}
855 
 
856 
/* Function: push_dummy_call (formerly push_arguments)
857 
   Setup the function arguments for calling a function in the inferior.
858 
 
859 
   On the Renesas SH architecture, there are four registers (R4 to R7)
860 
   which are dedicated for passing function arguments.  Up to the first
861 
   four arguments (depending on size) may go into these registers.
862 
   The rest go on the stack.
863 
 
864 
   MVS: Except on SH variants that have floating point registers.
865 
   In that case, float and double arguments are passed in the same
866 
   manner, but using FP registers instead of GP registers.
867 
 
868 
   Arguments that are smaller than 4 bytes will still take up a whole
869 
   register or a whole 32-bit word on the stack, and will be
870 
   right-justified in the register or the stack word.  This includes
871 
   chars, shorts, and small aggregate types.
872 
 
873 
   Arguments that are larger than 4 bytes may be split between two or
874 
   more registers.  If there are not enough registers free, an argument
875 
   may be passed partly in a register (or registers), and partly on the
876 
   stack.  This includes doubles, long longs, and larger aggregates.
877 
   As far as I know, there is no upper limit to the size of aggregates
878 
   that will be passed in this way; in other words, the convention of
879 
   passing a pointer to a large aggregate instead of a copy is not used.
880 
 
881 
   MVS: The above appears to be true for the SH variants that do not
882 
   have an FPU, however those that have an FPU appear to copy the
883 
   aggregate argument onto the stack (and not place it in registers)
884 
   if it is larger than 16 bytes (four GP registers).
885 
 
886 
   An exceptional case exists for struct arguments (and possibly other
887 
   aggregates such as arrays) if the size is larger than 4 bytes but
888 
   not a multiple of 4 bytes.  In this case the argument is never split
889 
   between the registers and the stack, but instead is copied in its
890 
   entirety onto the stack, AND also copied into as many registers as
891 
   there is room for.  In other words, space in registers permitting,
892 
   two copies of the same argument are passed in.  As far as I can tell,
893 
   only the one on the stack is used, although that may be a function
894 
   of the level of compiler optimization.  I suspect this is a compiler
895 
   bug.  Arguments of these odd sizes are left-justified within the
896 
   word (as opposed to arguments smaller than 4 bytes, which are
897 
   right-justified).
898 
 
899 
   If the function is to return an aggregate type such as a struct, it
900 
   is either returned in the normal return value register R0 (if its
901 
   size is no greater than one byte), or else the caller must allocate
902 
   space into which the callee will copy the return value (if the size
903 
   is greater than one byte).  In this case, a pointer to the return
904 
   value location is passed into the callee in register R2, which does
905 
   not displace any of the other arguments passed in via registers R4
906 
   to R7.   */
907 
 
908 
/* Helper function to justify value in register according to endianess. */
909 
static char *
910 
sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len)
911 
{
912 
  static char valbuf[4];
913 
 
914 
  memset (valbuf, 0, sizeof (valbuf));
915 
  if (len < 4)
916 
    {
917 
      /* value gets right-justified in the register or stack word */
918 
      if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
919 
        memcpy (valbuf + (4 - len), (char *) value_contents (val), len);
920 
      else
921 
        memcpy (valbuf, (char *) value_contents (val), len);
922 
      return valbuf;
923 
    }
924 
  return (char *) value_contents (val);
925 
}
926 
 
927 
/* Helper function to eval number of bytes to allocate on stack. */
928 
static CORE_ADDR
929 
sh_stack_allocsize (int nargs, struct value **args)
930 
{
931 
  int stack_alloc = 0;
932 
  while (nargs-- > 0)
933 
    stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
934 
  return stack_alloc;
935 
}
936 
 
937 
/* Helper functions for getting the float arguments right.  Registers usage
938 
   depends on the ABI and the endianess.  The comments should enlighten how
939 
   it's intended to work. */
940 
 
941 
/* This array stores which of the float arg registers are already in use. */
942 
static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
943 
 
944 
/* This function just resets the above array to "no reg used so far". */
945 
static void
946 
sh_init_flt_argreg (void)
947 
{
948 
  memset (flt_argreg_array, 0, sizeof flt_argreg_array);
949 
}
950 
 
951 
/* This function returns the next register to use for float arg passing.
952 
   It returns either a valid value between FLOAT_ARG0_REGNUM and
953 
   FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
954 
   FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
955 
 
956 
   Note that register number 0 in flt_argreg_array corresponds with the
957 
   real float register fr4.  In contrast to FLOAT_ARG0_REGNUM (value is
958 
   29) the parity of the register number is preserved, which is important
959 
   for the double register passing test (see the "argreg & 1" test below). */
960 
static int
961 
sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type)
962 
{
963 
  int argreg;
964 
 
965 
  /* First search for the next free register. */
966 
  for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
967 
       ++argreg)
968 
    if (!flt_argreg_array[argreg])
969 
      break;
970 
 
971 
  /* No register left? */
972 
  if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
973 
    return FLOAT_ARGLAST_REGNUM + 1;
974 
 
975 
  if (len == 8)
976 
    {
977 
      /* Doubles are always starting in a even register number. */
978 
      if (argreg & 1)
979 
        {
980 
          /* In gcc ABI, the skipped register is lost for further argument
981 
             passing now.  Not so in Renesas ABI.  */
982 
          if (!sh_is_renesas_calling_convention (func_type))
983 
            flt_argreg_array[argreg] = 1;
984 
 
985 
          ++argreg;
986 
 
987 
          /* No register left? */
988 
          if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
989 
            return FLOAT_ARGLAST_REGNUM + 1;
990 
        }
991 
      /* Also mark the next register as used. */
992 
      flt_argreg_array[argreg + 1] = 1;
993 
    }
994 
  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
995 
           && !sh_is_renesas_calling_convention (func_type))
996 
    {
997 
      /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
998 
      if (!flt_argreg_array[argreg + 1])
999 
        ++argreg;
1000 
    }
1001 
  flt_argreg_array[argreg] = 1;
1002 
  return FLOAT_ARG0_REGNUM + argreg;
1003 
}
1004 
 
1005 
/* Helper function which figures out, if a type is treated like a float type.
1006 
 
1007 
   The FPU ABIs have a special way how to treat types as float types.
1008 
   Structures with exactly one member, which is of type float or double, are
1009 
   treated exactly as the base types float or double:
1010 
 
1011 
     struct sf {
1012 
       float f;
1013 
     };
1014 
 
1015 
     struct sd {
1016 
       double d;
1017 
     };
1018 
 
1019 
   are handled the same way as just
1020 
 
1021 
     float f;
1022 
 
1023 
     double d;
1024 
 
1025 
   As a result, arguments of these struct types are pushed into floating point
1026 
   registers exactly as floats or doubles, using the same decision algorithm.
1027 
 
1028 
   The same is valid if these types are used as function return types.  The
1029 
   above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1030 
   or even using struct convention as it is for other structs.  */
1031 
 
1032 
static int
1033 
sh_treat_as_flt_p (struct type *type)
1034 
{
1035 
  int len = TYPE_LENGTH (type);
1036 
 
1037 
  /* Ordinary float types are obviously treated as float.  */
1038 
  if (TYPE_CODE (type) == TYPE_CODE_FLT)
1039 
    return 1;
1040 
  /* Otherwise non-struct types are not treated as float.  */
1041 
  if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
1042 
    return 0;
1043 
  /* Otherwise structs with more than one memeber are not treated as float.  */
1044 
  if (TYPE_NFIELDS (type) != 1)
1045 
    return 0;
1046 
  /* Otherwise if the type of that member is float, the whole type is
1047 
     treated as float.  */
1048 
  if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
1049 
    return 1;
1050 
  /* Otherwise it's not treated as float.  */
1051 
  return 0;
1052 
}
1053 
 
1054 
static CORE_ADDR
1055 
sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
1056 
                        struct value *function,
1057 
                        struct regcache *regcache,
1058 
                        CORE_ADDR bp_addr, int nargs,
1059 
                        struct value **args,
1060 
                        CORE_ADDR sp, int struct_return,
1061 
                        CORE_ADDR struct_addr)
1062 
{
1063 
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1064 
  int stack_offset = 0;
1065 
  int argreg = ARG0_REGNUM;
1066 
  int flt_argreg = 0;
1067 
  int argnum;
1068 
  struct type *func_type = value_type (function);
1069 
  struct type *type;
1070 
  CORE_ADDR regval;
1071 
  char *val;
1072 
  int len, reg_size = 0;
1073 
  int pass_on_stack = 0;
1074 
  int treat_as_flt;
1075 
  int last_reg_arg = INT_MAX;
1076 
 
1077 
  /* The Renesas ABI expects all varargs arguments, plus the last
1078 
     non-vararg argument to be on the stack, no matter how many
1079 
     registers have been used so far.  */
1080 
  if (sh_is_renesas_calling_convention (func_type)
1081 
      && TYPE_VARARGS (func_type))
1082 
    last_reg_arg = TYPE_NFIELDS (func_type) - 2;
1083 
 
1084 
  /* first force sp to a 4-byte alignment */
1085 
  sp = sh_frame_align (gdbarch, sp);
1086 
 
1087 
  /* make room on stack for args */
1088 
  sp -= sh_stack_allocsize (nargs, args);
1089 
 
1090 
  /* Initialize float argument mechanism. */
1091 
  sh_init_flt_argreg ();
1092 
 
1093 
  /* Now load as many as possible of the first arguments into
1094 
     registers, and push the rest onto the stack.  There are 16 bytes
1095 
     in four registers available.  Loop thru args from first to last.  */
1096 
  for (argnum = 0; argnum < nargs; argnum++)
1097 
    {
1098 
      type = value_type (args[argnum]);
1099 
      len = TYPE_LENGTH (type);
1100 
      val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
1101 
 
1102 
      /* Some decisions have to be made how various types are handled.
1103 
         This also differs in different ABIs. */
1104 
      pass_on_stack = 0;
1105 
 
1106 
      /* Find out the next register to use for a floating point value. */
1107 
      treat_as_flt = sh_treat_as_flt_p (type);
1108 
      if (treat_as_flt)
1109 
        flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type);
1110 
      /* In Renesas ABI, long longs and aggregate types are always passed
1111 
         on stack.  */
1112 
      else if (sh_is_renesas_calling_convention (func_type)
1113 
               && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8)
1114 
                   || TYPE_CODE (type) == TYPE_CODE_STRUCT
1115 
                   || TYPE_CODE (type) == TYPE_CODE_UNION))
1116 
        pass_on_stack = 1;
1117 
      /* In contrast to non-FPU CPUs, arguments are never split between
1118 
         registers and stack.  If an argument doesn't fit in the remaining
1119 
         registers it's always pushed entirely on the stack.  */
1120 
      else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1121 
        pass_on_stack = 1;
1122 
 
1123 
      while (len > 0)
1124 
        {
1125 
          if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1126 
              || (!treat_as_flt && (argreg > ARGLAST_REGNUM
1127 
                                    || pass_on_stack))
1128 
              || argnum > last_reg_arg)
1129 
            {
1130 
              /* The data goes entirely on the stack, 4-byte aligned. */
1131 
              reg_size = (len + 3) & ~3;
1132 
              write_memory (sp + stack_offset, val, reg_size);
1133 
              stack_offset += reg_size;
1134 
            }
1135 
          else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
1136 
            {
1137 
              /* Argument goes in a float argument register.  */
1138 
              reg_size = register_size (gdbarch, flt_argreg);
1139 
              regval = extract_unsigned_integer (val, reg_size, byte_order);
1140 
              /* In little endian mode, float types taking two registers
1141 
                 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1142 
                 be stored swapped in the argument registers.  The below
1143 
                 code first writes the first 32 bits in the next but one
1144 
                 register, increments the val and len values accordingly
1145 
                 and then proceeds as normal by writing the second 32 bits
1146 
                 into the next register. */
1147 
              if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
1148 
                  && TYPE_LENGTH (type) == 2 * reg_size)
1149 
                {
1150 
                  regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1151 
                                                  regval);
1152 
                  val += reg_size;
1153 
                  len -= reg_size;
1154 
                  regval = extract_unsigned_integer (val, reg_size, byte_order);
1155 
                }
1156 
              regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1157 
            }
1158 
          else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
1159 
            {
1160 
              /* there's room in a register */
1161 
              reg_size = register_size (gdbarch, argreg);
1162 
              regval = extract_unsigned_integer (val, reg_size, byte_order);
1163 
              regcache_cooked_write_unsigned (regcache, argreg++, regval);
1164 
            }
1165 
          /* Store the value one register at a time or in one step on stack.  */
1166 
          len -= reg_size;
1167 
          val += reg_size;
1168 
        }
1169 
    }
1170 
 
1171 
  if (struct_return)
1172 
    {
1173 
      if (sh_is_renesas_calling_convention (func_type))
1174 
        /* If the function uses the Renesas ABI, subtract another 4 bytes from
1175 
           the stack and store the struct return address there.  */
1176 
        write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
1177 
      else
1178 
        /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1179 
           its own dedicated register.  */
1180 
        regcache_cooked_write_unsigned (regcache,
1181 
                                        STRUCT_RETURN_REGNUM, struct_addr);
1182 
    }
1183 
 
1184 
  /* Store return address. */
1185 
  regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1186 
 
1187 
  /* Update stack pointer.  */
1188 
  regcache_cooked_write_unsigned (regcache,
1189 
                                  gdbarch_sp_regnum (gdbarch), sp);
1190 
 
1191 
  return sp;
1192 
}
1193 
 
1194 
static CORE_ADDR
1195 
sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
1196 
                          struct value *function,
1197 
                          struct regcache *regcache,
1198 
                          CORE_ADDR bp_addr,
1199 
                          int nargs, struct value **args,
1200 
                          CORE_ADDR sp, int struct_return,
1201 
                          CORE_ADDR struct_addr)
1202 
{
1203 
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1204 
  int stack_offset = 0;
1205 
  int argreg = ARG0_REGNUM;
1206 
  int argnum;
1207 
  struct type *func_type = value_type (function);
1208 
  struct type *type;
1209 
  CORE_ADDR regval;
1210 
  char *val;
1211 
  int len, reg_size = 0;
1212 
  int pass_on_stack = 0;
1213 
  int last_reg_arg = INT_MAX;
1214 
 
1215 
  /* The Renesas ABI expects all varargs arguments, plus the last
1216 
     non-vararg argument to be on the stack, no matter how many
1217 
     registers have been used so far.  */
1218 
  if (sh_is_renesas_calling_convention (func_type)
1219 
      && TYPE_VARARGS (func_type))
1220 
    last_reg_arg = TYPE_NFIELDS (func_type) - 2;
1221 
 
1222 
  /* first force sp to a 4-byte alignment */
1223 
  sp = sh_frame_align (gdbarch, sp);
1224 
 
1225 
  /* make room on stack for args */
1226 
  sp -= sh_stack_allocsize (nargs, args);
1227 
 
1228 
  /* Now load as many as possible of the first arguments into
1229 
     registers, and push the rest onto the stack.  There are 16 bytes
1230 
     in four registers available.  Loop thru args from first to last.  */
1231 
  for (argnum = 0; argnum < nargs; argnum++)
1232 
    {
1233 
      type = value_type (args[argnum]);
1234 
      len = TYPE_LENGTH (type);
1235 
      val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
1236 
 
1237 
      /* Some decisions have to be made how various types are handled.
1238 
         This also differs in different ABIs. */
1239 
      pass_on_stack = 0;
1240 
      /* Renesas ABI pushes doubles and long longs entirely on stack.
1241 
         Same goes for aggregate types.  */
1242 
      if (sh_is_renesas_calling_convention (func_type)
1243 
          && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8)
1244 
              || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8)
1245 
              || TYPE_CODE (type) == TYPE_CODE_STRUCT
1246 
              || TYPE_CODE (type) == TYPE_CODE_UNION))
1247 
        pass_on_stack = 1;
1248 
      while (len > 0)
1249 
        {
1250 
          if (argreg > ARGLAST_REGNUM || pass_on_stack
1251 
              || argnum > last_reg_arg)
1252 
            {
1253 
              /* The remainder of the data goes entirely on the stack,
1254 
                 4-byte aligned. */
1255 
              reg_size = (len + 3) & ~3;
1256 
              write_memory (sp + stack_offset, val, reg_size);
1257 
              stack_offset += reg_size;
1258 
            }
1259 
          else if (argreg <= ARGLAST_REGNUM)
1260 
            {
1261 
              /* there's room in a register */
1262 
              reg_size = register_size (gdbarch, argreg);
1263 
              regval = extract_unsigned_integer (val, reg_size, byte_order);
1264 
              regcache_cooked_write_unsigned (regcache, argreg++, regval);
1265 
            }
1266 
          /* Store the value reg_size bytes at a time.  This means that things
1267 
             larger than reg_size bytes may go partly in registers and partly
1268 
             on the stack.  */
1269 
          len -= reg_size;
1270 
          val += reg_size;
1271 
        }
1272 
    }
1273 
 
1274 
  if (struct_return)
1275 
    {
1276 
      if (sh_is_renesas_calling_convention (func_type))
1277 
        /* If the function uses the Renesas ABI, subtract another 4 bytes from
1278 
           the stack and store the struct return address there.  */
1279 
        write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
1280 
      else
1281 
        /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1282 
           its own dedicated register.  */
1283 
        regcache_cooked_write_unsigned (regcache,
1284 
                                        STRUCT_RETURN_REGNUM, struct_addr);
1285 
    }
1286 
 
1287 
  /* Store return address. */
1288 
  regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1289 
 
1290 
  /* Update stack pointer.  */
1291 
  regcache_cooked_write_unsigned (regcache,
1292 
                                  gdbarch_sp_regnum (gdbarch), sp);
1293 
 
1294 
  return sp;
1295 
}
1296 
 
1297 
/* Find a function's return value in the appropriate registers (in
1298 
   regbuf), and copy it into valbuf.  Extract from an array REGBUF
1299 
   containing the (raw) register state a function return value of type
1300 
   TYPE, and copy that, in virtual format, into VALBUF.  */
1301 
static void
1302 
sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
1303 
                               void *valbuf)
1304 
{
1305 
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
1306 
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1307 
  int len = TYPE_LENGTH (type);
1308 
  int return_register = R0_REGNUM;
1309 
  int offset;
1310 
 
1311 
  if (len <= 4)
1312 
    {
1313 
      ULONGEST c;
1314 
 
1315 
      regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1316 
      store_unsigned_integer (valbuf, len, byte_order, c);
1317 
    }
1318 
  else if (len == 8)
1319 
    {
1320 
      int i, regnum = R0_REGNUM;
1321 
      for (i = 0; i < len; i += 4)
1322 
        regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1323 
    }
1324 
  else
1325 
    error (_("bad size for return value"));
1326 
}
1327 
 
1328 
static void
1329 
sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
1330 
                             void *valbuf)
1331 
{
1332 
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
1333 
  if (sh_treat_as_flt_p (type))
1334 
    {
1335 
      int len = TYPE_LENGTH (type);
1336 
      int i, regnum = gdbarch_fp0_regnum (gdbarch);
1337 
      for (i = 0; i < len; i += 4)
1338 
        if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1339 
          regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
1340 
        else
1341 
          regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1342 
    }
1343 
  else
1344 
    sh_extract_return_value_nofpu (type, regcache, valbuf);
1345 
}
1346 
 
1347 
/* Write into appropriate registers a function return value
1348 
   of type TYPE, given in virtual format.
1349 
   If the architecture is sh4 or sh3e, store a function's return value
1350 
   in the R0 general register or in the FP0 floating point register,
1351 
   depending on the type of the return value. In all the other cases
1352 
   the result is stored in r0, left-justified. */
1353 
static void
1354 
sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
1355 
                             const void *valbuf)
1356 
{
1357 
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
1358 
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1359 
  ULONGEST val;
1360 
  int len = TYPE_LENGTH (type);
1361 
 
1362 
  if (len <= 4)
1363 
    {
1364 
      val = extract_unsigned_integer (valbuf, len, byte_order);
1365 
      regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1366 
    }
1367 
  else
1368 
    {
1369 
      int i, regnum = R0_REGNUM;
1370 
      for (i = 0; i < len; i += 4)
1371 
        regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1372 
    }
1373 
}
1374 
 
1375 
static void
1376 
sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
1377 
                           const void *valbuf)
1378 
{
1379 
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
1380 
  if (sh_treat_as_flt_p (type))
1381 
    {
1382 
      int len = TYPE_LENGTH (type);
1383 
      int i, regnum = gdbarch_fp0_regnum (gdbarch);
1384 
      for (i = 0; i < len; i += 4)
1385 
        if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1386 
          regcache_raw_write (regcache, regnum++,
1387 
                              (char *) valbuf + len - 4 - i);
1388 
        else
1389 
          regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1390 
    }
1391 
  else
1392 
    sh_store_return_value_nofpu (type, regcache, valbuf);
1393 
}
1394 
 
1395 
static enum return_value_convention
1396 
sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *func_type,
1397 
                       struct type *type, struct regcache *regcache,
1398 
                       gdb_byte *readbuf, const gdb_byte *writebuf)
1399 
{
1400 
  if (sh_use_struct_convention_nofpu (
1401 
        sh_is_renesas_calling_convention (func_type), type))
1402 
    return RETURN_VALUE_STRUCT_CONVENTION;
1403 
  if (writebuf)
1404 
    sh_store_return_value_nofpu (type, regcache, writebuf);
1405 
  else if (readbuf)
1406 
    sh_extract_return_value_nofpu (type, regcache, readbuf);
1407 
  return RETURN_VALUE_REGISTER_CONVENTION;
1408 
}
1409 
 
1410 
static enum return_value_convention
1411 
sh_return_value_fpu (struct gdbarch *gdbarch, struct type *func_type,
1412 
                     struct type *type, struct regcache *regcache,
1413 
                     gdb_byte *readbuf, const gdb_byte *writebuf)
1414 
{
1415 
  if (sh_use_struct_convention (
1416 
        sh_is_renesas_calling_convention (func_type), type))
1417 
    return RETURN_VALUE_STRUCT_CONVENTION;
1418 
  if (writebuf)
1419 
    sh_store_return_value_fpu (type, regcache, writebuf);
1420 
  else if (readbuf)
1421 
    sh_extract_return_value_fpu (type, regcache, readbuf);
1422 
  return RETURN_VALUE_REGISTER_CONVENTION;
1423 
}
1424 
 
1425 
/* Print the registers in a form similar to the E7000 */
1426 
 
1427 
static void
1428 
sh_generic_show_regs (struct frame_info *frame)
1429 
{
1430 
  printf_filtered
1431 
    ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1432 
     phex (get_frame_register_unsigned (frame,
1433 
                                        gdbarch_pc_regnum
1434 
                                           (get_frame_arch (frame))), 4),
1435 
     (long) get_frame_register_unsigned (frame, SR_REGNUM),
1436 
     (long) get_frame_register_unsigned (frame, PR_REGNUM),
1437 
     (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1438 
 
1439 
  printf_filtered
1440 
    ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1441 
     (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1442 
     (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1443 
     (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1444 
 
1445 
  printf_filtered
1446 
    ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1447 
     (long) get_frame_register_unsigned (frame, 0),
1448 
     (long) get_frame_register_unsigned (frame, 1),
1449 
     (long) get_frame_register_unsigned (frame, 2),
1450 
     (long) get_frame_register_unsigned (frame, 3),
1451 
     (long) get_frame_register_unsigned (frame, 4),
1452 
     (long) get_frame_register_unsigned (frame, 5),
1453 
     (long) get_frame_register_unsigned (frame, 6),
1454 
     (long) get_frame_register_unsigned (frame, 7));
1455 
  printf_filtered
1456 
    ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1457 
     (long) get_frame_register_unsigned (frame, 8),
1458 
     (long) get_frame_register_unsigned (frame, 9),
1459 
     (long) get_frame_register_unsigned (frame, 10),
1460 
     (long) get_frame_register_unsigned (frame, 11),
1461 
     (long) get_frame_register_unsigned (frame, 12),
1462 
     (long) get_frame_register_unsigned (frame, 13),
1463 
     (long) get_frame_register_unsigned (frame, 14),
1464 
     (long) get_frame_register_unsigned (frame, 15));
1465 
}
1466 
 
1467 
static void
1468 
sh3_show_regs (struct frame_info *frame)
1469 
{
1470 
  printf_filtered
1471 
    ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1472 
     phex (get_frame_register_unsigned (frame,
1473 
                                        gdbarch_pc_regnum
1474 
                                          (get_frame_arch (frame))), 4),
1475 
     (long) get_frame_register_unsigned (frame, SR_REGNUM),
1476 
     (long) get_frame_register_unsigned (frame, PR_REGNUM),
1477 
     (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1478 
 
1479 
  printf_filtered
1480 
    ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1481 
     (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1482 
     (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1483 
     (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1484 
  printf_filtered
1485 
    ("     SSR %08lx      SPC %08lx\n",
1486 
     (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1487 
     (long) get_frame_register_unsigned (frame, SPC_REGNUM));
1488 
 
1489 
  printf_filtered
1490 
    ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1491 
     (long) get_frame_register_unsigned (frame, 0),
1492 
     (long) get_frame_register_unsigned (frame, 1),
1493 
     (long) get_frame_register_unsigned (frame, 2),
1494 
     (long) get_frame_register_unsigned (frame, 3),
1495 
     (long) get_frame_register_unsigned (frame, 4),
1496 
     (long) get_frame_register_unsigned (frame, 5),
1497 
     (long) get_frame_register_unsigned (frame, 6),
1498 
     (long) get_frame_register_unsigned (frame, 7));
1499 
  printf_filtered
1500 
    ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1501 
     (long) get_frame_register_unsigned (frame, 8),
1502 
     (long) get_frame_register_unsigned (frame, 9),
1503 
     (long) get_frame_register_unsigned (frame, 10),
1504 
     (long) get_frame_register_unsigned (frame, 11),
1505 
     (long) get_frame_register_unsigned (frame, 12),
1506 
     (long) get_frame_register_unsigned (frame, 13),
1507 
     (long) get_frame_register_unsigned (frame, 14),
1508 
     (long) get_frame_register_unsigned (frame, 15));
1509 
}
1510 
 
1511 
static void
1512 
sh2e_show_regs (struct frame_info *frame)
1513 
{
1514 
  struct gdbarch *gdbarch = get_frame_arch (frame);
1515 
  printf_filtered
1516 
    ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1517 
     phex (get_frame_register_unsigned (frame,
1518 
                                        gdbarch_pc_regnum (gdbarch)), 4),
1519 
     (long) get_frame_register_unsigned (frame, SR_REGNUM),
1520 
     (long) get_frame_register_unsigned (frame, PR_REGNUM),
1521 
     (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1522 
 
1523 
  printf_filtered
1524 
    ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1525 
     (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1526 
     (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1527 
     (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1528 
  printf_filtered
1529 
    ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1530 
     (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1531 
     (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1532 
     (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1533 
     (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1534 
 
1535 
  printf_filtered
1536 
    ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1537 
     (long) get_frame_register_unsigned (frame, 0),
1538 
     (long) get_frame_register_unsigned (frame, 1),
1539 
     (long) get_frame_register_unsigned (frame, 2),
1540 
     (long) get_frame_register_unsigned (frame, 3),
1541 
     (long) get_frame_register_unsigned (frame, 4),
1542 
     (long) get_frame_register_unsigned (frame, 5),
1543 
     (long) get_frame_register_unsigned (frame, 6),
1544 
     (long) get_frame_register_unsigned (frame, 7));
1545 
  printf_filtered
1546 
    ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1547 
     (long) get_frame_register_unsigned (frame, 8),
1548 
     (long) get_frame_register_unsigned (frame, 9),
1549 
     (long) get_frame_register_unsigned (frame, 10),
1550 
     (long) get_frame_register_unsigned (frame, 11),
1551 
     (long) get_frame_register_unsigned (frame, 12),
1552 
     (long) get_frame_register_unsigned (frame, 13),
1553 
     (long) get_frame_register_unsigned (frame, 14),
1554 
     (long) get_frame_register_unsigned (frame, 15));
1555 
 
1556 
  printf_filtered
1557 
    ("FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1558 
     (long) get_frame_register_unsigned
1559 
              (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1560 
     (long) get_frame_register_unsigned
1561 
              (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1562 
     (long) get_frame_register_unsigned
1563 
              (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1564 
     (long) get_frame_register_unsigned
1565 
              (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1566 
     (long) get_frame_register_unsigned
1567 
              (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1568 
     (long) get_frame_register_unsigned
1569 
              (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1570 
     (long) get_frame_register_unsigned
1571 
              (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1572 
     (long) get_frame_register_unsigned
1573 
              (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1574 
  printf_filtered
1575 
    ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1576 
     (long) get_frame_register_unsigned
1577 
              (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1578 
     (long) get_frame_register_unsigned
1579 
              (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1580 
     (long) get_frame_register_unsigned
1581 
              (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1582 
     (long) get_frame_register_unsigned
1583 
              (frame, gdbarch_fp0_regnum (gdbarch) + 11),
1584 
     (long) get_frame_register_unsigned
1585 
              (frame, gdbarch_fp0_regnum (gdbarch) + 12),
1586 
     (long) get_frame_register_unsigned
1587 
              (frame, gdbarch_fp0_regnum (gdbarch) + 13),
1588 
     (long) get_frame_register_unsigned
1589 
              (frame, gdbarch_fp0_regnum (gdbarch) + 14),
1590 
     (long) get_frame_register_unsigned
1591 
              (frame, gdbarch_fp0_regnum (gdbarch) + 15));
1592 
}
1593 
 
1594 
static void
1595 
sh2a_show_regs (struct frame_info *frame)
1596 
{
1597 
  struct gdbarch *gdbarch = get_frame_arch (frame);
1598 
  int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1599 
 
1600 
  printf_filtered
1601 
    ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1602 
     phex (get_frame_register_unsigned (frame,
1603 
                                        gdbarch_pc_regnum (gdbarch)), 4),
1604 
     (long) get_frame_register_unsigned (frame, SR_REGNUM),
1605 
     (long) get_frame_register_unsigned (frame, PR_REGNUM),
1606 
     (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1607 
 
1608 
  printf_filtered
1609 
    ("     GBR %08lx      VBR %08lx      TBR %08lx     MACL %08lx\n",
1610 
     (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1611 
     (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1612 
     (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1613 
     (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1614 
  printf_filtered
1615 
    ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1616 
     (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1617 
     (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1618 
     (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1619 
     (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1620 
 
1621 
  printf_filtered
1622 
    ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1623 
     (long) get_frame_register_unsigned (frame, 0),
1624 
     (long) get_frame_register_unsigned (frame, 1),
1625 
     (long) get_frame_register_unsigned (frame, 2),
1626 
     (long) get_frame_register_unsigned (frame, 3),
1627 
     (long) get_frame_register_unsigned (frame, 4),
1628 
     (long) get_frame_register_unsigned (frame, 5),
1629 
     (long) get_frame_register_unsigned (frame, 6),
1630 
     (long) get_frame_register_unsigned (frame, 7));
1631 
  printf_filtered
1632 
    ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1633 
     (long) get_frame_register_unsigned (frame, 8),
1634 
     (long) get_frame_register_unsigned (frame, 9),
1635 
     (long) get_frame_register_unsigned (frame, 10),
1636 
     (long) get_frame_register_unsigned (frame, 11),
1637 
     (long) get_frame_register_unsigned (frame, 12),
1638 
     (long) get_frame_register_unsigned (frame, 13),
1639 
     (long) get_frame_register_unsigned (frame, 14),
1640 
     (long) get_frame_register_unsigned (frame, 15));
1641 
 
1642 
  printf_filtered
1643 
    (pr ? "DR0-DR6  %08lx%08lx  %08lx%08lx  %08lx%08lx  %08lx%08lx\n"
1644 
        : "FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1645 
     (long) get_frame_register_unsigned
1646 
              (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1647 
     (long) get_frame_register_unsigned
1648 
              (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1649 
     (long) get_frame_register_unsigned
1650 
              (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1651 
     (long) get_frame_register_unsigned
1652 
              (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1653 
     (long) get_frame_register_unsigned
1654 
              (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1655 
     (long) get_frame_register_unsigned
1656 
              (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1657 
     (long) get_frame_register_unsigned
1658 
              (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1659 
     (long) get_frame_register_unsigned
1660 
              (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1661 
  printf_filtered
1662 
    (pr ? "DR8-DR14 %08lx%08lx  %08lx%08lx  %08lx%08lx  %08lx%08lx\n"
1663 
        : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1664 
     (long) get_frame_register_unsigned
1665 
              (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1666 
     (long) get_frame_register_unsigned
1667 
              (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1668 
     (long) get_frame_register_unsigned
1669 
              (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1670 
     (long) get_frame_register_unsigned
1671 
              (frame, gdbarch_fp0_regnum (gdbarch) + 11),
1672 
     (long) get_frame_register_unsigned
1673 
              (frame, gdbarch_fp0_regnum (gdbarch) + 12),
1674 
     (long) get_frame_register_unsigned
1675 
              (frame, gdbarch_fp0_regnum (gdbarch) + 13),
1676 
     (long) get_frame_register_unsigned
1677 
              (frame, gdbarch_fp0_regnum (gdbarch) + 14),
1678 
     (long) get_frame_register_unsigned
1679 
              (frame, gdbarch_fp0_regnum (gdbarch) + 15));
1680 
  printf_filtered
1681 
    ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1682 
  printf_filtered
1683 
    ("R0b-R7b  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1684 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1685 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1686 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1687 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1688 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1689 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1690 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1691 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1692 
  printf_filtered
1693 
    ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1694 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1695 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1696 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1697 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1698 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1699 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1700 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1701 
  printf_filtered
1702 
    ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1703 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1704 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1705 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1706 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1707 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
1708 
}
1709 
 
1710 
static void
1711 
sh2a_nofpu_show_regs (struct frame_info *frame)
1712 
{
1713 
  int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1714 
 
1715 
  printf_filtered
1716 
    ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1717 
     phex (get_frame_register_unsigned (frame,
1718 
                                        gdbarch_pc_regnum
1719 
                                          (get_frame_arch (frame))), 4),
1720 
     (long) get_frame_register_unsigned (frame, SR_REGNUM),
1721 
     (long) get_frame_register_unsigned (frame, PR_REGNUM),
1722 
     (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1723 
 
1724 
  printf_filtered
1725 
    ("     GBR %08lx      VBR %08lx      TBR %08lx     MACL %08lx\n",
1726 
     (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1727 
     (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1728 
     (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1729 
     (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1730 
  printf_filtered
1731 
    ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1732 
     (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1733 
     (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1734 
     (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1735 
     (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1736 
 
1737 
  printf_filtered
1738 
    ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1739 
     (long) get_frame_register_unsigned (frame, 0),
1740 
     (long) get_frame_register_unsigned (frame, 1),
1741 
     (long) get_frame_register_unsigned (frame, 2),
1742 
     (long) get_frame_register_unsigned (frame, 3),
1743 
     (long) get_frame_register_unsigned (frame, 4),
1744 
     (long) get_frame_register_unsigned (frame, 5),
1745 
     (long) get_frame_register_unsigned (frame, 6),
1746 
     (long) get_frame_register_unsigned (frame, 7));
1747 
  printf_filtered
1748 
    ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1749 
     (long) get_frame_register_unsigned (frame, 8),
1750 
     (long) get_frame_register_unsigned (frame, 9),
1751 
     (long) get_frame_register_unsigned (frame, 10),
1752 
     (long) get_frame_register_unsigned (frame, 11),
1753 
     (long) get_frame_register_unsigned (frame, 12),
1754 
     (long) get_frame_register_unsigned (frame, 13),
1755 
     (long) get_frame_register_unsigned (frame, 14),
1756 
     (long) get_frame_register_unsigned (frame, 15));
1757 
 
1758 
  printf_filtered
1759 
    ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1760 
  printf_filtered
1761 
    ("R0b-R7b  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1762 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1763 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1764 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1765 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1766 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1767 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1768 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1769 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1770 
  printf_filtered
1771 
    ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1772 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1773 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1774 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1775 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1776 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1777 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1778 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1779 
  printf_filtered
1780 
    ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1781 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1782 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1783 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1784 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1785 
     (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
1786 
}
1787 
 
1788 
static void
1789 
sh3e_show_regs (struct frame_info *frame)
1790 
{
1791 
  struct gdbarch *gdbarch = get_frame_arch (frame);
1792 
  printf_filtered
1793 
    ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1794 
     phex (get_frame_register_unsigned (frame,
1795 
                                        gdbarch_pc_regnum (gdbarch)), 4),
1796 
     (long) get_frame_register_unsigned (frame, SR_REGNUM),
1797 
     (long) get_frame_register_unsigned (frame, PR_REGNUM),
1798 
     (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1799 
 
1800 
  printf_filtered
1801 
    ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1802 
     (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1803 
     (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1804 
     (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1805 
  printf_filtered
1806 
    ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1807 
     (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1808 
     (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1809 
     (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1810 
     (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1811 
 
1812 
  printf_filtered
1813 
    ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1814 
     (long) get_frame_register_unsigned (frame, 0),
1815 
     (long) get_frame_register_unsigned (frame, 1),
1816 
     (long) get_frame_register_unsigned (frame, 2),
1817 
     (long) get_frame_register_unsigned (frame, 3),
1818 
     (long) get_frame_register_unsigned (frame, 4),
1819 
     (long) get_frame_register_unsigned (frame, 5),
1820 
     (long) get_frame_register_unsigned (frame, 6),
1821 
     (long) get_frame_register_unsigned (frame, 7));
1822 
  printf_filtered
1823 
    ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1824 
     (long) get_frame_register_unsigned (frame, 8),
1825 
     (long) get_frame_register_unsigned (frame, 9),
1826 
     (long) get_frame_register_unsigned (frame, 10),
1827 
     (long) get_frame_register_unsigned (frame, 11),
1828 
     (long) get_frame_register_unsigned (frame, 12),
1829 
     (long) get_frame_register_unsigned (frame, 13),
1830 
     (long) get_frame_register_unsigned (frame, 14),
1831 
     (long) get_frame_register_unsigned (frame, 15));
1832 
 
1833 
  printf_filtered
1834 
    ("FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1835 
     (long) get_frame_register_unsigned
1836 
              (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1837 
     (long) get_frame_register_unsigned
1838 
              (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1839 
     (long) get_frame_register_unsigned
1840 
              (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1841 
     (long) get_frame_register_unsigned
1842 
              (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1843 
     (long) get_frame_register_unsigned
1844 
              (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1845 
     (long) get_frame_register_unsigned
1846 
              (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1847 
     (long) get_frame_register_unsigned
1848 
              (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1849 
     (long) get_frame_register_unsigned
1850 
              (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1851 
  printf_filtered
1852 
    ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1853 
     (long) get_frame_register_unsigned
1854 
              (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1855 
     (long) get_frame_register_unsigned
1856 
              (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1857 
     (long) get_frame_register_unsigned
1858 
              (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1859 
     (long) get_frame_register_unsigned
1860 
              (frame, gdbarch_fp0_regnum (gdbarch) + 11),
1861 
     (long) get_frame_register_unsigned
1862 
              (frame, gdbarch_fp0_regnum (gdbarch) + 12),
1863 
     (long) get_frame_register_unsigned
1864 
              (frame, gdbarch_fp0_regnum (gdbarch) + 13),
1865 
     (long) get_frame_register_unsigned
1866 
              (frame, gdbarch_fp0_regnum (gdbarch) + 14),
1867 
     (long) get_frame_register_unsigned
1868 
              (frame, gdbarch_fp0_regnum (gdbarch) + 15));
1869 
}
1870 
 
1871 
static void
1872 
sh3_dsp_show_regs (struct frame_info *frame)
1873 
{
1874 
  printf_filtered
1875 
    ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1876 
     phex (get_frame_register_unsigned (frame,
1877 
                                        gdbarch_pc_regnum
1878 
                                          (get_frame_arch (frame))), 4),
1879 
     (long) get_frame_register_unsigned (frame, SR_REGNUM),
1880 
     (long) get_frame_register_unsigned (frame, PR_REGNUM),
1881 
     (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1882 
 
1883 
  printf_filtered
1884 
    ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1885 
     (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1886 
     (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1887 
     (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1888 
 
1889 
  printf_filtered
1890 
    ("     SSR %08lx      SPC %08lx      DSR %08lx\n",
1891 
     (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1892 
     (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1893 
     (long) get_frame_register_unsigned (frame, DSR_REGNUM));
1894 
 
1895 
  printf_filtered
1896 
    ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1897 
     (long) get_frame_register_unsigned (frame, 0),
1898 
     (long) get_frame_register_unsigned (frame, 1),
1899 
     (long) get_frame_register_unsigned (frame, 2),
1900 
     (long) get_frame_register_unsigned (frame, 3),
1901 
     (long) get_frame_register_unsigned (frame, 4),
1902 
     (long) get_frame_register_unsigned (frame, 5),
1903 
     (long) get_frame_register_unsigned (frame, 6),
1904 
     (long) get_frame_register_unsigned (frame, 7));
1905 
  printf_filtered
1906 
    ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1907 
     (long) get_frame_register_unsigned (frame, 8),
1908 
     (long) get_frame_register_unsigned (frame, 9),
1909 
     (long) get_frame_register_unsigned (frame, 10),
1910 
     (long) get_frame_register_unsigned (frame, 11),
1911 
     (long) get_frame_register_unsigned (frame, 12),
1912 
     (long) get_frame_register_unsigned (frame, 13),
1913 
     (long) get_frame_register_unsigned (frame, 14),
1914 
     (long) get_frame_register_unsigned (frame, 15));
1915 
 
1916 
  printf_filtered
1917 
    ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1918 
     (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
1919 
     (long) get_frame_register_unsigned (frame, A0_REGNUM),
1920 
     (long) get_frame_register_unsigned (frame, M0_REGNUM),
1921 
     (long) get_frame_register_unsigned (frame, X0_REGNUM),
1922 
     (long) get_frame_register_unsigned (frame, Y0_REGNUM),
1923 
     (long) get_frame_register_unsigned (frame, RS_REGNUM),
1924 
     (long) get_frame_register_unsigned (frame, MOD_REGNUM));
1925 
  printf_filtered
1926 
    ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1927 
     (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
1928 
     (long) get_frame_register_unsigned (frame, A1_REGNUM),
1929 
     (long) get_frame_register_unsigned (frame, M1_REGNUM),
1930 
     (long) get_frame_register_unsigned (frame, X1_REGNUM),
1931 
     (long) get_frame_register_unsigned (frame, Y1_REGNUM),
1932 
     (long) get_frame_register_unsigned (frame, RE_REGNUM));
1933 
}
1934 
 
1935 
static void
1936 
sh4_show_regs (struct frame_info *frame)
1937 
{
1938 
  struct gdbarch *gdbarch = get_frame_arch (frame);
1939 
  int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1940 
 
1941 
  printf_filtered
1942 
    ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1943 
     phex (get_frame_register_unsigned (frame,
1944 
                                        gdbarch_pc_regnum (gdbarch)), 4),
1945 
     (long) get_frame_register_unsigned (frame, SR_REGNUM),
1946 
     (long) get_frame_register_unsigned (frame, PR_REGNUM),
1947 
     (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1948 
 
1949 
  printf_filtered
1950 
    ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1951 
     (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1952 
     (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1953 
     (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1954 
  printf_filtered
1955 
    ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1956 
     (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1957 
     (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1958 
     (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1959 
     (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1960 
 
1961 
  printf_filtered
1962 
    ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1963 
     (long) get_frame_register_unsigned (frame, 0),
1964 
     (long) get_frame_register_unsigned (frame, 1),
1965 
     (long) get_frame_register_unsigned (frame, 2),
1966 
     (long) get_frame_register_unsigned (frame, 3),
1967 
     (long) get_frame_register_unsigned (frame, 4),
1968 
     (long) get_frame_register_unsigned (frame, 5),
1969 
     (long) get_frame_register_unsigned (frame, 6),
1970 
     (long) get_frame_register_unsigned (frame, 7));
1971 
  printf_filtered
1972 
    ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1973 
     (long) get_frame_register_unsigned (frame, 8),
1974 
     (long) get_frame_register_unsigned (frame, 9),
1975 
     (long) get_frame_register_unsigned (frame, 10),
1976 
     (long) get_frame_register_unsigned (frame, 11),
1977 
     (long) get_frame_register_unsigned (frame, 12),
1978 
     (long) get_frame_register_unsigned (frame, 13),
1979 
     (long) get_frame_register_unsigned (frame, 14),
1980 
     (long) get_frame_register_unsigned (frame, 15));
1981 
 
1982 
  printf_filtered
1983 
    (pr ? "DR0-DR6  %08lx%08lx  %08lx%08lx  %08lx%08lx  %08lx%08lx\n"
1984 
        : "FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1985 
     (long) get_frame_register_unsigned
1986 
              (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1987 
     (long) get_frame_register_unsigned
1988 
              (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1989 
     (long) get_frame_register_unsigned
1990 
              (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1991 
     (long) get_frame_register_unsigned
1992 
              (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1993 
     (long) get_frame_register_unsigned
1994 
              (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1995 
     (long) get_frame_register_unsigned
1996 
              (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1997 
     (long) get_frame_register_unsigned
1998 
              (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1999 
     (long) get_frame_register_unsigned
2000 
              (frame, gdbarch_fp0_regnum (gdbarch) + 7));
2001 
  printf_filtered
2002 
    (pr ? "DR8-DR14 %08lx%08lx  %08lx%08lx  %08lx%08lx  %08lx%08lx\n"
2003 
        : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2004 
     (long) get_frame_register_unsigned
2005 
              (frame, gdbarch_fp0_regnum (gdbarch) + 8),
2006 
     (long) get_frame_register_unsigned
2007 
              (frame, gdbarch_fp0_regnum (gdbarch) + 9),
2008 
     (long) get_frame_register_unsigned
2009 
              (frame, gdbarch_fp0_regnum (gdbarch) + 10),
2010 
     (long) get_frame_register_unsigned
2011 
              (frame, gdbarch_fp0_regnum (gdbarch) + 11),
2012 
     (long) get_frame_register_unsigned
2013 
              (frame, gdbarch_fp0_regnum (gdbarch) + 12),
2014 
     (long) get_frame_register_unsigned
2015 
              (frame, gdbarch_fp0_regnum (gdbarch) + 13),
2016 
     (long) get_frame_register_unsigned
2017 
              (frame, gdbarch_fp0_regnum (gdbarch) + 14),
2018 
     (long) get_frame_register_unsigned
2019 
              (frame, gdbarch_fp0_regnum (gdbarch) + 15));
2020 
}
2021 
 
2022 
static void
2023 
sh4_nofpu_show_regs (struct frame_info *frame)
2024 
{
2025 
  printf_filtered
2026 
    ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
2027 
     phex (get_frame_register_unsigned (frame,
2028 
                                        gdbarch_pc_regnum
2029 
                                          (get_frame_arch (frame))), 4),
2030 
     (long) get_frame_register_unsigned (frame, SR_REGNUM),
2031 
     (long) get_frame_register_unsigned (frame, PR_REGNUM),
2032 
     (long) get_frame_register_unsigned (frame, MACH_REGNUM));
2033 
 
2034 
  printf_filtered
2035 
    ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
2036 
     (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2037 
     (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2038 
     (long) get_frame_register_unsigned (frame, MACL_REGNUM));
2039 
  printf_filtered
2040 
    ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
2041 
     (long) get_frame_register_unsigned (frame, SSR_REGNUM),
2042 
     (long) get_frame_register_unsigned (frame, SPC_REGNUM),
2043 
     (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
2044 
     (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
2045 
 
2046 
  printf_filtered
2047 
    ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2048 
     (long) get_frame_register_unsigned (frame, 0),
2049 
     (long) get_frame_register_unsigned (frame, 1),
2050 
     (long) get_frame_register_unsigned (frame, 2),
2051 
     (long) get_frame_register_unsigned (frame, 3),
2052 
     (long) get_frame_register_unsigned (frame, 4),
2053 
     (long) get_frame_register_unsigned (frame, 5),
2054 
     (long) get_frame_register_unsigned (frame, 6),
2055 
     (long) get_frame_register_unsigned (frame, 7));
2056 
  printf_filtered
2057 
    ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2058 
     (long) get_frame_register_unsigned (frame, 8),
2059 
     (long) get_frame_register_unsigned (frame, 9),
2060 
     (long) get_frame_register_unsigned (frame, 10),
2061 
     (long) get_frame_register_unsigned (frame, 11),
2062 
     (long) get_frame_register_unsigned (frame, 12),
2063 
     (long) get_frame_register_unsigned (frame, 13),
2064 
     (long) get_frame_register_unsigned (frame, 14),
2065 
     (long) get_frame_register_unsigned (frame, 15));
2066 
}
2067 
 
2068 
static void
2069 
sh_dsp_show_regs (struct frame_info *frame)
2070 
{
2071 
  printf_filtered
2072 
    ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
2073 
     phex (get_frame_register_unsigned (frame,
2074 
                                        gdbarch_pc_regnum
2075 
                                          (get_frame_arch (frame))), 4),
2076 
     (long) get_frame_register_unsigned (frame, SR_REGNUM),
2077 
     (long) get_frame_register_unsigned (frame, PR_REGNUM),
2078 
     (long) get_frame_register_unsigned (frame, MACH_REGNUM));
2079 
 
2080 
  printf_filtered
2081 
    ("     GBR %08lx      VBR %08lx      DSR %08lx     MACL %08lx\n",
2082 
     (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2083 
     (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2084 
     (long) get_frame_register_unsigned (frame, DSR_REGNUM),
2085 
     (long) get_frame_register_unsigned (frame, MACL_REGNUM));
2086 
 
2087 
  printf_filtered
2088 
    ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2089 
     (long) get_frame_register_unsigned (frame, 0),
2090 
     (long) get_frame_register_unsigned (frame, 1),
2091 
     (long) get_frame_register_unsigned (frame, 2),
2092 
     (long) get_frame_register_unsigned (frame, 3),
2093 
     (long) get_frame_register_unsigned (frame, 4),
2094 
     (long) get_frame_register_unsigned (frame, 5),
2095 
     (long) get_frame_register_unsigned (frame, 6),
2096 
     (long) get_frame_register_unsigned (frame, 7));
2097 
  printf_filtered
2098 
    ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2099 
     (long) get_frame_register_unsigned (frame, 8),
2100 
     (long) get_frame_register_unsigned (frame, 9),
2101 
     (long) get_frame_register_unsigned (frame, 10),
2102 
     (long) get_frame_register_unsigned (frame, 11),
2103 
     (long) get_frame_register_unsigned (frame, 12),
2104 
     (long) get_frame_register_unsigned (frame, 13),
2105 
     (long) get_frame_register_unsigned (frame, 14),
2106 
     (long) get_frame_register_unsigned (frame, 15));
2107 
 
2108 
  printf_filtered
2109 
    ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2110 
     (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
2111 
     (long) get_frame_register_unsigned (frame, A0_REGNUM),
2112 
     (long) get_frame_register_unsigned (frame, M0_REGNUM),
2113 
     (long) get_frame_register_unsigned (frame, X0_REGNUM),
2114 
     (long) get_frame_register_unsigned (frame, Y0_REGNUM),
2115 
     (long) get_frame_register_unsigned (frame, RS_REGNUM),
2116 
     (long) get_frame_register_unsigned (frame, MOD_REGNUM));
2117 
  printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2118 
     (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
2119 
     (long) get_frame_register_unsigned (frame, A1_REGNUM),
2120 
     (long) get_frame_register_unsigned (frame, M1_REGNUM),
2121 
     (long) get_frame_register_unsigned (frame, X1_REGNUM),
2122 
     (long) get_frame_register_unsigned (frame, Y1_REGNUM),
2123 
     (long) get_frame_register_unsigned (frame, RE_REGNUM));
2124 
}
2125 
 
2126 
static void
2127 
sh_show_regs_command (char *args, int from_tty)
2128 
{
2129 
  if (sh_show_regs)
2130 
    (*sh_show_regs) (get_current_frame ());
2131 
}
2132 
 
2133 
static struct type *
2134 
sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
2135 
{
2136 
  if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
2137 
       && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2138 
    return builtin_type (gdbarch)->builtin_float;
2139 
  else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2140 
    return builtin_type (gdbarch)->builtin_double;
2141 
  else
2142 
    return builtin_type (gdbarch)->builtin_int;
2143 
}
2144 
 
2145 
/* Return the GDB type object for the "standard" data type
2146 
   of data in register N.  */
2147 
static struct type *
2148 
sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
2149 
{
2150 
  if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
2151 
       && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2152 
    return builtin_type (gdbarch)->builtin_float;
2153 
  else
2154 
    return builtin_type (gdbarch)->builtin_int;
2155 
}
2156 
 
2157 
static struct type *
2158 
sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high)
2159 
{
2160 
  return lookup_array_range_type (builtin_type (gdbarch)->builtin_float,
2161 
                                  0, high);
2162 
}
2163 
 
2164 
static struct type *
2165 
sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
2166 
{
2167 
  if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
2168 
       && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2169 
    return builtin_type (gdbarch)->builtin_float;
2170 
  else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2171 
    return builtin_type (gdbarch)->builtin_double;
2172 
  else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2173 
    return sh_sh4_build_float_register_type (gdbarch, 3);
2174 
  else
2175 
    return builtin_type (gdbarch)->builtin_int;
2176 
}
2177 
 
2178 
static struct type *
2179 
sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
2180 
{
2181 
  return builtin_type (gdbarch)->builtin_int;
2182 
}
2183 
 
2184 
/* Is a register in a reggroup?
2185 
   The default code in reggroup.c doesn't identify system registers, some
2186 
   float registers or any of the vector registers.
2187 
   TODO: sh2a and dsp registers.  */
2188 
static int
2189 
sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2190 
                        struct reggroup *reggroup)
2191 
{
2192 
  if (gdbarch_register_name (gdbarch, regnum) == NULL
2193 
      || *gdbarch_register_name (gdbarch, regnum) == '\0')
2194 
    return 0;
2195 
 
2196 
  if (reggroup == float_reggroup
2197 
      && (regnum == FPUL_REGNUM
2198 
          || regnum == FPSCR_REGNUM))
2199 
    return 1;
2200 
 
2201 
  if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
2202 
    {
2203 
      if (reggroup == vector_reggroup || reggroup == float_reggroup)
2204 
        return 1;
2205 
      if (reggroup == general_reggroup)
2206 
        return 0;
2207 
    }
2208 
 
2209 
  if (regnum == VBR_REGNUM
2210 
      || regnum == SR_REGNUM
2211 
      || regnum == FPSCR_REGNUM
2212 
      || regnum == SSR_REGNUM
2213 
      || regnum == SPC_REGNUM)
2214 
    {
2215 
      if (reggroup == system_reggroup)
2216 
        return 1;
2217 
      if (reggroup == general_reggroup)
2218 
        return 0;
2219 
    }
2220 
 
2221 
  /* The default code can cope with any other registers.  */
2222 
  return default_register_reggroup_p (gdbarch, regnum, reggroup);
2223 
}
2224 
 
2225 
/* On the sh4, the DRi pseudo registers are problematic if the target
2226 
   is little endian. When the user writes one of those registers, for
2227 
   instance with 'ser var $dr0=1', we want the double to be stored
2228 
   like this:
2229 
   fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2230 
   fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2231 
 
2232 
   This corresponds to little endian byte order & big endian word
2233 
   order.  However if we let gdb write the register w/o conversion, it
2234 
   will write fr0 and fr1 this way:
2235 
   fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2236 
   fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2237 
   because it will consider fr0 and fr1 as a single LE stretch of memory.
2238 
 
2239 
   To achieve what we want we must force gdb to store things in
2240 
   floatformat_ieee_double_littlebyte_bigword (which is defined in
2241 
   include/floatformat.h and libiberty/floatformat.c.
2242 
 
2243 
   In case the target is big endian, there is no problem, the
2244 
   raw bytes will look like:
2245 
   fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2246 
   fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2247 
 
2248 
   The other pseudo registers (the FVs) also don't pose a problem
2249 
   because they are stored as 4 individual FP elements. */
2250 
 
2251 
static void
2252 
sh_register_convert_to_virtual (int regnum, struct type *type,
2253 
                                char *from, char *to)
2254 
{
2255 
  if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
2256 
    {
2257 
      DOUBLEST val;
2258 
      floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2259 
                               from, &val);
2260 
      store_typed_floating (to, type, val);
2261 
    }
2262 
  else
2263 
    error
2264 
      ("sh_register_convert_to_virtual called with non DR register number");
2265 
}
2266 
 
2267 
static void
2268 
sh_register_convert_to_raw (struct type *type, int regnum,
2269 
                            const void *from, void *to)
2270 
{
2271 
  if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
2272 
    {
2273 
      DOUBLEST val = extract_typed_floating (from, type);
2274 
      floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2275 
                                 &val, to);
2276 
    }
2277 
  else
2278 
    error (_("sh_register_convert_to_raw called with non DR register number"));
2279 
}
2280 
 
2281 
/* For vectors of 4 floating point registers. */
2282 
static int
2283 
fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
2284 
{
2285 
  int fp_regnum;
2286 
 
2287 
  fp_regnum = gdbarch_fp0_regnum (gdbarch)
2288 
              + (fv_regnum - FV0_REGNUM) * 4;
2289 
  return fp_regnum;
2290 
}
2291 
 
2292 
/* For double precision floating point registers, i.e 2 fp regs.*/
2293 
static int
2294 
dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
2295 
{
2296 
  int fp_regnum;
2297 
 
2298 
  fp_regnum = gdbarch_fp0_regnum (gdbarch)
2299 
              + (dr_regnum - DR0_REGNUM) * 2;
2300 
  return fp_regnum;
2301 
}
2302 
 
2303 
static void
2304 
sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2305 
                         int reg_nr, gdb_byte *buffer)
2306 
{
2307 
  int base_regnum, portion;
2308 
  char temp_buffer[MAX_REGISTER_SIZE];
2309 
 
2310 
  if (reg_nr == PSEUDO_BANK_REGNUM)
2311 
    regcache_raw_read (regcache, BANK_REGNUM, buffer);
2312 
  else
2313 
  if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2314 
    {
2315 
      base_regnum = dr_reg_base_num (gdbarch, reg_nr);
2316 
 
2317 
      /* Build the value in the provided buffer. */
2318 
      /* Read the real regs for which this one is an alias.  */
2319 
      for (portion = 0; portion < 2; portion++)
2320 
        regcache_raw_read (regcache, base_regnum + portion,
2321 
                           (temp_buffer
2322 
                            + register_size (gdbarch,
2323 
                                             base_regnum) * portion));
2324 
      /* We must pay attention to the endiannes. */
2325 
      sh_register_convert_to_virtual (reg_nr,
2326 
                                      register_type (gdbarch, reg_nr),
2327 
                                      temp_buffer, buffer);
2328 
    }
2329 
  else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2330 
    {
2331 
      base_regnum = fv_reg_base_num (gdbarch, reg_nr);
2332 
 
2333 
      /* Read the real regs for which this one is an alias.  */
2334 
      for (portion = 0; portion < 4; portion++)
2335 
        regcache_raw_read (regcache, base_regnum + portion,
2336 
                           ((char *) buffer
2337 
                            + register_size (gdbarch,
2338 
                                             base_regnum) * portion));
2339 
    }
2340 
}
2341 
 
2342 
static void
2343 
sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2344 
                          int reg_nr, const gdb_byte *buffer)
2345 
{
2346 
  int base_regnum, portion;
2347 
  char temp_buffer[MAX_REGISTER_SIZE];
2348 
 
2349 
  if (reg_nr == PSEUDO_BANK_REGNUM)
2350 
    {
2351 
      /* When the bank register is written to, the whole register bank
2352 
         is switched and all values in the bank registers must be read
2353 
         from the target/sim again. We're just invalidating the regcache
2354 
         so that a re-read happens next time it's necessary.  */
2355 
      int bregnum;
2356 
 
2357 
      regcache_raw_write (regcache, BANK_REGNUM, buffer);
2358 
      for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
2359 
        regcache_invalidate (regcache, bregnum);
2360 
    }
2361 
  else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2362 
    {
2363 
      base_regnum = dr_reg_base_num (gdbarch, reg_nr);
2364 
 
2365 
      /* We must pay attention to the endiannes. */
2366 
      sh_register_convert_to_raw (register_type (gdbarch, reg_nr),
2367 
                                  reg_nr, buffer, temp_buffer);
2368 
 
2369 
      /* Write the real regs for which this one is an alias.  */
2370 
      for (portion = 0; portion < 2; portion++)
2371 
        regcache_raw_write (regcache, base_regnum + portion,
2372 
                            (temp_buffer
2373 
                             + register_size (gdbarch,
2374 
                                              base_regnum) * portion));
2375 
    }
2376 
  else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2377 
    {
2378 
      base_regnum = fv_reg_base_num (gdbarch, reg_nr);
2379 
 
2380 
      /* Write the real regs for which this one is an alias.  */
2381 
      for (portion = 0; portion < 4; portion++)
2382 
        regcache_raw_write (regcache, base_regnum + portion,
2383 
                            ((char *) buffer
2384 
                             + register_size (gdbarch,
2385 
                                              base_regnum) * portion));
2386 
    }
2387 
}
2388 
 
2389 
static int
2390 
sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr)
2391 
{
2392 
  if (legacy_register_sim_regno (gdbarch, nr) < 0)
2393 
    return legacy_register_sim_regno (gdbarch, nr);
2394 
  if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
2395 
    return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
2396 
  if (nr == MOD_REGNUM)
2397 
    return SIM_SH_MOD_REGNUM;
2398 
  if (nr == RS_REGNUM)
2399 
    return SIM_SH_RS_REGNUM;
2400 
  if (nr == RE_REGNUM)
2401 
    return SIM_SH_RE_REGNUM;
2402 
  if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2403 
    return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2404 
  return nr;
2405 
}
2406 
 
2407 
static int
2408 
sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr)
2409 
{
2410 
  switch (nr)
2411 
    {
2412 
      case TBR_REGNUM:
2413 
        return SIM_SH_TBR_REGNUM;
2414 
      case IBNR_REGNUM:
2415 
        return SIM_SH_IBNR_REGNUM;
2416 
      case IBCR_REGNUM:
2417 
        return SIM_SH_IBCR_REGNUM;
2418 
      case BANK_REGNUM:
2419 
        return SIM_SH_BANK_REGNUM;
2420 
      case MACLB_REGNUM:
2421 
        return SIM_SH_BANK_MACL_REGNUM;
2422 
      case GBRB_REGNUM:
2423 
        return SIM_SH_BANK_GBR_REGNUM;
2424 
      case PRB_REGNUM:
2425 
        return SIM_SH_BANK_PR_REGNUM;
2426 
      case IVNB_REGNUM:
2427 
        return SIM_SH_BANK_IVN_REGNUM;
2428 
      case MACHB_REGNUM:
2429 
        return SIM_SH_BANK_MACH_REGNUM;
2430 
      default:
2431 
        break;
2432 
    }
2433 
  return legacy_register_sim_regno (gdbarch, nr);
2434 
}
2435 
 
2436 
/* Set up the register unwinding such that call-clobbered registers are
2437 
   not displayed in frames >0 because the true value is not certain.
2438 
   The 'undefined' registers will show up as 'not available' unless the
2439 
   CFI says otherwise.
2440 
 
2441 
   This function is currently set up for SH4 and compatible only.  */
2442 
 
2443 
static void
2444 
sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
2445 
                          struct dwarf2_frame_state_reg *reg,
2446 
                          struct frame_info *this_frame)
2447 
{
2448 
  /* Mark the PC as the destination for the return address.  */
2449 
  if (regnum == gdbarch_pc_regnum (gdbarch))
2450 
    reg->how = DWARF2_FRAME_REG_RA;
2451 
 
2452 
  /* Mark the stack pointer as the call frame address.  */
2453 
  else if (regnum == gdbarch_sp_regnum (gdbarch))
2454 
    reg->how = DWARF2_FRAME_REG_CFA;
2455 
 
2456 
  /* The above was taken from the default init_reg in dwarf2-frame.c
2457 
     while the below is SH specific.  */
2458 
 
2459 
  /* Caller save registers.  */
2460 
  else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7)
2461 
           || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11)
2462 
           || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5)
2463 
           || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2)
2464 
           || (regnum == MACH_REGNUM)
2465 
           || (regnum == MACL_REGNUM)
2466 
           || (regnum == FPUL_REGNUM)
2467 
           || (regnum == SR_REGNUM))
2468 
    reg->how = DWARF2_FRAME_REG_UNDEFINED;
2469 
 
2470 
  /* Callee save registers.  */
2471 
  else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15)
2472 
           || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15)
2473 
           || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8)
2474 
           || (regnum == FV0_REGNUM+3))
2475 
    reg->how = DWARF2_FRAME_REG_SAME_VALUE;
2476 
 
2477 
  /* Other registers.  These are not in the ABI and may or may not
2478 
     mean anything in frames >0 so don't show them.  */
2479 
  else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15)
2480 
           || (regnum == GBR_REGNUM)
2481 
           || (regnum == VBR_REGNUM)
2482 
           || (regnum == FPSCR_REGNUM)
2483 
           || (regnum == SSR_REGNUM)
2484 
           || (regnum == SPC_REGNUM))
2485 
    reg->how = DWARF2_FRAME_REG_UNDEFINED;
2486 
}
2487 
 
2488 
static struct sh_frame_cache *
2489 
sh_alloc_frame_cache (void)
2490 
{
2491 
  struct sh_frame_cache *cache;
2492 
  int i;
2493 
 
2494 
  cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2495 
 
2496 
  /* Base address.  */
2497 
  cache->base = 0;
2498 
  cache->saved_sp = 0;
2499 
  cache->sp_offset = 0;
2500 
  cache->pc = 0;
2501 
 
2502 
  /* Frameless until proven otherwise.  */
2503 
  cache->uses_fp = 0;
2504 
 
2505 
  /* Saved registers.  We initialize these to -1 since zero is a valid
2506 
     offset (that's where fp is supposed to be stored).  */
2507 
  for (i = 0; i < SH_NUM_REGS; i++)
2508 
    {
2509 
      cache->saved_regs[i] = -1;
2510 
    }
2511 
 
2512 
  return cache;
2513 
}
2514 
 
2515 
static struct sh_frame_cache *
2516 
sh_frame_cache (struct frame_info *this_frame, void **this_cache)
2517 
{
2518 
  struct gdbarch *gdbarch = get_frame_arch (this_frame);
2519 
  struct sh_frame_cache *cache;
2520 
  CORE_ADDR current_pc;
2521 
  int i;
2522 
 
2523 
  if (*this_cache)
2524 
    return *this_cache;
2525 
 
2526 
  cache = sh_alloc_frame_cache ();
2527 
  *this_cache = cache;
2528 
 
2529 
  /* In principle, for normal frames, fp holds the frame pointer,
2530 
     which holds the base address for the current stack frame.
2531 
     However, for functions that don't need it, the frame pointer is
2532 
     optional.  For these "frameless" functions the frame pointer is
2533 
     actually the frame pointer of the calling frame. */
2534 
  cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM);
2535 
  if (cache->base == 0)
2536 
    return cache;
2537 
 
2538 
  cache->pc = get_frame_func (this_frame);
2539 
  current_pc = get_frame_pc (this_frame);
2540 
  if (cache->pc != 0)
2541 
    {
2542 
      ULONGEST fpscr;
2543 
      fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM);
2544 
      sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr);
2545 
    }
2546 
 
2547 
  if (!cache->uses_fp)
2548 
    {
2549 
      /* We didn't find a valid frame, which means that CACHE->base
2550 
         currently holds the frame pointer for our calling frame.  If
2551 
         we're at the start of a function, or somewhere half-way its
2552 
         prologue, the function's frame probably hasn't been fully
2553 
         setup yet.  Try to reconstruct the base address for the stack
2554 
         frame by looking at the stack pointer.  For truly "frameless"
2555 
         functions this might work too.  */
2556 
      cache->base = get_frame_register_unsigned
2557 
                     (this_frame, gdbarch_sp_regnum (gdbarch));
2558 
    }
2559 
 
2560 
  /* Now that we have the base address for the stack frame we can
2561 
     calculate the value of sp in the calling frame.  */
2562 
  cache->saved_sp = cache->base + cache->sp_offset;
2563 
 
2564 
  /* Adjust all the saved registers such that they contain addresses
2565 
     instead of offsets.  */
2566 
  for (i = 0; i < SH_NUM_REGS; i++)
2567 
    if (cache->saved_regs[i] != -1)
2568 
      cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2569 
 
2570 
  return cache;
2571 
}
2572 
 
2573 
static struct value *
2574 
sh_frame_prev_register (struct frame_info *this_frame,
2575 
                        void **this_cache, int regnum)
2576 
{
2577 
  struct gdbarch *gdbarch = get_frame_arch (this_frame);
2578 
  struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
2579 
 
2580 
  gdb_assert (regnum >= 0);
2581 
 
2582 
  if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2583 
    return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2584 
 
2585 
  /* The PC of the previous frame is stored in the PR register of
2586 
     the current frame.  Frob regnum so that we pull the value from
2587 
     the correct place.  */
2588 
  if (regnum == gdbarch_pc_regnum (gdbarch))
2589 
    regnum = PR_REGNUM;
2590 
 
2591 
  if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
2592 
    return frame_unwind_got_memory (this_frame, regnum,
2593 
                                    cache->saved_regs[regnum]);
2594 
 
2595 
  return frame_unwind_got_register (this_frame, regnum, regnum);
2596 
}
2597 
 
2598 
static void
2599 
sh_frame_this_id (struct frame_info *this_frame, void **this_cache,
2600 
                  struct frame_id *this_id)
2601 
{
2602 
  struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
2603 
 
2604 
  /* This marks the outermost frame.  */
2605 
  if (cache->base == 0)
2606 
    return;
2607 
 
2608 
  *this_id = frame_id_build (cache->saved_sp, cache->pc);
2609 
}
2610 
 
2611 
static const struct frame_unwind sh_frame_unwind = {
2612 
  NORMAL_FRAME,
2613 
  sh_frame_this_id,
2614 
  sh_frame_prev_register,
2615 
  NULL,
2616 
  default_frame_sniffer
2617 
};
2618 
 
2619 
static CORE_ADDR
2620 
sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2621 
{
2622 
  return frame_unwind_register_unsigned (next_frame,
2623 
                                         gdbarch_sp_regnum (gdbarch));
2624 
}
2625 
 
2626 
static CORE_ADDR
2627 
sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2628 
{
2629 
  return frame_unwind_register_unsigned (next_frame,
2630 
                                         gdbarch_pc_regnum (gdbarch));
2631 
}
2632 
 
2633 
static struct frame_id
2634 
sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2635 
{
2636 
  CORE_ADDR sp = get_frame_register_unsigned (this_frame,
2637 
                                              gdbarch_sp_regnum (gdbarch));
2638 
  return frame_id_build (sp, get_frame_pc (this_frame));
2639 
}
2640 
 
2641 
static CORE_ADDR
2642 
sh_frame_base_address (struct frame_info *this_frame, void **this_cache)
2643 
{
2644 
  struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
2645 
 
2646 
  return cache->base;
2647 
}
2648 
 
2649 
static const struct frame_base sh_frame_base = {
2650 
  &sh_frame_unwind,
2651 
  sh_frame_base_address,
2652 
  sh_frame_base_address,
2653 
  sh_frame_base_address
2654 
};
2655 
 
2656 
/* The epilogue is defined here as the area at the end of a function,
2657 
   either on the `ret' instruction itself or after an instruction which
2658 
   destroys the function's stack frame. */
2659 
static int
2660 
sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2661 
{
2662 
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2663 
  CORE_ADDR func_addr = 0, func_end = 0;
2664 
 
2665 
  if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2666 
    {
2667 
      ULONGEST inst;
2668 
      /* The sh epilogue is max. 14 bytes long.  Give another 14 bytes
2669 
         for a nop and some fixed data (e.g. big offsets) which are
2670 
         unfortunately also treated as part of the function (which
2671 
         means, they are below func_end. */
2672 
      CORE_ADDR addr = func_end - 28;
2673 
      if (addr < func_addr + 4)
2674 
        addr = func_addr + 4;
2675 
      if (pc < addr)
2676 
        return 0;
2677 
 
2678 
      /* First search forward until hitting an rts. */
2679 
      while (addr < func_end
2680 
             && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order)))
2681 
        addr += 2;
2682 
      if (addr >= func_end)
2683 
        return 0;
2684 
 
2685 
      /* At this point we should find a mov.l @r15+,r14 instruction,
2686 
         either before or after the rts.  If not, then the function has
2687 
         probably no "normal" epilogue and we bail out here. */
2688 
      inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2689 
      if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2,
2690 
                                                       byte_order)))
2691 
        addr -= 2;
2692 
      else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2,
2693 
                                                             byte_order)))
2694 
        return 0;
2695 
 
2696 
      inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2697 
 
2698 
      /* Step over possible lds.l @r15+,macl. */
2699 
      if (IS_MACL_LDS (inst))
2700 
        {
2701 
          addr -= 2;
2702 
          inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2703 
        }
2704 
 
2705 
      /* Step over possible lds.l @r15+,pr. */
2706 
      if (IS_LDS (inst))
2707 
        {
2708 
          addr -= 2;
2709 
          inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2710 
        }
2711 
 
2712 
      /* Step over possible mov r14,r15. */
2713 
      if (IS_MOV_FP_SP (inst))
2714 
        {
2715 
          addr -= 2;
2716 
          inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2717 
        }
2718 
 
2719 
      /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2720 
         instructions. */
2721 
      while (addr > func_addr + 4
2722 
             && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
2723 
        {
2724 
          addr -= 2;
2725 
          inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2726 
        }
2727 
 
2728 
      /* On SH2a check if the previous instruction was perhaps a MOVI20.
2729 
         That's allowed for the epilogue.  */
2730 
      if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
2731 
           || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
2732 
          && addr > func_addr + 6
2733 
          && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2,
2734 
                                                      byte_order)))
2735 
        addr -= 4;
2736 
 
2737 
      if (pc >= addr)
2738 
        return 1;
2739 
    }
2740 
  return 0;
2741 
}
2742 
 
2743 
 
2744 
/* Supply register REGNUM from the buffer specified by REGS and LEN
2745 
   in the register set REGSET to register cache REGCACHE.
2746 
   REGTABLE specifies where each register can be found in REGS.
2747 
   If REGNUM is -1, do this for all registers in REGSET.  */
2748 
 
2749 
void
2750 
sh_corefile_supply_regset (const struct regset *regset,
2751 
                           struct regcache *regcache,
2752 
                           int regnum, const void *regs, size_t len)
2753 
{
2754 
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
2755 
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2756 
  const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
2757 
                                             ? tdep->core_gregmap
2758 
                                             : tdep->core_fpregmap);
2759 
  int i;
2760 
 
2761 
  for (i = 0; regmap[i].regnum != -1; i++)
2762 
    {
2763 
      if ((regnum == -1 || regnum == regmap[i].regnum)
2764 
          && regmap[i].offset + 4 <= len)
2765 
        regcache_raw_supply (regcache, regmap[i].regnum,
2766 
                             (char *)regs + regmap[i].offset);
2767 
    }
2768 
}
2769 
 
2770 
/* Collect register REGNUM in the register set REGSET from register cache
2771 
   REGCACHE into the buffer specified by REGS and LEN.
2772 
   REGTABLE specifies where each register can be found in REGS.
2773 
   If REGNUM is -1, do this for all registers in REGSET.  */
2774 
 
2775 
void
2776 
sh_corefile_collect_regset (const struct regset *regset,
2777 
                            const struct regcache *regcache,
2778 
                            int regnum, void *regs, size_t len)
2779 
{
2780 
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
2781 
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2782 
  const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
2783 
                                             ? tdep->core_gregmap
2784 
                                             : tdep->core_fpregmap);
2785 
  int i;
2786 
 
2787 
  for (i = 0; regmap[i].regnum != -1; i++)
2788 
    {
2789 
      if ((regnum == -1 || regnum == regmap[i].regnum)
2790 
          && regmap[i].offset + 4 <= len)
2791 
        regcache_raw_collect (regcache, regmap[i].regnum,
2792 
                              (char *)regs + regmap[i].offset);
2793 
    }
2794 
}
2795 
 
2796 
/* The following two regsets have the same contents, so it is tempting to
2797 
   unify them, but they are distiguished by their address, so don't.  */
2798 
 
2799 
struct regset sh_corefile_gregset =
2800 
{
2801 
  NULL,
2802 
  sh_corefile_supply_regset,
2803 
  sh_corefile_collect_regset
2804 
};
2805 
 
2806 
static struct regset sh_corefile_fpregset =
2807 
{
2808 
  NULL,
2809 
  sh_corefile_supply_regset,
2810 
  sh_corefile_collect_regset
2811 
};
2812 
 
2813 
static const struct regset *
2814 
sh_regset_from_core_section (struct gdbarch *gdbarch, const char *sect_name,
2815 
                             size_t sect_size)
2816 
{
2817 
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2818 
 
2819 
  if (tdep->core_gregmap && strcmp (sect_name, ".reg") == 0)
2820 
    return &sh_corefile_gregset;
2821 
 
2822 
  if (tdep->core_fpregmap && strcmp (sect_name, ".reg2") == 0)
2823 
    return &sh_corefile_fpregset;
2824 
 
2825 
  return NULL;
2826 
}
2827 
 
2828 
 
2829 
static struct gdbarch *
2830 
sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2831 
{
2832 
  struct gdbarch *gdbarch;
2833 
  struct gdbarch_tdep *tdep;
2834 
 
2835 
  sh_show_regs = sh_generic_show_regs;
2836 
  switch (info.bfd_arch_info->mach)
2837 
    {
2838 
    case bfd_mach_sh2e:
2839 
      sh_show_regs = sh2e_show_regs;
2840 
      break;
2841 
    case bfd_mach_sh2a:
2842 
      sh_show_regs = sh2a_show_regs;
2843 
      break;
2844 
    case bfd_mach_sh2a_nofpu:
2845 
      sh_show_regs = sh2a_nofpu_show_regs;
2846 
      break;
2847 
    case bfd_mach_sh_dsp:
2848 
      sh_show_regs = sh_dsp_show_regs;
2849 
      break;
2850 
 
2851 
    case bfd_mach_sh3:
2852 
    case bfd_mach_sh3_nommu:
2853 
    case bfd_mach_sh2a_nofpu_or_sh3_nommu:
2854 
      sh_show_regs = sh3_show_regs;
2855 
      break;
2856 
 
2857 
    case bfd_mach_sh3e:
2858 
    case bfd_mach_sh2a_or_sh3e:
2859 
      sh_show_regs = sh3e_show_regs;
2860 
      break;
2861 
 
2862 
    case bfd_mach_sh3_dsp:
2863 
    case bfd_mach_sh4al_dsp:
2864 
      sh_show_regs = sh3_dsp_show_regs;
2865 
      break;
2866 
 
2867 
    case bfd_mach_sh4:
2868 
    case bfd_mach_sh4a:
2869 
    case bfd_mach_sh2a_or_sh4:
2870 
      sh_show_regs = sh4_show_regs;
2871 
      break;
2872 
 
2873 
    case bfd_mach_sh4_nofpu:
2874 
    case bfd_mach_sh4_nommu_nofpu:
2875 
    case bfd_mach_sh4a_nofpu:
2876 
    case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
2877 
      sh_show_regs = sh4_nofpu_show_regs;
2878 
      break;
2879 
 
2880 
    case bfd_mach_sh5:
2881 
      sh_show_regs = sh64_show_regs;
2882 
      /* SH5 is handled entirely in sh64-tdep.c */
2883 
      return sh64_gdbarch_init (info, arches);
2884 
    }
2885 
 
2886 
  /* If there is already a candidate, use it.  */
2887 
  arches = gdbarch_list_lookup_by_info (arches, &info);
2888 
  if (arches != NULL)
2889 
    return arches->gdbarch;
2890 
 
2891 
  /* None found, create a new architecture from the information
2892 
     provided. */
2893 
  tdep = XZALLOC (struct gdbarch_tdep);
2894 
  gdbarch = gdbarch_alloc (&info, tdep);
2895 
 
2896 
  set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2897 
  set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2898 
  set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2899 
  set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2900 
  set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2901 
  set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2902 
  set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2903 
  set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2904 
 
2905 
  set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2906 
  set_gdbarch_sp_regnum (gdbarch, 15);
2907 
  set_gdbarch_pc_regnum (gdbarch, 16);
2908 
  set_gdbarch_fp0_regnum (gdbarch, -1);
2909 
  set_gdbarch_num_pseudo_regs (gdbarch, 0);
2910 
 
2911 
  set_gdbarch_register_type (gdbarch, sh_default_register_type);
2912 
  set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p);
2913 
 
2914 
  set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2915 
 
2916 
  set_gdbarch_print_insn (gdbarch, print_insn_sh);
2917 
  set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2918 
 
2919 
  set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);
2920 
 
2921 
  set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2922 
  set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2923 
 
2924 
  set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2925 
 
2926 
  set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2927 
 
2928 
  set_gdbarch_frame_align (gdbarch, sh_frame_align);
2929 
  set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2930 
  set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2931 
  set_gdbarch_dummy_id (gdbarch, sh_dummy_id);
2932 
  frame_base_set_default (gdbarch, &sh_frame_base);
2933 
 
2934 
  set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2935 
 
2936 
  dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg);
2937 
 
2938 
  set_gdbarch_regset_from_core_section (gdbarch, sh_regset_from_core_section);
2939 
 
2940 
  switch (info.bfd_arch_info->mach)
2941 
    {
2942 
    case bfd_mach_sh:
2943 
      set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2944 
      break;
2945 
 
2946 
    case bfd_mach_sh2:
2947 
      set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2948 
      break;
2949 
 
2950 
    case bfd_mach_sh2e:
2951 
      /* doubles on sh2e and sh3e are actually 4 byte. */
2952 
      set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2953 
 
2954 
      set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2955 
      set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2956 
      set_gdbarch_fp0_regnum (gdbarch, 25);
2957 
      set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2958 
      set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2959 
      break;
2960 
 
2961 
    case bfd_mach_sh2a:
2962 
      set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
2963 
      set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
2964 
      set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2965 
 
2966 
      set_gdbarch_fp0_regnum (gdbarch, 25);
2967 
      set_gdbarch_num_pseudo_regs (gdbarch, 9);
2968 
      set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2969 
      set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2970 
      set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2971 
      set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2972 
      break;
2973 
 
2974 
    case bfd_mach_sh2a_nofpu:
2975 
      set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
2976 
      set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2977 
 
2978 
      set_gdbarch_num_pseudo_regs (gdbarch, 1);
2979 
      set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2980 
      set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2981 
      break;
2982 
 
2983 
    case bfd_mach_sh_dsp:
2984 
      set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2985 
      set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2986 
      break;
2987 
 
2988 
    case bfd_mach_sh3:
2989 
    case bfd_mach_sh3_nommu:
2990 
    case bfd_mach_sh2a_nofpu_or_sh3_nommu:
2991 
      set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2992 
      break;
2993 
 
2994 
    case bfd_mach_sh3e:
2995 
    case bfd_mach_sh2a_or_sh3e:
2996 
      /* doubles on sh2e and sh3e are actually 4 byte. */
2997 
      set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2998 
 
2999 
      set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
3000 
      set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
3001 
      set_gdbarch_fp0_regnum (gdbarch, 25);
3002 
      set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
3003 
      set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
3004 
      break;
3005 
 
3006 
    case bfd_mach_sh3_dsp:
3007 
      set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
3008 
      set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
3009 
      break;
3010 
 
3011 
    case bfd_mach_sh4:
3012 
    case bfd_mach_sh4a:
3013 
    case bfd_mach_sh2a_or_sh4:
3014 
      set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
3015 
      set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
3016 
      set_gdbarch_fp0_regnum (gdbarch, 25);
3017 
      set_gdbarch_num_pseudo_regs (gdbarch, 13);
3018 
      set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
3019 
      set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
3020 
      set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
3021 
      set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
3022 
      break;
3023 
 
3024 
    case bfd_mach_sh4_nofpu:
3025 
    case bfd_mach_sh4a_nofpu:
3026 
    case bfd_mach_sh4_nommu_nofpu:
3027 
    case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
3028 
      set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
3029 
      break;
3030 
 
3031 
    case bfd_mach_sh4al_dsp:
3032 
      set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
3033 
      set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
3034 
      break;
3035 
 
3036 
    default:
3037 
      set_gdbarch_register_name (gdbarch, sh_sh_register_name);
3038 
      break;
3039 
    }
3040 
 
3041 
  /* Hook in ABI-specific overrides, if they have been registered.  */
3042 
  gdbarch_init_osabi (info, gdbarch);
3043 
 
3044 
  dwarf2_append_unwinders (gdbarch);
3045 
  frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind);
3046 
 
3047 
  return gdbarch;
3048 
}
3049 
 
3050 
static void
3051 
show_sh_command (char *args, int from_tty)
3052 
{
3053 
  help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout);
3054 
}
3055 
 
3056 
static void
3057 
set_sh_command (char *args, int from_tty)
3058 
{
3059 
  printf_unfiltered
3060 
    ("\"set sh\" must be followed by an appropriate subcommand.\n");
3061 
  help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout);
3062 
}
3063 
 
3064 
extern initialize_file_ftype _initialize_sh_tdep;       /* -Wmissing-prototypes */
3065 
 
3066 
void
3067 
_initialize_sh_tdep (void)
3068 
{
3069 
  struct cmd_list_element *c;
3070 
 
3071 
  gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
3072 
 
3073 
  add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers"));
3074 
 
3075 
  add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.",
3076 
                  &setshcmdlist, "set sh ", 0, &setlist);
3077 
  add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.",
3078 
                  &showshcmdlist, "show sh ", 0, &showlist);
3079 
 
3080 
  add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum,
3081 
                        &sh_active_calling_convention,
3082 
                        _("Set calling convention used when calling target "
3083 
                          "functions from GDB."),
3084 
                        _("Show calling convention used when calling target "
3085 
                          "functions from GDB."),
3086 
                        _("gcc       - Use GCC calling convention (default).\n"
3087 
                          "renesas   - Enforce Renesas calling convention."),
3088 
                        NULL, NULL,
3089 
                        &setshcmdlist, &showshcmdlist);
3090 
}

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