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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.2/] [gdb/] [sparc-tdep.c] - Blame information for rev 330

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1 330 jeremybenn
/* Target-dependent code for SPARC.
2
 
3
   Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4
   Free Software Foundation, Inc.
5
 
6
   This file is part of GDB.
7
 
8
   This program is free software; you can redistribute it and/or modify
9
   it under the terms of the GNU General Public License as published by
10
   the Free Software Foundation; either version 3 of the License, or
11
   (at your option) any later version.
12
 
13
   This program is distributed in the hope that it will be useful,
14
   but WITHOUT ANY WARRANTY; without even the implied warranty of
15
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
   GNU General Public License for more details.
17
 
18
   You should have received a copy of the GNU General Public License
19
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
20
 
21
#include "defs.h"
22
#include "arch-utils.h"
23
#include "dis-asm.h"
24
#include "dwarf2-frame.h"
25
#include "floatformat.h"
26
#include "frame.h"
27
#include "frame-base.h"
28
#include "frame-unwind.h"
29
#include "gdbcore.h"
30
#include "gdbtypes.h"
31
#include "inferior.h"
32
#include "symtab.h"
33
#include "objfiles.h"
34
#include "osabi.h"
35
#include "regcache.h"
36
#include "target.h"
37
#include "value.h"
38
 
39
#include "gdb_assert.h"
40
#include "gdb_string.h"
41
 
42
#include "sparc-tdep.h"
43
 
44
struct regset;
45
 
46
/* This file implements the SPARC 32-bit ABI as defined by the section
47
   "Low-Level System Information" of the SPARC Compliance Definition
48
   (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC.  The SCD
49
   lists changes with respect to the original 32-bit psABI as defined
50
   in the "System V ABI, SPARC Processor Supplement".
51
 
52
   Note that if we talk about SunOS, we mean SunOS 4.x, which was
53
   BSD-based, which is sometimes (retroactively?) referred to as
54
   Solaris 1.x.  If we talk about Solaris we mean Solaris 2.x and
55
   above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
56
   suffering from severe version number inflation).  Solaris 2.x is
57
   also known as SunOS 5.x, since that's what uname(1) says.  Solaris
58
   2.x is SVR4-based.  */
59
 
60
/* Please use the sparc32_-prefix for 32-bit specific code, the
61
   sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
62
   code that can handle both.  The 64-bit specific code lives in
63
   sparc64-tdep.c; don't add any here.  */
64
 
65
/* The SPARC Floating-Point Quad-Precision format is similar to
66
   big-endian IA-64 Quad-recision format.  */
67
#define floatformats_sparc_quad floatformats_ia64_quad
68
 
69
/* The stack pointer is offset from the stack frame by a BIAS of 2047
70
   (0x7ff) for 64-bit code.  BIAS is likely to be defined on SPARC
71
   hosts, so undefine it first.  */
72
#undef BIAS
73
#define BIAS 2047
74
 
75
/* Macros to extract fields from SPARC instructions.  */
76
#define X_OP(i) (((i) >> 30) & 0x3)
77
#define X_RD(i) (((i) >> 25) & 0x1f)
78
#define X_A(i) (((i) >> 29) & 1)
79
#define X_COND(i) (((i) >> 25) & 0xf)
80
#define X_OP2(i) (((i) >> 22) & 0x7)
81
#define X_IMM22(i) ((i) & 0x3fffff)
82
#define X_OP3(i) (((i) >> 19) & 0x3f)
83
#define X_RS1(i) (((i) >> 14) & 0x1f)
84
#define X_RS2(i) ((i) & 0x1f)
85
#define X_I(i) (((i) >> 13) & 1)
86
/* Sign extension macros.  */
87
#define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
88
#define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
89
#define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
90
 
91
/* Fetch the instruction at PC.  Instructions are always big-endian
92
   even if the processor operates in little-endian mode.  */
93
 
94
unsigned long
95
sparc_fetch_instruction (CORE_ADDR pc)
96
{
97
  gdb_byte buf[4];
98
  unsigned long insn;
99
  int i;
100
 
101
  /* If we can't read the instruction at PC, return zero.  */
102
  if (target_read_memory (pc, buf, sizeof (buf)))
103
    return 0;
104
 
105
  insn = 0;
106
  for (i = 0; i < sizeof (buf); i++)
107
    insn = (insn << 8) | buf[i];
108
  return insn;
109
}
110
 
111
 
112
/* Return non-zero if the instruction corresponding to PC is an "unimp"
113
   instruction.  */
114
 
115
static int
116
sparc_is_unimp_insn (CORE_ADDR pc)
117
{
118
  const unsigned long insn = sparc_fetch_instruction (pc);
119
 
120
  return ((insn & 0xc1c00000) == 0);
121
}
122
 
123
/* OpenBSD/sparc includes StackGhost, which according to the author's
124
   website http://stackghost.cerias.purdue.edu "... transparently and
125
   automatically protects applications' stack frames; more
126
   specifically, it guards the return pointers.  The protection
127
   mechanisms require no application source or binary modification and
128
   imposes only a negligible performance penalty."
129
 
130
   The same website provides the following description of how
131
   StackGhost works:
132
 
133
   "StackGhost interfaces with the kernel trap handler that would
134
   normally write out registers to the stack and the handler that
135
   would read them back in.  By XORing a cookie into the
136
   return-address saved in the user stack when it is actually written
137
   to the stack, and then XOR it out when the return-address is pulled
138
   from the stack, StackGhost can cause attacker corrupted return
139
   pointers to behave in a manner the attacker cannot predict.
140
   StackGhost can also use several unused bits in the return pointer
141
   to detect a smashed return pointer and abort the process."
142
 
143
   For GDB this means that whenever we're reading %i7 from a stack
144
   frame's window save area, we'll have to XOR the cookie.
145
 
146
   More information on StackGuard can be found on in:
147
 
148
   Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
149
   Stack Protection."  2001.  Published in USENIX Security Symposium
150
   '01.  */
151
 
152
/* Fetch StackGhost Per-Process XOR cookie.  */
153
 
154
ULONGEST
155
sparc_fetch_wcookie (struct gdbarch *gdbarch)
156
{
157
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
158
  struct target_ops *ops = &current_target;
159
  gdb_byte buf[8];
160
  int len;
161
 
162
  len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8);
163
  if (len == -1)
164
    return 0;
165
 
166
  /* We should have either an 32-bit or an 64-bit cookie.  */
167
  gdb_assert (len == 4 || len == 8);
168
 
169
  return extract_unsigned_integer (buf, len, byte_order);
170
}
171
 
172
 
173
/* The functions on this page are intended to be used to classify
174
   function arguments.  */
175
 
176
/* Check whether TYPE is "Integral or Pointer".  */
177
 
178
static int
179
sparc_integral_or_pointer_p (const struct type *type)
180
{
181
  int len = TYPE_LENGTH (type);
182
 
183
  switch (TYPE_CODE (type))
184
    {
185
    case TYPE_CODE_INT:
186
    case TYPE_CODE_BOOL:
187
    case TYPE_CODE_CHAR:
188
    case TYPE_CODE_ENUM:
189
    case TYPE_CODE_RANGE:
190
      /* We have byte, half-word, word and extended-word/doubleword
191
         integral types.  The doubleword is an extension to the
192
         original 32-bit ABI by the SCD 2.4.x.  */
193
      return (len == 1 || len == 2 || len == 4 || len == 8);
194
    case TYPE_CODE_PTR:
195
    case TYPE_CODE_REF:
196
      /* Allow either 32-bit or 64-bit pointers.  */
197
      return (len == 4 || len == 8);
198
    default:
199
      break;
200
    }
201
 
202
  return 0;
203
}
204
 
205
/* Check whether TYPE is "Floating".  */
206
 
207
static int
208
sparc_floating_p (const struct type *type)
209
{
210
  switch (TYPE_CODE (type))
211
    {
212
    case TYPE_CODE_FLT:
213
      {
214
        int len = TYPE_LENGTH (type);
215
        return (len == 4 || len == 8 || len == 16);
216
      }
217
    default:
218
      break;
219
    }
220
 
221
  return 0;
222
}
223
 
224
/* Check whether TYPE is "Structure or Union".
225
 
226
   In terms of Ada subprogram calls, arrays are treated the same as
227
   struct and union types.  So this function also returns non-zero
228
   for array types.  */
229
 
230
static int
231
sparc_structure_or_union_p (const struct type *type)
232
{
233
  switch (TYPE_CODE (type))
234
    {
235
    case TYPE_CODE_STRUCT:
236
    case TYPE_CODE_UNION:
237
    case TYPE_CODE_ARRAY:
238
      return 1;
239
    default:
240
      break;
241
    }
242
 
243
  return 0;
244
}
245
 
246
/* Register information.  */
247
 
248
static const char *sparc32_register_names[] =
249
{
250
  "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
251
  "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
252
  "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
253
  "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
254
 
255
  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
256
  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
257
  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
258
  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
259
 
260
  "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
261
};
262
 
263
/* Total number of registers.  */
264
#define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
265
 
266
/* We provide the aliases %d0..%d30 for the floating registers as
267
   "psuedo" registers.  */
268
 
269
static const char *sparc32_pseudo_register_names[] =
270
{
271
  "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
272
  "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
273
};
274
 
275
/* Total number of pseudo registers.  */
276
#define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
277
 
278
/* Return the name of register REGNUM.  */
279
 
280
static const char *
281
sparc32_register_name (struct gdbarch *gdbarch, int regnum)
282
{
283
  if (regnum >= 0 && regnum < SPARC32_NUM_REGS)
284
    return sparc32_register_names[regnum];
285
 
286
  if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS)
287
    return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS];
288
 
289
  return NULL;
290
}
291
 
292
/* Construct types for ISA-specific registers.  */
293
 
294
static struct type *
295
sparc_psr_type (struct gdbarch *gdbarch)
296
{
297
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
298
 
299
  if (!tdep->sparc_psr_type)
300
    {
301
      struct type *type;
302
 
303
      type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 4);
304
      append_flags_type_flag (type, 5, "ET");
305
      append_flags_type_flag (type, 6, "PS");
306
      append_flags_type_flag (type, 7, "S");
307
      append_flags_type_flag (type, 12, "EF");
308
      append_flags_type_flag (type, 13, "EC");
309
 
310
      tdep->sparc_psr_type = type;
311
    }
312
 
313
  return tdep->sparc_psr_type;
314
}
315
 
316
static struct type *
317
sparc_fsr_type (struct gdbarch *gdbarch)
318
{
319
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
320
 
321
  if (!tdep->sparc_fsr_type)
322
    {
323
      struct type *type;
324
 
325
      type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 4);
326
      append_flags_type_flag (type, 0, "NXA");
327
      append_flags_type_flag (type, 1, "DZA");
328
      append_flags_type_flag (type, 2, "UFA");
329
      append_flags_type_flag (type, 3, "OFA");
330
      append_flags_type_flag (type, 4, "NVA");
331
      append_flags_type_flag (type, 5, "NXC");
332
      append_flags_type_flag (type, 6, "DZC");
333
      append_flags_type_flag (type, 7, "UFC");
334
      append_flags_type_flag (type, 8, "OFC");
335
      append_flags_type_flag (type, 9, "NVC");
336
      append_flags_type_flag (type, 22, "NS");
337
      append_flags_type_flag (type, 23, "NXM");
338
      append_flags_type_flag (type, 24, "DZM");
339
      append_flags_type_flag (type, 25, "UFM");
340
      append_flags_type_flag (type, 26, "OFM");
341
      append_flags_type_flag (type, 27, "NVM");
342
 
343
      tdep->sparc_fsr_type = type;
344
    }
345
 
346
  return tdep->sparc_fsr_type;
347
}
348
 
349
/* Return the GDB type object for the "standard" data type of data in
350
   register REGNUM. */
351
 
352
static struct type *
353
sparc32_register_type (struct gdbarch *gdbarch, int regnum)
354
{
355
  if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM)
356
    return builtin_type (gdbarch)->builtin_float;
357
 
358
  if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM)
359
    return builtin_type (gdbarch)->builtin_double;
360
 
361
  if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM)
362
    return builtin_type (gdbarch)->builtin_data_ptr;
363
 
364
  if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
365
    return builtin_type (gdbarch)->builtin_func_ptr;
366
 
367
  if (regnum == SPARC32_PSR_REGNUM)
368
    return sparc_psr_type (gdbarch);
369
 
370
  if (regnum == SPARC32_FSR_REGNUM)
371
    return sparc_fsr_type (gdbarch);
372
 
373
  return builtin_type (gdbarch)->builtin_int32;
374
}
375
 
376
static void
377
sparc32_pseudo_register_read (struct gdbarch *gdbarch,
378
                              struct regcache *regcache,
379
                              int regnum, gdb_byte *buf)
380
{
381
  gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
382
 
383
  regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
384
  regcache_raw_read (regcache, regnum, buf);
385
  regcache_raw_read (regcache, regnum + 1, buf + 4);
386
}
387
 
388
static void
389
sparc32_pseudo_register_write (struct gdbarch *gdbarch,
390
                               struct regcache *regcache,
391
                               int regnum, const gdb_byte *buf)
392
{
393
  gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
394
 
395
  regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
396
  regcache_raw_write (regcache, regnum, buf);
397
  regcache_raw_write (regcache, regnum + 1, buf + 4);
398
}
399
 
400
 
401
static CORE_ADDR
402
sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
403
                         CORE_ADDR funcaddr,
404
                         struct value **args, int nargs,
405
                         struct type *value_type,
406
                         CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
407
                         struct regcache *regcache)
408
{
409
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
410
 
411
  *bp_addr = sp - 4;
412
  *real_pc = funcaddr;
413
 
414
  if (using_struct_return (gdbarch, NULL, value_type))
415
    {
416
      gdb_byte buf[4];
417
 
418
      /* This is an UNIMP instruction.  */
419
      store_unsigned_integer (buf, 4, byte_order,
420
                              TYPE_LENGTH (value_type) & 0x1fff);
421
      write_memory (sp - 8, buf, 4);
422
      return sp - 8;
423
    }
424
 
425
  return sp - 4;
426
}
427
 
428
static CORE_ADDR
429
sparc32_store_arguments (struct regcache *regcache, int nargs,
430
                         struct value **args, CORE_ADDR sp,
431
                         int struct_return, CORE_ADDR struct_addr)
432
{
433
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
434
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
435
  /* Number of words in the "parameter array".  */
436
  int num_elements = 0;
437
  int element = 0;
438
  int i;
439
 
440
  for (i = 0; i < nargs; i++)
441
    {
442
      struct type *type = value_type (args[i]);
443
      int len = TYPE_LENGTH (type);
444
 
445
      if (sparc_structure_or_union_p (type)
446
          || (sparc_floating_p (type) && len == 16))
447
        {
448
          /* Structure, Union and Quad-Precision Arguments.  */
449
          sp -= len;
450
 
451
          /* Use doubleword alignment for these values.  That's always
452
             correct, and wasting a few bytes shouldn't be a problem.  */
453
          sp &= ~0x7;
454
 
455
          write_memory (sp, value_contents (args[i]), len);
456
          args[i] = value_from_pointer (lookup_pointer_type (type), sp);
457
          num_elements++;
458
        }
459
      else if (sparc_floating_p (type))
460
        {
461
          /* Floating arguments.  */
462
          gdb_assert (len == 4 || len == 8);
463
          num_elements += (len / 4);
464
        }
465
      else
466
        {
467
          /* Integral and pointer arguments.  */
468
          gdb_assert (sparc_integral_or_pointer_p (type));
469
 
470
          if (len < 4)
471
            args[i] = value_cast (builtin_type (gdbarch)->builtin_int32,
472
                                  args[i]);
473
          num_elements += ((len + 3) / 4);
474
        }
475
    }
476
 
477
  /* Always allocate at least six words.  */
478
  sp -= max (6, num_elements) * 4;
479
 
480
  /* The psABI says that "Software convention requires space for the
481
     struct/union return value pointer, even if the word is unused."  */
482
  sp -= 4;
483
 
484
  /* The psABI says that "Although software convention and the
485
     operating system require every stack frame to be doubleword
486
     aligned."  */
487
  sp &= ~0x7;
488
 
489
  for (i = 0; i < nargs; i++)
490
    {
491
      const bfd_byte *valbuf = value_contents (args[i]);
492
      struct type *type = value_type (args[i]);
493
      int len = TYPE_LENGTH (type);
494
 
495
      gdb_assert (len == 4 || len == 8);
496
 
497
      if (element < 6)
498
        {
499
          int regnum = SPARC_O0_REGNUM + element;
500
 
501
          regcache_cooked_write (regcache, regnum, valbuf);
502
          if (len > 4 && element < 5)
503
            regcache_cooked_write (regcache, regnum + 1, valbuf + 4);
504
        }
505
 
506
      /* Always store the argument in memory.  */
507
      write_memory (sp + 4 + element * 4, valbuf, len);
508
      element += len / 4;
509
    }
510
 
511
  gdb_assert (element == num_elements);
512
 
513
  if (struct_return)
514
    {
515
      gdb_byte buf[4];
516
 
517
      store_unsigned_integer (buf, 4, byte_order, struct_addr);
518
      write_memory (sp, buf, 4);
519
    }
520
 
521
  return sp;
522
}
523
 
524
static CORE_ADDR
525
sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
526
                         struct regcache *regcache, CORE_ADDR bp_addr,
527
                         int nargs, struct value **args, CORE_ADDR sp,
528
                         int struct_return, CORE_ADDR struct_addr)
529
{
530
  CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8));
531
 
532
  /* Set return address.  */
533
  regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc);
534
 
535
  /* Set up function arguments.  */
536
  sp = sparc32_store_arguments (regcache, nargs, args, sp,
537
                                struct_return, struct_addr);
538
 
539
  /* Allocate the 16-word window save area.  */
540
  sp -= 16 * 4;
541
 
542
  /* Stack should be doubleword aligned at this point.  */
543
  gdb_assert (sp % 8 == 0);
544
 
545
  /* Finally, update the stack pointer.  */
546
  regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp);
547
 
548
  return sp;
549
}
550
 
551
 
552
/* Use the program counter to determine the contents and size of a
553
   breakpoint instruction.  Return a pointer to a string of bytes that
554
   encode a breakpoint instruction, store the length of the string in
555
   *LEN and optionally adjust *PC to point to the correct memory
556
   location for inserting the breakpoint.  */
557
 
558
static const gdb_byte *
559
sparc_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
560
{
561
  static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 };
562
 
563
  *len = sizeof (break_insn);
564
  return break_insn;
565
}
566
 
567
 
568
/* Allocate and initialize a frame cache.  */
569
 
570
static struct sparc_frame_cache *
571
sparc_alloc_frame_cache (void)
572
{
573
  struct sparc_frame_cache *cache;
574
  int i;
575
 
576
  cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache);
577
 
578
  /* Base address.  */
579
  cache->base = 0;
580
  cache->pc = 0;
581
 
582
  /* Frameless until proven otherwise.  */
583
  cache->frameless_p = 1;
584
 
585
  cache->struct_return_p = 0;
586
 
587
  return cache;
588
}
589
 
590
/* GCC generates several well-known sequences of instructions at the begining
591
   of each function prologue when compiling with -fstack-check.  If one of
592
   such sequences starts at START_PC, then return the address of the
593
   instruction immediately past this sequence.  Otherwise, return START_PC.  */
594
 
595
static CORE_ADDR
596
sparc_skip_stack_check (const CORE_ADDR start_pc)
597
{
598
  CORE_ADDR pc = start_pc;
599
  unsigned long insn;
600
  int offset_stack_checking_sequence = 0;
601
 
602
  /* With GCC, all stack checking sequences begin with the same two
603
     instructions.  */
604
 
605
  /* sethi <some immediate>,%g1 */
606
  insn = sparc_fetch_instruction (pc);
607
  pc = pc + 4;
608
  if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1))
609
    return start_pc;
610
 
611
  /* sub %sp, %g1, %g1 */
612
  insn = sparc_fetch_instruction (pc);
613
  pc = pc + 4;
614
  if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
615
        && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1))
616
    return start_pc;
617
 
618
  insn = sparc_fetch_instruction (pc);
619
  pc = pc + 4;
620
 
621
  /* First possible sequence:
622
         [first two instructions above]
623
         clr [%g1 - some immediate]  */
624
 
625
  /* clr [%g1 - some immediate]  */
626
  if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
627
      && X_RS1 (insn) == 1 && X_RD (insn) == 0)
628
    {
629
      /* Valid stack-check sequence, return the new PC.  */
630
      return pc;
631
    }
632
 
633
  /* Second possible sequence: A small number of probes.
634
         [first two instructions above]
635
         clr [%g1]
636
         add   %g1, -<some immediate>, %g1
637
         clr [%g1]
638
         [repeat the two instructions above any (small) number of times]
639
         clr [%g1 - some immediate]  */
640
 
641
  /* clr [%g1] */
642
  else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
643
      && X_RS1 (insn) == 1 && X_RD (insn) == 0)
644
    {
645
      while (1)
646
        {
647
          /* add %g1, -<some immediate>, %g1 */
648
          insn = sparc_fetch_instruction (pc);
649
          pc = pc + 4;
650
          if (!(X_OP (insn) == 2  && X_OP3(insn) == 0 && X_I(insn)
651
                && X_RS1 (insn) == 1 && X_RD (insn) == 1))
652
            break;
653
 
654
          /* clr [%g1] */
655
          insn = sparc_fetch_instruction (pc);
656
          pc = pc + 4;
657
          if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
658
                && X_RD (insn) == 0 && X_RS1 (insn) == 1))
659
            return start_pc;
660
        }
661
 
662
      /* clr [%g1 - some immediate] */
663
      if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
664
            && X_RS1 (insn) == 1 && X_RD (insn) == 0))
665
        return start_pc;
666
 
667
      /* We found a valid stack-check sequence, return the new PC.  */
668
      return pc;
669
    }
670
 
671
  /* Third sequence: A probing loop.
672
         [first two instructions above]
673
         sethi  <some immediate>, %g4
674
         sub  %g1, %g4, %g4
675
         cmp  %g1, %g4
676
         be  <disp>
677
         add  %g1, -<some immediate>, %g1
678
         ba  <disp>
679
         clr  [%g1]
680
         clr [%g4 - some immediate]  */
681
 
682
  /* sethi  <some immediate>, %g4 */
683
  else if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4)
684
    {
685
      /* sub  %g1, %g4, %g4 */
686
      insn = sparc_fetch_instruction (pc);
687
      pc = pc + 4;
688
      if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
689
            && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
690
        return start_pc;
691
 
692
      /* cmp  %g1, %g4 */
693
      insn = sparc_fetch_instruction (pc);
694
      pc = pc + 4;
695
      if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn)
696
            && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
697
        return start_pc;
698
 
699
      /* be  <disp> */
700
      insn = sparc_fetch_instruction (pc);
701
      pc = pc + 4;
702
      if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1))
703
        return start_pc;
704
 
705
      /* add  %g1, -<some immediate>, %g1 */
706
      insn = sparc_fetch_instruction (pc);
707
      pc = pc + 4;
708
      if (!(X_OP (insn) == 2  && X_OP3(insn) == 0 && X_I(insn)
709
            && X_RS1 (insn) == 1 && X_RD (insn) == 1))
710
        return start_pc;
711
 
712
      /* ba  <disp> */
713
      insn = sparc_fetch_instruction (pc);
714
      pc = pc + 4;
715
      if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8))
716
        return start_pc;
717
 
718
      /* clr  [%g1] */
719
      insn = sparc_fetch_instruction (pc);
720
      pc = pc + 4;
721
      if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
722
            && X_RD (insn) == 0 && X_RS1 (insn) == 1))
723
        return start_pc;
724
 
725
      /* clr [%g4 - some immediate]  */
726
      insn = sparc_fetch_instruction (pc);
727
      pc = pc + 4;
728
      if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
729
            && X_RS1 (insn) == 4 && X_RD (insn) == 0))
730
        return start_pc;
731
 
732
      /* We found a valid stack-check sequence, return the new PC.  */
733
      return pc;
734
    }
735
 
736
  /* No stack check code in our prologue, return the start_pc.  */
737
  return start_pc;
738
}
739
 
740
CORE_ADDR
741
sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
742
                        CORE_ADDR current_pc, struct sparc_frame_cache *cache)
743
{
744
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
745
  unsigned long insn;
746
  int offset = 0;
747
  int dest = -1;
748
 
749
  pc = sparc_skip_stack_check (pc);
750
 
751
  if (current_pc <= pc)
752
    return current_pc;
753
 
754
  /* We have to handle to "Procedure Linkage Table" (PLT) special.  On
755
     SPARC the linker usually defines a symbol (typically
756
     _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
757
     This symbol makes us end up here with PC pointing at the start of
758
     the PLT and CURRENT_PC probably pointing at a PLT entry.  If we
759
     would do our normal prologue analysis, we would probably conclude
760
     that we've got a frame when in reality we don't, since the
761
     dynamic linker patches up the first PLT with some code that
762
     starts with a SAVE instruction.  Patch up PC such that it points
763
     at the start of our PLT entry.  */
764
  if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL))
765
    pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size);
766
 
767
  insn = sparc_fetch_instruction (pc);
768
 
769
  /* Recognize a SETHI insn and record its destination.  */
770
  if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04)
771
    {
772
      dest = X_RD (insn);
773
      offset += 4;
774
 
775
      insn = sparc_fetch_instruction (pc + 4);
776
    }
777
 
778
  /* Allow for an arithmetic operation on DEST or %g1.  */
779
  if (X_OP (insn) == 2 && X_I (insn)
780
      && (X_RD (insn) == 1 || X_RD (insn) == dest))
781
    {
782
      offset += 4;
783
 
784
      insn = sparc_fetch_instruction (pc + 8);
785
    }
786
 
787
  /* Check for the SAVE instruction that sets up the frame.  */
788
  if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c)
789
    {
790
      cache->frameless_p = 0;
791
      return pc + offset + 4;
792
    }
793
 
794
  return pc;
795
}
796
 
797
static CORE_ADDR
798
sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
799
{
800
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
801
  return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum);
802
}
803
 
804
/* Return PC of first real instruction of the function starting at
805
   START_PC.  */
806
 
807
static CORE_ADDR
808
sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
809
{
810
  struct symtab_and_line sal;
811
  CORE_ADDR func_start, func_end;
812
  struct sparc_frame_cache cache;
813
 
814
  /* This is the preferred method, find the end of the prologue by
815
     using the debugging information.  */
816
  if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end))
817
    {
818
      sal = find_pc_line (func_start, 0);
819
 
820
      if (sal.end < func_end
821
          && start_pc <= sal.end)
822
        return sal.end;
823
    }
824
 
825
  start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache);
826
 
827
  /* The psABI says that "Although the first 6 words of arguments
828
     reside in registers, the standard stack frame reserves space for
829
     them.".  It also suggests that a function may use that space to
830
     "write incoming arguments 0 to 5" into that space, and that's
831
     indeed what GCC seems to be doing.  In that case GCC will
832
     generate debug information that points to the stack slots instead
833
     of the registers, so we should consider the instructions that
834
     write out these incoming arguments onto the stack.  Of course we
835
     only need to do this if we have a stack frame.  */
836
 
837
  while (!cache.frameless_p)
838
    {
839
      unsigned long insn = sparc_fetch_instruction (start_pc);
840
 
841
      /* Recognize instructions that store incoming arguments in
842
         %i0...%i5 into the corresponding stack slot.  */
843
      if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 && X_I (insn)
844
          && (X_RD (insn) >= 24 && X_RD (insn) <= 29) && X_RS1 (insn) == 30
845
          && X_SIMM13 (insn) == 68 + (X_RD (insn) - 24) * 4)
846
        {
847
          start_pc += 4;
848
          continue;
849
        }
850
 
851
      break;
852
    }
853
 
854
  return start_pc;
855
}
856
 
857
/* Normal frames.  */
858
 
859
struct sparc_frame_cache *
860
sparc_frame_cache (struct frame_info *this_frame, void **this_cache)
861
{
862
  struct sparc_frame_cache *cache;
863
 
864
  if (*this_cache)
865
    return *this_cache;
866
 
867
  cache = sparc_alloc_frame_cache ();
868
  *this_cache = cache;
869
 
870
  cache->pc = get_frame_func (this_frame);
871
  if (cache->pc != 0)
872
    sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc,
873
                            get_frame_pc (this_frame), cache);
874
 
875
  if (cache->frameless_p)
876
    {
877
      /* This function is frameless, so %fp (%i6) holds the frame
878
         pointer for our calling frame.  Use %sp (%o6) as this frame's
879
         base address.  */
880
      cache->base =
881
        get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM);
882
    }
883
  else
884
    {
885
      /* For normal frames, %fp (%i6) holds the frame pointer, the
886
         base address for the current stack frame.  */
887
      cache->base =
888
        get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM);
889
    }
890
 
891
  if (cache->base & 1)
892
    cache->base += BIAS;
893
 
894
  return cache;
895
}
896
 
897
static int
898
sparc32_struct_return_from_sym (struct symbol *sym)
899
{
900
  struct type *type = check_typedef (SYMBOL_TYPE (sym));
901
  enum type_code code = TYPE_CODE (type);
902
 
903
  if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD)
904
    {
905
      type = check_typedef (TYPE_TARGET_TYPE (type));
906
      if (sparc_structure_or_union_p (type)
907
          || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
908
        return 1;
909
    }
910
 
911
  return 0;
912
}
913
 
914
struct sparc_frame_cache *
915
sparc32_frame_cache (struct frame_info *this_frame, void **this_cache)
916
{
917
  struct sparc_frame_cache *cache;
918
  struct symbol *sym;
919
 
920
  if (*this_cache)
921
    return *this_cache;
922
 
923
  cache = sparc_frame_cache (this_frame, this_cache);
924
 
925
  sym = find_pc_function (cache->pc);
926
  if (sym)
927
    {
928
      cache->struct_return_p = sparc32_struct_return_from_sym (sym);
929
    }
930
  else
931
    {
932
      /* There is no debugging information for this function to
933
         help us determine whether this function returns a struct
934
         or not.  So we rely on another heuristic which is to check
935
         the instruction at the return address and see if this is
936
         an "unimp" instruction.  If it is, then it is a struct-return
937
         function.  */
938
      CORE_ADDR pc;
939
      int regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM;
940
 
941
      pc = get_frame_register_unsigned (this_frame, regnum) + 8;
942
      if (sparc_is_unimp_insn (pc))
943
        cache->struct_return_p = 1;
944
    }
945
 
946
  return cache;
947
}
948
 
949
static void
950
sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache,
951
                       struct frame_id *this_id)
952
{
953
  struct sparc_frame_cache *cache =
954
    sparc32_frame_cache (this_frame, this_cache);
955
 
956
  /* This marks the outermost frame.  */
957
  if (cache->base == 0)
958
    return;
959
 
960
  (*this_id) = frame_id_build (cache->base, cache->pc);
961
}
962
 
963
static struct value *
964
sparc32_frame_prev_register (struct frame_info *this_frame,
965
                             void **this_cache, int regnum)
966
{
967
  struct gdbarch *gdbarch = get_frame_arch (this_frame);
968
  struct sparc_frame_cache *cache =
969
    sparc32_frame_cache (this_frame, this_cache);
970
 
971
  if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
972
    {
973
      CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0;
974
 
975
      /* If this functions has a Structure, Union or Quad-Precision
976
         return value, we have to skip the UNIMP instruction that encodes
977
         the size of the structure.  */
978
      if (cache->struct_return_p)
979
        pc += 4;
980
 
981
      regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM;
982
      pc += get_frame_register_unsigned (this_frame, regnum) + 8;
983
      return frame_unwind_got_constant (this_frame, regnum, pc);
984
    }
985
 
986
  /* Handle StackGhost.  */
987
  {
988
    ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
989
 
990
    if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM)
991
      {
992
        CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
993
        ULONGEST i7;
994
 
995
        /* Read the value in from memory.  */
996
        i7 = get_frame_memory_unsigned (this_frame, addr, 4);
997
        return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie);
998
      }
999
  }
1000
 
1001
  /* The previous frame's `local' and `in' registers have been saved
1002
     in the register save area.  */
1003
  if (!cache->frameless_p
1004
      && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM)
1005
    {
1006
      CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
1007
 
1008
      return frame_unwind_got_memory (this_frame, regnum, addr);
1009
    }
1010
 
1011
  /* The previous frame's `out' registers are accessible as the
1012
     current frame's `in' registers.  */
1013
  if (!cache->frameless_p
1014
      && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM)
1015
    regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM);
1016
 
1017
  return frame_unwind_got_register (this_frame, regnum, regnum);
1018
}
1019
 
1020
static const struct frame_unwind sparc32_frame_unwind =
1021
{
1022
  NORMAL_FRAME,
1023
  sparc32_frame_this_id,
1024
  sparc32_frame_prev_register,
1025
  NULL,
1026
  default_frame_sniffer
1027
};
1028
 
1029
 
1030
static CORE_ADDR
1031
sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache)
1032
{
1033
  struct sparc_frame_cache *cache =
1034
    sparc32_frame_cache (this_frame, this_cache);
1035
 
1036
  return cache->base;
1037
}
1038
 
1039
static const struct frame_base sparc32_frame_base =
1040
{
1041
  &sparc32_frame_unwind,
1042
  sparc32_frame_base_address,
1043
  sparc32_frame_base_address,
1044
  sparc32_frame_base_address
1045
};
1046
 
1047
static struct frame_id
1048
sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1049
{
1050
  CORE_ADDR sp;
1051
 
1052
  sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM);
1053
  if (sp & 1)
1054
    sp += BIAS;
1055
  return frame_id_build (sp, get_frame_pc (this_frame));
1056
}
1057
 
1058
 
1059
/* Extract a function return value of TYPE from REGCACHE, and copy
1060
   that into VALBUF.  */
1061
 
1062
static void
1063
sparc32_extract_return_value (struct type *type, struct regcache *regcache,
1064
                              gdb_byte *valbuf)
1065
{
1066
  int len = TYPE_LENGTH (type);
1067
  gdb_byte buf[8];
1068
 
1069
  gdb_assert (!sparc_structure_or_union_p (type));
1070
  gdb_assert (!(sparc_floating_p (type) && len == 16));
1071
 
1072
  if (sparc_floating_p (type))
1073
    {
1074
      /* Floating return values.  */
1075
      regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf);
1076
      if (len > 4)
1077
        regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4);
1078
      memcpy (valbuf, buf, len);
1079
    }
1080
  else
1081
    {
1082
      /* Integral and pointer return values.  */
1083
      gdb_assert (sparc_integral_or_pointer_p (type));
1084
 
1085
      regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf);
1086
      if (len > 4)
1087
        {
1088
          regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4);
1089
          gdb_assert (len == 8);
1090
          memcpy (valbuf, buf, 8);
1091
        }
1092
      else
1093
        {
1094
          /* Just stripping off any unused bytes should preserve the
1095
             signed-ness just fine.  */
1096
          memcpy (valbuf, buf + 4 - len, len);
1097
        }
1098
    }
1099
}
1100
 
1101
/* Store the function return value of type TYPE from VALBUF into
1102
   REGCACHE.  */
1103
 
1104
static void
1105
sparc32_store_return_value (struct type *type, struct regcache *regcache,
1106
                            const gdb_byte *valbuf)
1107
{
1108
  int len = TYPE_LENGTH (type);
1109
  gdb_byte buf[8];
1110
 
1111
  gdb_assert (!sparc_structure_or_union_p (type));
1112
  gdb_assert (!(sparc_floating_p (type) && len == 16));
1113
  gdb_assert (len <= 8);
1114
 
1115
  if (sparc_floating_p (type))
1116
    {
1117
      /* Floating return values.  */
1118
      memcpy (buf, valbuf, len);
1119
      regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf);
1120
      if (len > 4)
1121
        regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4);
1122
    }
1123
  else
1124
    {
1125
      /* Integral and pointer return values.  */
1126
      gdb_assert (sparc_integral_or_pointer_p (type));
1127
 
1128
      if (len > 4)
1129
        {
1130
          gdb_assert (len == 8);
1131
          memcpy (buf, valbuf, 8);
1132
          regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4);
1133
        }
1134
      else
1135
        {
1136
          /* ??? Do we need to do any sign-extension here?  */
1137
          memcpy (buf + 4 - len, valbuf, len);
1138
        }
1139
      regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf);
1140
    }
1141
}
1142
 
1143
static enum return_value_convention
1144
sparc32_return_value (struct gdbarch *gdbarch, struct type *func_type,
1145
                      struct type *type, struct regcache *regcache,
1146
                      gdb_byte *readbuf, const gdb_byte *writebuf)
1147
{
1148
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1149
 
1150
  /* The psABI says that "...every stack frame reserves the word at
1151
     %fp+64.  If a function returns a structure, union, or
1152
     quad-precision value, this word should hold the address of the
1153
     object into which the return value should be copied."  This
1154
     guarantees that we can always find the return value, not just
1155
     before the function returns.  */
1156
 
1157
  if (sparc_structure_or_union_p (type)
1158
      || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
1159
    {
1160
      if (readbuf)
1161
        {
1162
          ULONGEST sp;
1163
          CORE_ADDR addr;
1164
 
1165
          regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1166
          addr = read_memory_unsigned_integer (sp + 64, 4, byte_order);
1167
          read_memory (addr, readbuf, TYPE_LENGTH (type));
1168
        }
1169
 
1170
      return RETURN_VALUE_ABI_PRESERVES_ADDRESS;
1171
    }
1172
 
1173
  if (readbuf)
1174
    sparc32_extract_return_value (type, regcache, readbuf);
1175
  if (writebuf)
1176
    sparc32_store_return_value (type, regcache, writebuf);
1177
 
1178
  return RETURN_VALUE_REGISTER_CONVENTION;
1179
}
1180
 
1181
static int
1182
sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
1183
{
1184
  return (sparc_structure_or_union_p (type)
1185
          || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16));
1186
}
1187
 
1188
static int
1189
sparc32_dwarf2_struct_return_p (struct frame_info *this_frame)
1190
{
1191
  CORE_ADDR pc = get_frame_address_in_block (this_frame);
1192
  struct symbol *sym = find_pc_function (pc);
1193
 
1194
  if (sym)
1195
    return sparc32_struct_return_from_sym (sym);
1196
  return 0;
1197
}
1198
 
1199
static void
1200
sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1201
                               struct dwarf2_frame_state_reg *reg,
1202
                               struct frame_info *this_frame)
1203
{
1204
  int off;
1205
 
1206
  switch (regnum)
1207
    {
1208
    case SPARC_G0_REGNUM:
1209
      /* Since %g0 is always zero, there is no point in saving it, and
1210
         people will be inclined omit it from the CFI.  Make sure we
1211
         don't warn about that.  */
1212
      reg->how = DWARF2_FRAME_REG_SAME_VALUE;
1213
      break;
1214
    case SPARC_SP_REGNUM:
1215
      reg->how = DWARF2_FRAME_REG_CFA;
1216
      break;
1217
    case SPARC32_PC_REGNUM:
1218
    case SPARC32_NPC_REGNUM:
1219
      reg->how = DWARF2_FRAME_REG_RA_OFFSET;
1220
      off = 8;
1221
      if (sparc32_dwarf2_struct_return_p (this_frame))
1222
        off += 4;
1223
      if (regnum == SPARC32_NPC_REGNUM)
1224
        off += 4;
1225
      reg->loc.offset = off;
1226
      break;
1227
    }
1228
}
1229
 
1230
 
1231
/* The SPARC Architecture doesn't have hardware single-step support,
1232
   and most operating systems don't implement it either, so we provide
1233
   software single-step mechanism.  */
1234
 
1235
static CORE_ADDR
1236
sparc_analyze_control_transfer (struct frame_info *frame,
1237
                                CORE_ADDR pc, CORE_ADDR *npc)
1238
{
1239
  unsigned long insn = sparc_fetch_instruction (pc);
1240
  int conditional_p = X_COND (insn) & 0x7;
1241
  int branch_p = 0;
1242
  long offset = 0;                       /* Must be signed for sign-extend.  */
1243
 
1244
  if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0)
1245
    {
1246
      /* Branch on Integer Register with Prediction (BPr).  */
1247
      branch_p = 1;
1248
      conditional_p = 1;
1249
    }
1250
  else if (X_OP (insn) == 0 && X_OP2 (insn) == 6)
1251
    {
1252
      /* Branch on Floating-Point Condition Codes (FBfcc).  */
1253
      branch_p = 1;
1254
      offset = 4 * X_DISP22 (insn);
1255
    }
1256
  else if (X_OP (insn) == 0 && X_OP2 (insn) == 5)
1257
    {
1258
      /* Branch on Floating-Point Condition Codes with Prediction
1259
         (FBPfcc).  */
1260
      branch_p = 1;
1261
      offset = 4 * X_DISP19 (insn);
1262
    }
1263
  else if (X_OP (insn) == 0 && X_OP2 (insn) == 2)
1264
    {
1265
      /* Branch on Integer Condition Codes (Bicc).  */
1266
      branch_p = 1;
1267
      offset = 4 * X_DISP22 (insn);
1268
    }
1269
  else if (X_OP (insn) == 0 && X_OP2 (insn) == 1)
1270
    {
1271
      /* Branch on Integer Condition Codes with Prediction (BPcc).  */
1272
      branch_p = 1;
1273
      offset = 4 * X_DISP19 (insn);
1274
    }
1275
  else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a)
1276
    {
1277
      /* Trap instruction (TRAP).  */
1278
      return gdbarch_tdep (get_frame_arch (frame))->step_trap (frame, insn);
1279
    }
1280
 
1281
  /* FIXME: Handle DONE and RETRY instructions.  */
1282
 
1283
  if (branch_p)
1284
    {
1285
      if (conditional_p)
1286
        {
1287
          /* For conditional branches, return nPC + 4 iff the annul
1288
             bit is 1.  */
1289
          return (X_A (insn) ? *npc + 4 : 0);
1290
        }
1291
      else
1292
        {
1293
          /* For unconditional branches, return the target if its
1294
             specified condition is "always" and return nPC + 4 if the
1295
             condition is "never".  If the annul bit is 1, set *NPC to
1296
             zero.  */
1297
          if (X_COND (insn) == 0x0)
1298
            pc = *npc, offset = 4;
1299
          if (X_A (insn))
1300
            *npc = 0;
1301
 
1302
          gdb_assert (offset != 0);
1303
          return pc + offset;
1304
        }
1305
    }
1306
 
1307
  return 0;
1308
}
1309
 
1310
static CORE_ADDR
1311
sparc_step_trap (struct frame_info *frame, unsigned long insn)
1312
{
1313
  return 0;
1314
}
1315
 
1316
int
1317
sparc_software_single_step (struct frame_info *frame)
1318
{
1319
  struct gdbarch *arch = get_frame_arch (frame);
1320
  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1321
  struct address_space *aspace = get_frame_address_space (frame);
1322
  CORE_ADDR npc, nnpc;
1323
 
1324
  CORE_ADDR pc, orig_npc;
1325
 
1326
  pc = get_frame_register_unsigned (frame, tdep->pc_regnum);
1327
  orig_npc = npc = get_frame_register_unsigned (frame, tdep->npc_regnum);
1328
 
1329
  /* Analyze the instruction at PC.  */
1330
  nnpc = sparc_analyze_control_transfer (frame, pc, &npc);
1331
  if (npc != 0)
1332
    insert_single_step_breakpoint (arch, aspace, npc);
1333
 
1334
  if (nnpc != 0)
1335
    insert_single_step_breakpoint (arch, aspace, nnpc);
1336
 
1337
  /* Assert that we have set at least one breakpoint, and that
1338
     they're not set at the same spot - unless we're going
1339
     from here straight to NULL, i.e. a call or jump to 0.  */
1340
  gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0);
1341
  gdb_assert (nnpc != npc || orig_npc == 0);
1342
 
1343
  return 1;
1344
}
1345
 
1346
static void
1347
sparc_write_pc (struct regcache *regcache, CORE_ADDR pc)
1348
{
1349
  struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
1350
 
1351
  regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc);
1352
  regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4);
1353
}
1354
 
1355
 
1356
/* Return the appropriate register set for the core section identified
1357
   by SECT_NAME and SECT_SIZE.  */
1358
 
1359
static const struct regset *
1360
sparc_regset_from_core_section (struct gdbarch *gdbarch,
1361
                                const char *sect_name, size_t sect_size)
1362
{
1363
  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1364
 
1365
  if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset)
1366
    return tdep->gregset;
1367
 
1368
  if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset)
1369
    return tdep->fpregset;
1370
 
1371
  return NULL;
1372
}
1373
 
1374
 
1375
static struct gdbarch *
1376
sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1377
{
1378
  struct gdbarch_tdep *tdep;
1379
  struct gdbarch *gdbarch;
1380
 
1381
  /* If there is already a candidate, use it.  */
1382
  arches = gdbarch_list_lookup_by_info (arches, &info);
1383
  if (arches != NULL)
1384
    return arches->gdbarch;
1385
 
1386
  /* Allocate space for the new architecture.  */
1387
  tdep = XZALLOC (struct gdbarch_tdep);
1388
  gdbarch = gdbarch_alloc (&info, tdep);
1389
 
1390
  tdep->pc_regnum = SPARC32_PC_REGNUM;
1391
  tdep->npc_regnum = SPARC32_NPC_REGNUM;
1392
  tdep->step_trap = sparc_step_trap;
1393
 
1394
  set_gdbarch_long_double_bit (gdbarch, 128);
1395
  set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad);
1396
 
1397
  set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS);
1398
  set_gdbarch_register_name (gdbarch, sparc32_register_name);
1399
  set_gdbarch_register_type (gdbarch, sparc32_register_type);
1400
  set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS);
1401
  set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read);
1402
  set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write);
1403
 
1404
  /* Register numbers of various important registers.  */
1405
  set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */
1406
  set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */
1407
  set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */
1408
 
1409
  /* Call dummy code.  */
1410
  set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
1411
  set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code);
1412
  set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call);
1413
 
1414
  set_gdbarch_return_value (gdbarch, sparc32_return_value);
1415
  set_gdbarch_stabs_argument_has_addr
1416
    (gdbarch, sparc32_stabs_argument_has_addr);
1417
 
1418
  set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue);
1419
 
1420
  /* Stack grows downward.  */
1421
  set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1422
 
1423
  set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc);
1424
 
1425
  set_gdbarch_frame_args_skip (gdbarch, 8);
1426
 
1427
  set_gdbarch_print_insn (gdbarch, print_insn_sparc);
1428
 
1429
  set_gdbarch_software_single_step (gdbarch, sparc_software_single_step);
1430
  set_gdbarch_write_pc (gdbarch, sparc_write_pc);
1431
 
1432
  set_gdbarch_dummy_id (gdbarch, sparc_dummy_id);
1433
 
1434
  set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc);
1435
 
1436
  frame_base_set_default (gdbarch, &sparc32_frame_base);
1437
 
1438
  /* Hook in the DWARF CFI frame unwinder.  */
1439
  dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg);
1440
  /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1441
     StackGhost issues have been resolved.  */
1442
 
1443
  /* Hook in ABI-specific overrides, if they have been registered.  */
1444
  gdbarch_init_osabi (info, gdbarch);
1445
 
1446
  frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind);
1447
 
1448
  /* If we have register sets, enable the generic core file support.  */
1449
  if (tdep->gregset)
1450
    set_gdbarch_regset_from_core_section (gdbarch,
1451
                                          sparc_regset_from_core_section);
1452
 
1453
  return gdbarch;
1454
}
1455
 
1456
/* Helper functions for dealing with register windows.  */
1457
 
1458
void
1459
sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum)
1460
{
1461
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
1462
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1463
  int offset = 0;
1464
  gdb_byte buf[8];
1465
  int i;
1466
 
1467
  if (sp & 1)
1468
    {
1469
      /* Registers are 64-bit.  */
1470
      sp += BIAS;
1471
 
1472
      for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1473
        {
1474
          if (regnum == i || regnum == -1)
1475
            {
1476
              target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1477
 
1478
              /* Handle StackGhost.  */
1479
              if (i == SPARC_I7_REGNUM)
1480
                {
1481
                  ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1482
                  ULONGEST i7;
1483
 
1484
                  i7 = extract_unsigned_integer (buf + offset, 8, byte_order);
1485
                  store_unsigned_integer (buf + offset, 8, byte_order,
1486
                                          i7 ^ wcookie);
1487
                }
1488
 
1489
              regcache_raw_supply (regcache, i, buf);
1490
            }
1491
        }
1492
    }
1493
  else
1494
    {
1495
      /* Registers are 32-bit.  Toss any sign-extension of the stack
1496
         pointer.  */
1497
      sp &= 0xffffffffUL;
1498
 
1499
      /* Clear out the top half of the temporary buffer, and put the
1500
         register value in the bottom half if we're in 64-bit mode.  */
1501
      if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1502
        {
1503
          memset (buf, 0, 4);
1504
          offset = 4;
1505
        }
1506
 
1507
      for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1508
        {
1509
          if (regnum == i || regnum == -1)
1510
            {
1511
              target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1512
                                  buf + offset, 4);
1513
 
1514
              /* Handle StackGhost.  */
1515
              if (i == SPARC_I7_REGNUM)
1516
                {
1517
                  ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1518
                  ULONGEST i7;
1519
 
1520
                  i7 = extract_unsigned_integer (buf + offset, 4, byte_order);
1521
                  store_unsigned_integer (buf + offset, 4, byte_order,
1522
                                          i7 ^ wcookie);
1523
                }
1524
 
1525
              regcache_raw_supply (regcache, i, buf);
1526
            }
1527
        }
1528
    }
1529
}
1530
 
1531
void
1532
sparc_collect_rwindow (const struct regcache *regcache,
1533
                       CORE_ADDR sp, int regnum)
1534
{
1535
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
1536
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1537
  int offset = 0;
1538
  gdb_byte buf[8];
1539
  int i;
1540
 
1541
  if (sp & 1)
1542
    {
1543
      /* Registers are 64-bit.  */
1544
      sp += BIAS;
1545
 
1546
      for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1547
        {
1548
          if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1549
            {
1550
              regcache_raw_collect (regcache, i, buf);
1551
 
1552
              /* Handle StackGhost.  */
1553
              if (i == SPARC_I7_REGNUM)
1554
                {
1555
                  ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1556
                  ULONGEST i7;
1557
 
1558
                  i7 = extract_unsigned_integer (buf + offset, 8, byte_order);
1559
                  store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie);
1560
                }
1561
 
1562
              target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1563
            }
1564
        }
1565
    }
1566
  else
1567
    {
1568
      /* Registers are 32-bit.  Toss any sign-extension of the stack
1569
         pointer.  */
1570
      sp &= 0xffffffffUL;
1571
 
1572
      /* Only use the bottom half if we're in 64-bit mode.  */
1573
      if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1574
        offset = 4;
1575
 
1576
      for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1577
        {
1578
          if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1579
            {
1580
              regcache_raw_collect (regcache, i, buf);
1581
 
1582
              /* Handle StackGhost.  */
1583
              if (i == SPARC_I7_REGNUM)
1584
                {
1585
                  ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1586
                  ULONGEST i7;
1587
 
1588
                  i7 = extract_unsigned_integer (buf + offset, 4, byte_order);
1589
                  store_unsigned_integer (buf + offset, 4, byte_order,
1590
                                          i7 ^ wcookie);
1591
                }
1592
 
1593
              target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1594
                                   buf + offset, 4);
1595
            }
1596
        }
1597
    }
1598
}
1599
 
1600
/* Helper functions for dealing with register sets.  */
1601
 
1602
void
1603
sparc32_supply_gregset (const struct sparc_gregset *gregset,
1604
                        struct regcache *regcache,
1605
                        int regnum, const void *gregs)
1606
{
1607
  const gdb_byte *regs = gregs;
1608
  int i;
1609
 
1610
  if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1611
    regcache_raw_supply (regcache, SPARC32_PSR_REGNUM,
1612
                         regs + gregset->r_psr_offset);
1613
 
1614
  if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1615
    regcache_raw_supply (regcache, SPARC32_PC_REGNUM,
1616
                         regs + gregset->r_pc_offset);
1617
 
1618
  if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1619
    regcache_raw_supply (regcache, SPARC32_NPC_REGNUM,
1620
                         regs + gregset->r_npc_offset);
1621
 
1622
  if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1623
    regcache_raw_supply (regcache, SPARC32_Y_REGNUM,
1624
                         regs + gregset->r_y_offset);
1625
 
1626
  if (regnum == SPARC_G0_REGNUM || regnum == -1)
1627
    regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL);
1628
 
1629
  if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1630
    {
1631
      int offset = gregset->r_g1_offset;
1632
 
1633
      for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1634
        {
1635
          if (regnum == i || regnum == -1)
1636
            regcache_raw_supply (regcache, i, regs + offset);
1637
          offset += 4;
1638
        }
1639
    }
1640
 
1641
  if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1642
    {
1643
      /* Not all of the register set variants include Locals and
1644
         Inputs.  For those that don't, we read them off the stack.  */
1645
      if (gregset->r_l0_offset == -1)
1646
        {
1647
          ULONGEST sp;
1648
 
1649
          regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1650
          sparc_supply_rwindow (regcache, sp, regnum);
1651
        }
1652
      else
1653
        {
1654
          int offset = gregset->r_l0_offset;
1655
 
1656
          for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1657
            {
1658
              if (regnum == i || regnum == -1)
1659
                regcache_raw_supply (regcache, i, regs + offset);
1660
              offset += 4;
1661
            }
1662
        }
1663
    }
1664
}
1665
 
1666
void
1667
sparc32_collect_gregset (const struct sparc_gregset *gregset,
1668
                         const struct regcache *regcache,
1669
                         int regnum, void *gregs)
1670
{
1671
  gdb_byte *regs = gregs;
1672
  int i;
1673
 
1674
  if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1675
    regcache_raw_collect (regcache, SPARC32_PSR_REGNUM,
1676
                          regs + gregset->r_psr_offset);
1677
 
1678
  if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1679
    regcache_raw_collect (regcache, SPARC32_PC_REGNUM,
1680
                          regs + gregset->r_pc_offset);
1681
 
1682
  if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1683
    regcache_raw_collect (regcache, SPARC32_NPC_REGNUM,
1684
                          regs + gregset->r_npc_offset);
1685
 
1686
  if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1687
    regcache_raw_collect (regcache, SPARC32_Y_REGNUM,
1688
                          regs + gregset->r_y_offset);
1689
 
1690
  if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1691
    {
1692
      int offset = gregset->r_g1_offset;
1693
 
1694
      /* %g0 is always zero.  */
1695
      for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1696
        {
1697
          if (regnum == i || regnum == -1)
1698
            regcache_raw_collect (regcache, i, regs + offset);
1699
          offset += 4;
1700
        }
1701
    }
1702
 
1703
  if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1704
    {
1705
      /* Not all of the register set variants include Locals and
1706
         Inputs.  For those that don't, we read them off the stack.  */
1707
      if (gregset->r_l0_offset != -1)
1708
        {
1709
          int offset = gregset->r_l0_offset;
1710
 
1711
          for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1712
            {
1713
              if (regnum == i || regnum == -1)
1714
                regcache_raw_collect (regcache, i, regs + offset);
1715
              offset += 4;
1716
            }
1717
        }
1718
    }
1719
}
1720
 
1721
void
1722
sparc32_supply_fpregset (struct regcache *regcache,
1723
                         int regnum, const void *fpregs)
1724
{
1725
  const gdb_byte *regs = fpregs;
1726
  int i;
1727
 
1728
  for (i = 0; i < 32; i++)
1729
    {
1730
      if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1731
        regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1732
    }
1733
 
1734
  if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1735
    regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1736
}
1737
 
1738
void
1739
sparc32_collect_fpregset (const struct regcache *regcache,
1740
                          int regnum, void *fpregs)
1741
{
1742
  gdb_byte *regs = fpregs;
1743
  int i;
1744
 
1745
  for (i = 0; i < 32; i++)
1746
    {
1747
      if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1748
        regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1749
    }
1750
 
1751
  if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1752
    regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1753
}
1754
 
1755
 
1756
/* SunOS 4.  */
1757
 
1758
/* From <machine/reg.h>.  */
1759
const struct sparc_gregset sparc32_sunos4_gregset =
1760
{
1761
 
1762
  1 * 4,                        /* %pc */
1763
  2 * 4,                        /* %npc */
1764
  3 * 4,                        /* %y */
1765
  -1,                           /* %wim */
1766
  -1,                           /* %tbr */
1767
  4 * 4,                        /* %g1 */
1768
  -1                            /* %l0 */
1769
};
1770
 
1771
 
1772
/* Provide a prototype to silence -Wmissing-prototypes.  */
1773
void _initialize_sparc_tdep (void);
1774
 
1775
void
1776
_initialize_sparc_tdep (void)
1777
{
1778
  register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init);
1779
}

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